E2E1022-27-Y4 This version: Jan. 1998 MSM80C48/49/50, MSM80C35/39/40 Previous version: Nov. 1996 ¡ Semiconductor MSM80C48/49/50 MSM80C35/39/40 ¡ Semiconductor CMOS 8-Bit Microcontroller GENERAL DESCRIPTION The OKI MSM80C48/MSM80C49/MSM80C50 are 8-bit, low-power, high-performance microcontrollers implemented in silicon-gate complementary metal-oxide semiconductor technology. Integrated within these chips are 8K/16K/32K bits of mask program ROM, 512/1024/2048 bits of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Program memory and data paths are byte wide. Eleven new instructions have been added to the NMOS version's instruction set, thereby optimizing power down, port data transfer, decrement and port float functions. Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages QFP (GSK). FEATURES • Lower power consumption enabled by CMOS silicon gate process • Completely static operation • Improved power-down feature • Instruction cycle : 1.36 ms (11 MHz) VCC=4.5 to 6.0 V (MSM80C48/49) 2.5 ms (6 MHz) VCC=3.5 to 6.0 V (MSM80C50) • 111 instructions • All instructions are usable even during execution of external ROM instructions. • Operation facility Addition, logical operations, and decimal adjust • Program memory (ROM) : 1K words ¥ 8 bits (MSM80C48) : 2K words ¥ 8 bits (MSM80C49) : 4K words ¥ 8 bits (MSM80C50) • Data memory (RAM) : 64 words ¥ 8 bits (MSM80C48) : 128 words ¥ 8 bits (MSM80C49) : 256 words ¥ 8 bits (MSM80C50) • Two sets of working registers • External and timer interrupts • Two test inputs • Built-in 8-bit timer counter • Extendable external memory and I/O ports • I/O port Input-output port : 2 ports ¥ 8 bits Data bus input-output port : 1 port ¥ 8 bits • Single-step execution function • Wide range of operating voltage, from + 2.5 V to + 6 V of VCC • High noise margin action • Compatible with Intel's 8048, 8049 and 8050 • Package 40-pin plastic DIP (DIP40-P-600-2.54) : (MSM80C48-¥¥¥RS) (MSM80C49-¥¥¥RS) (MSM80C50-¥¥¥RS) (MSM80C35RS) (MSM80C39RS) (MSM80C40RS) 44-pin plastic QFP(QFP44-P-910-0.80-2K) : (MSM80C48-¥¥¥GS-2K) (MSM80C49-¥¥¥GS-2K) (MSM80C50-¥¥¥GS-2K) (MSM80C35GS-2K) (MSM80C39GS-2K) (MSM80C40GS-2K) ¥¥¥ indicates the code number. 1/20 EA XTAL1 XTAL2 ALE PSEN CONTROL AND TIMING SS TIMER/EVENT COUNTER (8) 2 or 3 OSCILLATOR PROM/ PROGRAM XTAL EXPANDER MEMORY STROBE ENABLE ADDRESS LATCH, SINGLE INITIALIZE CPU MEMORY DATA LATCH STEP SEPARATE STROBE CYCLE CLOCK RESET PROG DECIMAL ADJUST ARITHMETIC LOGIC UNIT (8) FLAGS TEST1 4 HIGHER PROGRAM COUNTER (4) ∏480 TEMP REG (8) 8 RD READ STROBE (8) WRITE STROBE WR CONDITIONAL BRANCH LOGIC LOWER PROGRAM COUNTER (8) PROGRAM MEMORY (ROM) 1K¥8bits MSM80C48RS 2K¥8bits MSM80C49RS 4K¥8bits MSM80C50RS ACC Bit TEST TEST0 RAM ADDRESS TEST1 REGISTER INT FLAG0 FLAG1 TIMER FLAG CARRY ACC INSTRUCTION REGISTER OPTIONAL SECOND REGISTER BANK DATA STORE 8-LEVEL STACK REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 MULTIPLEXER BUS LATCH AND LOW PC TEMP REGISTER PLA DATA MEMORY (RAM) 64¥8 bits MSM80C48RS 128¥8 bits MSM80C49RS 256¥8 bits MSM80C50RS DECODER INTERRUPT INT ACCUMULATOR LATCH (8) ACCUMULATOR (8) 4 4 OSC FREQ PORT2 LATCH (HIGH4) PORT2 LATCH (LOW4) AND EXPANDER PORT I/O PORT2 BUS BUFFER 8 (PORT 2) PORT1 BUS BUFFER AND LATCH BUS BUFFER 8 8 (PORT 1) (DATA BUS PORT) ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 BLOCK DIAGRAM 2/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 P17 RD 8 33 P16 PSEN 9 32 P15 WR ALE 10 11 31 30 P14 DB0 12 29 P12 DB1 13 28 P11 DB2 14 27 P10 DB3 15 26 VDD DB4 16 25 PROG DB5 17 DB6 18 24 23 P23 P22 DB7 19 22 P21 VSS 20 21 P20 P13 P12 4 P13 5 P14 6 P15 7 NC 8 P16 9 P17 10 P24 11 34 DB4 34 3 32 DB2 31 DB1 30 DB0 29 ALE 28 WR 27 PSEN 26 RD 25 EA 24 INT 23 SS RESET 22 7 2 P11 36 DB6 EA P10 33 DB3 NC 21 P24 XTAL2 20 35 37 DB7 6 1 38 VSS INT VDD T0 18 P25 XTAL1 19 36 39 P20 5 40 P21 SS T1 16 P26 VCC 17 P27 37 41 P22 38 4 42 P23 3 P27 15 XTAL2 RESET 43 PROG T1 P26 14 VCC 39 P25 13 40 2 44 NC 1 NC 12 T0 XTAL1 35 DB5 PIN CONFIGURATION (TOP VIEW) NC: No-connection pin 40-Pin Plastic DIP 44-Pin Plastic QFP 3/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 PIN DESCRIPTIONS Symbol P10-P17 (PORT 1) Type I/O Description 8-bit quasi-bidirectional port P20-P27 (PORT 2) I/O 8-bit quasi-bidirectional port The high-order four bits of external program memory addresses can be output from P2.0-P2.3, to which the I/O expander MSM82C43RS may also be connected. DB0-DB7 (BUS) I/O Bidirectional port The low-order eight bits of external program memory address can be output from this port, and the addressed instruction is fetched under the control of PSEN signal. Also, the external data memory address is output, and data is read and written synchronously using RD and WR signals. The port can also serve as either a statically latched output port or a non-latching input port. T0 (Test 0) I/O The input can be tested with the conditional jump instructions JT0 and JNT0. The execution of the ENT0 CLK instruction causes a clock output. T1 (Test 1) I The input can be tested with the conditional jump instructions JT1 and JNT1. The execution of a STRT CNT instruction causes an internal counter input. INT (Interrupt) I Interrupt input. If interrupt is enabled, INT input initiates an interrupt. Interrupt is disabled after a reset. Also testable with a JNI instruction. Can be used to terminate the power-down mode. (Active "0" level) RD (Read) O A signal to read data from external data memory. (Active "0" level) WR (Write) O A signal to write data to external data memory. (Active "0" level) ALE Address & Data Latch Clock O This signal is generated in each cycle. It may be used as a clock output. External data memory or external program memory is addressed upon the falling edge. For the external ROM, this signal is used to latch the bus port data upon the ALE signal rise-up after the execution of the OUTL BUS, A instruction. PSEN Program Store Enable O A signal to fetch an instruction from external program memory (Active "0" level) RESET I RESET input initialize the processor. (Active "0" level) Used to terminate the power-down mode. SS (Single Step) I A program is executed step by step. This pin can also be used to control internal oscillation when the power-down mode is reset. (Active "0" level) EA (External Access) I When held at high level, all instructions are fetched from external memory. (Active "1" level) PROG (Expander Strobe) O This output strobes the MSM82C43RS I/O expander. 4/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 PIN DESCRIPTIONS (Continued) Symbol XTAL1 (Crystal 1) Type I Description One side of the internal crystal oscillator. An external clock can also be input. XTAL2 (Crystal 2) O Other side of the internal crystal oscillator. VCC — Power supply pin VDD — Standby control input. Normally, "1" level. When set to "0" level, oscillation is stopped and prosessor goes into standby mode. VSS — GND Note: A minimum of two machine cycles are required in RESET pulse duration under the specified power supply and stable oscillator frequency. 5/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage Storage Temperature Symbol Condition Rating Unit VCC Ta=25°C –0.5 to 7 V VI Ta=25°C –0.3 to VCC +0.5 V TSTG — –65 to +150 °C RECOMMENDED OPERATING CONDITIONS Symbol Condition Range Unit Supply Voltage Parameter VCC fOSC=DC to 11MHz* +2.5 to +6 V Ambient Temperature Ta Fan Out * N — –40 to +85 °C MOS load 10 — TTL load 1 — Minimum operating voltage is dependent on frequency. 6/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 MSM80C48/49/50 guaranteed operating range Ta=–40 to +85°C (msec) 100 Cycle Time (tCY) Guaranteed Operating Range 1.5MHz 10 MSM80C40/80C50 6MHz 11MHz MSM80C35/80C48/80C39/80C49 1 2 3 4 5 6 (V) Supply Voltage (VCC) 7/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter (VCC=5 V±10%, Ta=–40 to +85°C) Mea- Symbol Condition "L" Input Voltage VIL — –0.5 — 0.13 VCC V "H" Input Voltage *1 VIH — 0.4 VCC — VCC V — 0.7 VCC — VCC V — — 0.45 V Min. Typ. Max. Unit suring Circuit "H" Input Voltage *2 VIH "L" Output Voltage *3 VOL IOL=2 mA "L" Output Voltage *4 VOL IOL=1.6 mA — — 0.45 V "H" Output Voltage *3 VOH IOH=–400 mA 0.75 VCC — — V "H" Output Voltage *4 VOH IOH=–50 mA 0.75 VCC — — V "H" Output Voltage *3 VOH IOH=–20 mA 0.93 VCC — — V "H" Output Voltage *4 VOH IOH=–10 mA 0.93 VCC — — V Input Leakage Curent IIL VSS £ VIN £ VCC — — ±5 mA 2 Output Leakage Current *5 IOL VSS £ VO £ VCC — — ±5 mA 3 RESET Input current IR SS Input current *6 ISS P1, P2 input current IP1, IP2 Power Down Mode Standby Current ICCS Power Supply Current (Halt Mode) Power Supply Current ICC ICC VIN=0.7 VCC –20 –50 –80 mA VIN=0.13 VCC –3 –8 –15 mA Pull-up (VIN=VIL) 20 50 80 mA Pull-down (VIN=VIH) –6 –15 –25 mA VIN=VIH –300 –600 –900 mA VIN=VIL At hardware power down *7 Ta=25°C, VCC=2.0 V At HLTS execution *7 Ta=25°C, VCC=2.0 V VCC=4 V, f=1 MHz –10 –40 –80 mA — — 10 — — 10 — — 0.5 VCC=4 V, f=6 MHz — — 1.0 VCC=4 V, f=11 MHz — — 2.0 VCC=5 V, f=1 MHz — — 1.0 1 2 2 mA VCC=5 V, f=6 MHz — — 2.0 VCC=5 V, f=11 MHz — — 3.0 VCC=6 V, f=1 MHz — — 1.5 VCC=6 V, f=6 MHz — — 3.0 VCC=6 V, f=11 MHz — — 5.0 VCC=4 V, f=1 MHz — — 1.5 VCC=4 V, f=6 MHz — — 5.0 VCC=4 V, f=11 MHz — — 10 VCC=5 V, f=1 MHz — — 2.5 VCC=5 V, f=6 MHz — — 7.5 VCC=5 V, f=11 MHz — — 15 VCC=6 V, f=1 MHz — — 5.0 VCC=6 V, f=6 MHz — — 10 VCC=6 V, f=11 MHz — — 20 mA 4 mA 8/20 ¡ Semiconductor *1 *2 *3 *4 *5 *6 *7 MSM80C48/49/50, MSM80C35/39/40 This does not apply to RESET, XTAL1, XTAL2, VDD, and EA. RESET, XTAL1, XTAL2, VDD, and EA. BUS, RD, WR, PSEN, ALE, PROG Other outputs High-impedance state This operates as a pull-down resistor when the oscillation is stopped in the HLTS or VDD power-down mode and as a pull-up resistor in other states. This does not contain flow out current from I/O ports and signal pins. 9/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 AC Characteristics (VCC=2.5V to 6V (*1), Ta=–40 to +85°C) Parameter VCC=5 V±10% Variable clock Symbol 11 MHz Clock 0 to 11 MHz Min. Max. Min. Max. ALE Pulse Width Unit tLL 150 — 3.5t–170 — ns Address Setup Time (up to ALE) tAL 70 — 2t–110 — ns Address Hold Time (from ALE) tLA 50 — t–40 — ns Bus Port Latch Data Setup Time (up to ALE Rising Edge) tBL 110 — 2.5t –115 — ns Bus Port Latch Data Hold Time (from ALE Rising Edge) tLB 90 — 1.5 t–45 — ns Control Pulse Width (RD, WR) tCC1 480 — 7t–155 — ns Control Pulse Width (PSEN) tCC2 350 — 6t–200 — ns Data Setup Time (before WR) tDW 390 — 6t–155 — ns Data Hold after Time (after WR) tWD 40 — 2t–140 — ns Data Hold Time (after RD, PSEN) tDR 0 110 0 1.5t–30 ns RD to Data-in tRD1 — 350 — 5t–265 ns PSEN to Data-in tRD2 — 190 — 5t–265 ns Address Setup to WR tAW 300 — 6t–245 — ns Address Setup to Data-in tAD1 — 730 — 12t–360 ns Address Setup to Instruction tAD2 — 460 — 8t–265 ns Address Float to RD, WR tAFC1 140 — 2t–40 — ns Address Float to PSEN tAFC2 10 — 10 — ns Control Pulse Setup Time from ALE (PSEN) tLAFC2 60 — t–30 — ns Control Pulse Setup Time from ALE (RD, WR) tLAFC1 200 — 3t–75 — ns Control Pulse up to ALE (RD, WR, PROG) tCA1 50 — 1.5t–85 — ns Control Pulse up to ALE (PSEN) tCA2 320 — 4.5t–90 — ns Port Control Setup Time (up to PROG Falling Edge) tCP 50 — 2t–130 — ns Port Control Hold Time (from PROG Falling Edge) tPC 100 — 4t–260 — ns PROG to Input Data Valid tPR — 650 — 9t–170 ns Input Data Hold Time tPF 0 140 0 1.5t ns Output Data Setup Time tDP 250 — 6t–290 — ns Output Data Hold Time tPD 40 — 3t–230 — ns PROG Pulse Width tPP 700 — 10t–210 — ns Port 2 I/O Setup Time tPL 160 — 4.5–250 — ns Port 2 I/O Hold Time tLP 15 — 1.5t–120 — ns Port Output Data (from ALE) tPV — 510 — 4t+145 ns tOPRR 270 — 3t — ns tCY 1.36 — 15t — ms T0 Cycle Instruction Execution Time Note : Control output : CL=80pF Bus output : CL=150pF [for 20 pF (tAL, tAFC1, tAFC2)] *1 Minimum operating voltage is dependent on frequency. 10/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 Measuring circuits 1 2 A IO V VCC OUTPUT VIL (*1) INPUTS (*3) INPUTS VIH (*2) OUTPUT VCC A GND GND 3 4 A A (*3) VIL GND OUTPUT VIL VIH INPUTS INPUTS (*3) VCC OUTPUT VCC VIH GND 5 VIL (*3) INPUTS VIH VIH (*2) OUTPUT VCC VIL I CL GND VOH VOL O O VOH VOL tXXX tXXX *1 This is repeated for each specified input pin. *2 This is repeated for each specified output pin. *3 Input logic for setting the specified state 11/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 Timing Diagram Instruction fetch (from external program memory) tCY tLL ALE tAFC tCC PSEN tAL tLA BUS LATCH DATA tRD ADDRESS FLOATING tDR INSTRUCTION tBL tLB LATCH DATA ADDRESS tAD Read (from external data memory) ALE tCC RD tAFC tRD BUS FLOATING ADDRESS tDR DATA FLOAT- ADDRESS ING tAD 12/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 Write (to external memory) ALE tCC WR tAW BUS ADDRESS tDW FLOATING tWD DATA ADDRESS Low-order 4 bits input/output of port 2 when expanded I/O port is used (in external program memory access mode) ALE tPL P20-3 (Output mode) PCH tLP PORT DATA tDP PORT CONTROL tPD OUTPUT DATA tPF tPR P20-3 (Input mode) PCH PORT DATA INPUT DATA PORT CONTROL tCP tPC tPP PROG 13/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 FUNCTIONAL DESCRIPTION Added Functions of MSM80C48, MSM80C49 and MSM80C50 The MSM80C48, MSM80C49 and MSM80C50 are basically incorporated with the capabilities of Intel's 8048, 8049, and 8050 plus the following new functions: 1. Power-Down Mode Enhancements 1.1 Power-down by software (1) Clock (See item 4, "Power-down mode", for details.) a. Crystal oscillator halt (HLTS instruction) Power requirements can be minimized. b. Clock supply halt (HALT instruction) Restart is accomplished without oscillator wait. (2) I/O ports I/O port floating instructions Power consumption resulting from inputs/outputs can be minimized with FLT and FLTT instructions. Port floating is cancelled by executing FRES instruction, "0" level at INT pin or "0" level at RESET pin. (3) Six types of power-down can be done by a combination of HLTS/HALT and FLT/FLTT instructions. 1.2 Power-down by hardware (See 4.3, Power-down mode by VDD pin utilization for details.) Crystal oscillators can be halted by controlling the VDD pin, thereby floating all I/O ports for minimum power consumption. 2. Additional Instructions (11) HLTS MOV A, P2 HALT MOVP1, @ R3 FLT MOVP1 P, @R3 FLTT DEC @Rr FRES DJNZ @ Rr, addr MOV A, P1 3. Improved Uses of BUS P0-7, P10-7, P20-7, and SS pins 3.1 BUS P0-7 The MSM80C48, MSM80C49, and MSM80C50 remove the limitation on the use of OUTL BUS, A instructions during the external ROM access mode by having an independent data latch and external ROM mode address latch in BUS P0-7. Consequently, there is no need to relocate bus port instructions when in the external ROM access mode. 3.2 P10-7 and P20-7 The MSM80C48, MSM80C49 and MSM 80C50 are designed to minimize power consumption when P10-7 and P20-7 are used as input/output ports, to maximize the performance of CMOS. When these ports are used as output ports, the acceleration circuit is actuated only when 14/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 output data changes from "0" to "1", thus speeding up the rise time of the output signals. When these ports are used as input ports, the internal pull-up resistor becomes approximately 9 kW when input data is "1". The internal pull-up resistor rises to approximately 100 kW when input data is "0". Thus, a high noise margin can be obtained by selecting the impedance and thus the outflow of current is minimized whenever these ports are used as output or input ports. 3.3 Clock generation control via the SS pin When the crystal oscillator is halted in the HLTS or hardware power-down mode, the SS pin is pulled down by a resistor of 20 to 50 kW, while its internal pull-up resistor of 200 to 500kW is isolated from VCC. When the power-down mode is cancelled, the internal resistor of the SS pin is changed from pull-down to pull-up. Consequently, the CPU can be halted for any period of time until the crystal oscillator resumes normal oscillation when a capacitor is connected to the SS pin. 4. Power-Down Mode The MSM80C48, MSM80C49, and MSM80C50 power-down mode can be enabled in two different ways through software by a combination of clock control and port floating instructions, and through hardware by control of the VDD pin. 4.1 Software power-down mode Power-down mode can be done by a combination of the following instructions. (1) HALT (clock supply halt to control circuit) Instruction code : 0 0 0 0 0 0 0 1 Description : Although crystal oscillator operation is continued, the clock supply to the CPU control circuit is halted and CPU operations are suspended. When cancelling this software mode, restart is accomplished without oscillator wait. (2) HLTS (oscillation stop) Instruction code : 1 0 0 0 0 0 1 0 Description : The oscillator operation is halted and CPU operations are suspended. In cancelling this power down mode, connecting a capacitor to the SS pin enables a reasonable wait period to be accomplished before normal operation is resumed. [Except in the case of using the RESET pin] (3) FLT (floating P10-7, P20-7, and BP0-7) Instruction code : 1 0 1 0 0 0 1 0 Description : Internal ROM mode External ROM mode P1 Floating Floating P2 Floating P20-3 operation BP Floating Operation 15/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 Details of IC pin status as a result of executing the FLT instruction are shown in the above table. (4) FLTT (floating of all output pins) Instruction code : 1 1 0 0 0 0 1 0 Description : Internal ROM mode External ROM mode ALE Floating Operation PSEN Floating Operation PROG Floating Floating WR Floating Floating PD Floating Floating T0 OUT Floating Floating P1 Floating Floating P2 Floating P20-3 operation BP Floating Operation XTAL Operation Operation Details of IC pin status as a result of executing the FLTT instruction are shown in above Table. Example 1 : Power-down mode accomplished by stopping oscillation. m Can be set by execution of HLTS [82H] instruction. Example 2 : Power-down mode accomplished by stopping the clock supply to the CPU control circuit. m Can be set by execution of HALT [01H] instruction. Example 3 : Power-down mode by floating of P10-7, P20-7 and BP0-7, and subsequent stopping of CPU oscillation. m Can be set by first executing the FLT [A2H] instruction, followed by the HLTS [82H] instruction. Example 4 : Power-down mode by floating P10-7, P20-7 and BP0-7, and then stopping the clock supply to the CPU control circuit. m Can be set by first executing the FLT [A2H] instruction, and then the HALT [01H] instruction. Example 5 : Power-down mode by floating all output pins, followed by stopping oscillation. m Can be set by first executing the FLTT [C2H] instruction followed by execution of the HLTS [82H] instruction. Example 6 : Power-down mode by floating all output pins, followed by stopping of the clock supply to the CPU control circuit. m Can be set by first executing the FLTT [C2H] instruction, followed by execution of the HALT [01H] instruction. Connect the pull-up resistor or pull-down resistor to port pin and fix the output port pin level to either 1or 0 when output port is set to floating. 16/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 4.2 Cancellation of software power-down mode The power-down mode status outlined above in examples 1 to 6 can be cancelled by using either the interrupt pin or the RESET pin. (1) Use of the INT pin during external interrupt enable mode (i.e. following execution of EN I instruction). m The clock generator is activated and the CPU is started up when a "0" level is applied to the INT pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, an external interrupt is generated, and execution proceeds from address 3. If, however, the power-down is entered during the interrupt processing routine, execution resumes just after the power-down instruction. (2) Use of the INT pin during external interrupt disable mode (i.e. following execution of DIS I instruction or hardware reset) m The clock generator is activated and the CPU is started up when a "0" level is applied to the INT pin. When "0" level is maintained until the occurrence of at least 2 ALE output signals, execution is resumed just after the power-down instruction. (3) Use of the RESET pin m The clock generator is activated and the CPU started up when a "0" level is applied to the RESET pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, the CPU is reset and execution proceeds from address 0. In case cancellation is done in oscillation stop mode, the "0" level must be input to the RESET pin until oscillation is stabilized. 17/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 4.3 Hardware power-down mode In the MSM80C48, MSM80C49 and MSM80C50, forcing the level at the VDD pin to a "0" during either external ROM or internal ROM mode results in suspension of the oscillator function and subsequent floating (high impedance) of all the I/O pins except the RESET, SS and XTAL 1/2 pins. The CPU is thereby stopped while maintaining internal status. 4.4 Cancellation of hardware power-down mode (1) Use of RESET pin m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "0" level is input to the RESET pin. If this "0" level is kept applied to the RESET pin until oscillation become stable, the CPU will be reset and will start executing from address 0. (2) Use of the INT pin during external interrupt enable status (i.e. following execution of EN I instruction) m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "0" level is applied to the INT pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, an external interrupt is generated, and execution starts from address 3. However, if the power-down mode is started during an interrupt processing routine, execution will be continued on the next instruction after the present instruction. (3) Use of the INT pin during external interrupt disable mode (i.e. following excution of DIS I instruction or hardware reset) m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "0" level is applied to the INT pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, execution is continued on the next instruction after the present instruction. (4) Use of VDD pin only m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "1" level is also applied to both the RESET and INT pins. In this case, execution is resumed from the stopped position. 18/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 PACKAGE DIMENSIONS (Unit : mm) DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/20 ¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40 (Unit : mm) QFP44-P-910-0.80-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 20/20