OKI M6242B

¡ Semiconductor
MSM6242B
¡ Semiconductor
MSM6242B
DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR
DESCRIPTION
The MSM6242B is a silicon gate CMOS Real
Time Clock/Calendar for use in direct busconnection Microprocessor/Microcomputer
applications. An on-chip 32.768 KHz crystal
oscillator time base is divided to provide addressable 4-bit I/O data for SECONDS,
MINUTES, HOURS, DAY OF WEEK, DATE,
MONTH and YEAR. Data access is controlled
by 4-bit address, chip selects (CSO, CS1),
WRITE, READ, and ALE. Control Registers
D, E and F provide for 30 SECOND error
adjustment, INTERRUPT REQUEST (IRQ
FLAG) and BUSY status bits, clock STOP,
HOLD, and RESET FLAG bits, 4 selectable
INTERRUPTS rates are available at the STD.P
(STANDARD PULSE) output utilizing Control Register inputs T0, T1 and the ITRPT/
STND (INTERRUPT/STANDARD). Masking of the interrupt output (STD.P) can be
accomplished via the MASK bit. The
MSM6242B can operate in a 12/24 hour format and Leap Year timing is automatic.
The MSM6242B normally operates from a 5V
±10% supply at –40 to 85°C. Battery backup
operation down to 2.0V allows continuation
of time keeping when main power is off. The
MSM6242B is offered in a 18-pin plastic DIP
and a 24-pin plastic Small Outline package.
FEATURES
DIRECT MICROPROCESSOR/MICROCONTROLLER BUS CONNECTION
TIME
23:59:59
MONTH
DATE
12
31
• 4-bit data bus
• 4-bit address bus
• READ, WRITE, ALE and CHIP SELECT
INPUTS
• Status registers – IRQ and BUSY
• Selectable interrupt outputs – 1/64
second, 1 second, 1 minute, 1 hour
• Interrupt masking
• 32.768 KHz crystal controlled operation
YEAR
80
DAY OF WEEK
7
•
•
•
•
•
•
12/24 hour format
Auto leap year
±30 second error correction
Single 5V supply
Battery backup down to VDD = 2.0V
Low power dissipation:
20µW max at VDD = 2V
150µW max at VDD = 5V
• 18 pin Plastic DIP (DIP18-P-300)
• 24 Pin-V Plastic SOP (SOP24-P-430-VK)
23
MSM6242B
¡ Semiconductor
FUNCTIONAL BLOCK DIAGRAM
XT
XT
32.768KHz
OSC
1 Hz
COUNTER
RESET STOP 30 ADJ HOLD BUSY
bit
bit
bit bit
bit
GATE
A3
A2
A1
A0
CS0
ALE
DECODER
GATE
WR
RD
GATE & LATCH
30 sec
ADJ bit
D3
D2
D1
D0
S1 S10
MI1 MI10
H1 H10
D1 D10
MO1MO10
Y1 Y10
S1
S
CF
CS1
24/12bit
CD
CE
CF
W
64Hz
1-sec carry
1-min carry
1-hour carry
STDP
• S1~W~Y10 are time counter register
• C0~CF are control register
PIN CONFIGURATION
STD.P
1
18
VDD
CS0
2
17
XT
ALE
3
16
XT
A0
4
15
CS1
A1
5
14
D0
A2
6
13
D1
A3
7
12
D2
RD
8
11
D3
GND
9
10
WR
18 pin Plastic DIP
24
STD.P
CS0
NC
ALE
A0
NC
A1
NC
A2
A3
RD
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24 pin Plastic Small Outline
Package
VDD
XT
XT
NC
CS1
D0
NC
NC
D1
D2
D3
WR
A0-A3:
D0-D3:
CSO , CS1:
RD:
WR:
ALE:
STD.P:
XT, XT:
VDD:
VSS:
Address input
Data input/output
CHIP SELECTS 0,1
READ enable
WRITE enable
Address latch enable
Standard pulse output
XTAL oscillator input/output
+5V supply
ground
¡ Semiconductor
MSM6242B
REGISTER TABLE
Address Input
Register
Address
Input
A3 A2 A1 A0 Name
Data
D3
D2
D1
D0
Count
value
Description
0
0
0
0
0
S1
S8
S4
S2
S1
0 to 9
1-second digit register
1
0
0
0
1
S10
*
S40
S20
S10
0 to 5
10-second digit register
2
0
0
1
0
MI1
mi8
mi4
mi2
mi1
0 to 9
1-minute digit register
3
0
0
1
1
MI10
*
mi40
mi20
mi10
0 to 5
10-minute digit register
4
0
1
0
0
H1
h8
h4
h2
h1
0 to 9
1-hour digit register
5
0
1
0
1
H10
*
PM/
AM
h20
h10
0 to 2
or 0 to 1
PM/AM, 10-hour digit
register
6
0
1
1
0
D1
d8
d4
d2
d1
0 to 9
1-day digit register
7
0
1
1
1
D10
*
*
d20
d10
0 to 3
10-day digit register
8
1
0
0
0
MO1
mo8
mo4
mo2
mo1
0 to 9
1-month digit register
9
1
0
0
1
MO10
*
*
*
MO10
0 to 1
10-month digit register
A
1
0
1
0
Y1
y8
y4
y2
y1
0 to 9
1-year digit register
B
1
0
1
1
Y10
y80
y40
y20
y10
0 to 9
10-year digit register
C
1
1
0
0
W
*
w4
w2
w1
0 to 6
Week register
D
1
1
0
1
CD
30
sec.
ADJ
IRQ
FLAG
BUSY
HOLD
—
Control Register D
E
1
1
1
0
CE
t1
t0
ITRPT
MASK
/STND
—
Control Register E
F
1
1
1
1
CF
TEST
24/12
STOP
—
Control Register F
REST
REST = RESET
ITRPT/STND = INTERRUPT/STANDARD
Note 1)
Note 2)
Note 3)
Note 4)
Bit * does not exist (unrecognized during a write and held at "0" during a read).
Be sure to mask the AM/PM bit when processing 10's of hour's data.
BUSY bit is read only. The IRQ FLAG bit can only be set to a "0". Setting the IRQ FLAG to a "1" is done by
hardware.
PM at 1 and AM at 0 for PM / AM bit.
Figure 1. Register Table
25
MSM6242B
¡ Semiconductor
OSCILLATOR FREQUENCY DEVIATIONS
0
1
Ta = 25°C
∆f/f (PPM)
∆f/f (PPM)
0
-50
5V
-1
-2
-3
2V
-100
-60
-4
-40
-20
0
20
40
60
80
1
2
3
4
Figure 2. Frequency Deviation (PPM) vs Temperature
6
Figure 3. Frequency Deviation (PPM) vs Voltage
1. The graghs above showing frequency deviation vs temperature/voltage are primarily characteristic of the
MSM6242B with the oscillation circuit described below.
XT
XT
Crystal: Type N0, P3 by kinseki (32.768 KHz)
CG
26
5
VDD (V)
Ta (°C)
Note:
0
CD
VDD
CG, CD: 22pF (Temperature Characteristics: 0)
¡ Semiconductor
MSM6242B
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
VDD
Power Supply Voltage
Unit
-0. 3 to 7
V
-0.3 to VDD +0.3
V
Input Voltage
VI
Output Voltage
VO
-0.3 to VDD +0.3
V
TSTG
-55 to +150
°C
Storage Temperature
Ta = 25°C
OPERATING CONDITIONS
Parameter
Symbol
Condition
Rating
Power Supply Voltage
VDD
—
4 to 6
Standby Supply Voltage
VBAK
—
2 to 6
Crystal Frequency
f(XT)
—
32.768
kHz
Operating Temperature
TOP
—
-40 to +85
°C
Unit
V
D.C. Characteristics
(VDD = 5V ± 10%, TA = -40 ~ +85)
Parameter
"H" Input Voltage
"L" Input Voltage
Input Leak Current
Symbol
Condition
Min.
Typ.
VIH1
—
2.2
—
—
VIL1
—
—
—
0.8
ILK1
Input Leak Current
ILK2
"L" Output Voltage
VOL1
"H" Output Voltage
VI = VDD/0V
—
—
Max.
Unit
Applicable
Terminal
V
All input terminals except CS1, XT
1/-1
µA
Input terminals
other than
D0 ~ D3, XT
—
—
10/-10
IOL = 2.5mA
—
—
0.4
VOH
IOH = -400µA
2.4
—
—
"L" Output Voltage
VOL2
IOL = 2.5mA
—
—
0.4
V
OFF Leak Current
IOFFLK
V = VDD/0V
—
—
10
µA
Input frequency
1MHz
—
5
—
PF
All input
terminals
VDD =
5V
—
—
30
µA
VDD
VDD =
2V
—
—
10
4/5VDD
—
—
V
—
—
1/5VDD
CS1
Input Capacitance
CI
Current Consumption
IDD1
Current Consumption
IDD2
"H" Input Voltage
VIH2
"L" Input Voltage
VIL2
f(xt) =
32.768
KHz
CS1 ~~ 0
VDD = 2 ~ 5.5V
D0 ~ D3
V
D0 ~ D3
STD.P
27
MSM6242B
¡ Semiconductor
SWITCHING CHARACTERISTICS
(1) WRITE mode (ALE = VDD)
(VDD = 5V ± 10% Ta = -40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
CS1 Set up Time
tC1S
—
1000
—
CS1 Hold Time
tC1H
—
1000
—
Address Stable Before
WRITE
tAW
—
20
—
Address Stable After
WRITE
tWA
—
10
—
WRITE Pulse Width
tWW
—
120
—
Data Set up Time
tDS
—
100
—
Data Hold Time
tDH
—
10
—
RD / WR Recovery Time
tRCV
—
60
—
CS1
VIH2 –
A0 ~ A3
CS0
VIH1 –
VIL1 –
VIH1 –
WR
D0 ~ D3
(INPUT)
,
,,
,,
,,
,,
,
tAW
,,
,,
VIH1 –
VIL1 –
ns
tC1H
tC1S
,,
Unit
,,
,
tWA
tWW
,,
,
tDH
tDS
,,
,,
,,
,,
,,
,,
,,
,,
VIH1 = 2.2V
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
,,
,,
tRCV
,,
,
,,
,,
,,
,,
,,
,
Figure 4. Write Cycle — (ALE = VDD)
(2) WRITE mode (With use of ALE)
(VDD = 5V ± 10%, Ta = -40 ~ +85°C)
Parameter
28
Symbol
Min.
Max.
—
1000
—
—
25
—
—
25
—
—
40
—
tALW
—
10
—
WRITE Pulse Width
tWW
—
120
—
ALE After WRITE
tWAL
—
20
—
DATA Set up Time
tDS
—
100
—
DATA Hold Time
tDH
—
10
—
CS1 Hold Time
tC1H
—
1000
—
RD / WR Recovery Time
tRCV
—
60
—
CS1 Set up Time
tC1S
Address Set up Time
tAS
Address Hold Time
tAH
ALE Pulse Width
tAW
ALE Before WRITE
Condition
Unit
ns
¡ Semiconductor
MSM6242B
tC1S
CS1
VIH2 –
A0 ~ A3
CS0
VIH1 –
VIL1 –
VIH1 –
VIL1 –
VIH1 –
VIL1 –
VIH1 –
VIL1 –
ALE
WR
D0 ~ D3
(INPUT)
,,
,
,,
,,
tAS
,,
tC1H
,,
,,
,
,,
,,
,
,,
,,
tAW
,,
,,
,,
,,
,,
,,
,,
tALW
,,
,,
,
tWW
tWAL
t
,,
,, RCV
tDH,,,,,,
,,
,
tDS
,,
VIH1 = 2.2V
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
tAH
,
,,
,,
,,
,,
,,
,
Figure 5. Write Cycle — (With Use of ALE)
(3) READ mode (ALE = VDD)
(VDD = 5V ± 10%, Ta = -40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
CS1 Set up Time
tC1S
—
1000
—
CS1 Hold Time
tC1H
—
1000
—
Address Stable before
READ
tAR
—
20
—
Address Stable after
READ
tRA
—
RD to Data
tRD
CL = 150pF
Data Hold
tDR
—
0
—
RD / WR Recovery Time
tRCV
—
60
—
CS1
VIH2 –
A0 ~ A3
VIH1 –
VIL1 –
VIH1 –
VIL1 –
CS0
RD
D0 ~ D3
(OUTPUT)
VOH –
VOL –
Unit
ns
tC1S
,,
,
—
tAR
,,
,,
,
120
tRA
,,
,,
—
0
tC1H
,,
,
,,
,,
,,
tRCV
,,
,
,,
,,
,
tDR
tRD
,,
,,
,
,,
,,
,
"Z"
,,
,,
,,
,,
,,
VIH1 = 2.2V
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
VOH = 2.2V
VOL = 0.8V
,,
,
Figure 6. Read Cycle — (ALE = VDD)
29
MSM6242B
¡ Semiconductor
(4) READ mode (With use of ALE)
(VDD = 5V ± 10%, Ta = -40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
CS1 Set up Time
tC1S
—
1000
—
Address Set up Time
tAS
—
25
—
Address Hold Time
tAH
—
25
—
ALE Pulse Width
tAW
—
40
—
ALE before READ
tALR
—
10
—
ALE after READ
tRAL
—
10
—
RD to Data
tRD
CL = 150pF
DATA Hold
tDR
—
0
—
CS1 Hold Time
tC1H
—
1000
—
RD / WR Recovery Time
tRCV
—
60
—
CS1
A0 ~ A3
CS0
ALE
RD
D0 ~ D3
(OUTPUT)
VIH2 –
VIH1 –
VIL1 –
VIH1 –
VIL1,,–
VIH1 –
VIL1 –
VOH –
VOL –
tC1S
,,
,,
,,
120
—
,,
,,
tC1H
VIH1 = 2.2V
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
VOH = 2.2V
VOL = 0.8V
,,
,
tAW
,,
,
,,
,,
tALR
,,
,
,,
,
,,
,,
,,
tRD
,
,,
tRAL
tRCV
,,
,,
tDR,,,,,,
,,
,
,,
,
,,
,,
,,
,,
Figure 7. Read Cycle — (With Use of ALE)
30
ns
tAH
tAS
,,
Unit
"Z"
¡ Semiconductor
MSM6242B
PIN DESCRIPTION
Name
Pin No.
RS
GS
D0
14
19
D1
13
16
D2
12
15
D3
11
14
A0
4
5
A1
5
7
A2
6
9
A3
7
10
Description
Data Input/Output pins to be directly connected to a microcontroller bus for
reading and writing of the clock/calendar's registers and control registers. D0 = LSB
and D3 = MSB.
Address input pin for use by a microcomputer to select internal clock/calendar's
registers and control registers for Read/Write operations (See Function Table
Figure 1). Address input pins A0-A3 are used in combination with ALE for
addressing registers.
ALE
3
4
Address Latch Enable pin. This pin enables writing of address data when ALE = 1
and CSO = 0; address data is latched when ALE = 0 Microcontroller/Microprocessors having an ALE output should connect to this pin; otherwise it should
be connected at VDD
WR
10
13
Writing of data is performed by this pin.
When CS1 = 1 and CSO = 0, D0 ~ D3 data is written into the register at the rising
edge of WR.
RD
8
11
Reading of register data is accomplished using this pin. When CS1 = 1, CSO = 0
and RD = 0, the data of this register is output to D0 ~ D3. If both RD and WR are
set at 0 simaltaneously, RD is to be inhibited.
CS0
2
2
CS1
15
20
STD.P
1
1
XT
16
22
XT
17
23
VDD
18
24
Power supply pin. +2 ~ +6V power is to be applied to this pin.
GND
9
12
Ground pin.
Chip Select pins. These pins enable/disable ALE, RD and WR operation. CSO
and ALE work in combination with one another, while CS1 work independent
with ALE. CS1 must be connected to power failure detection as shown in Figure
18.
Output pin of N-CH OPEN DRAIN type. The output data is controlled by the
D1 data content of CE register. This pin has a priority to CSO and CS1.
Refer to Figure 9 and FUNCTIONAL DESCRIPTION OF REGISTERS.
32.768 kHz crystal is to be connected to these pins.
When an external clock of 32.768 kHz is to be used for MSM6242's oscillation
source, either CMOS output or pull-up TTL output is to be input from XT, while
XT should be left open.
RFB 5M Ω
VDD
XT
X'tal
C1
STD.P OUTPUT
32.768 kHz
N-CH
VDD OR GND
C2
XT
C1 = C2 = 15 ~ 30pF
The impedance of the crystal should be less than 30k Ω
Figure 8. Oscillator Circuit
Figure 9.
31
MSM6242B
¡ Semiconductor
FUNCTIONAL DESCRIPTION OF REGISTERS
S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1, Y10, W
a)
b)
c)
d)
e)
f)
These are abbreviations for SECOND1, SECOND10, MINUTE1, MINUTE10, HOUR1,
HOUR10, DAY1, DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These
values are in BCD notation.
All registers are logically positive. For example, (S8, S4, S2, S1) = 1001 which means 9
seconds.
If data is written which is out of the clock register data limits, it can result in erroneous clock
data being read back.
PM/AM, h20, h10
In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the setting of 12-hour
mode h20 is to be set. Otherwise it causes a discrepancy. In reading out the PM/AM bit in
the 24-hour mode, it is continuously read out as 0. In reading out h20 bit in the 12-hour mode,
0 is written into this bit first, then it is continuously read out as 0 unless 1 is being written
into this bit.
Registers Y1, Y10, and Leap Year. The MSM6242B is designed exclusively for the Christian
Era and is capable of identifying a leap year automatically. The result of the setting of a nonexistant day of the month is shown in the following example: If the date February 29 or
November 31, 1985, was written, it would be changed automatically to March 1, or
December 1, 1985 at the exact time at which a carry pulse occurs for the day's digit.
The Register W data limits are 0 – 6 (Tabel 1 shows a possible data definition).
TABLE 1
w4
0
0
0
0
1
1
1
w2
0
0
1
1
0
0
1
w1
0
1
0
1
0
1
0
Day of Week
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
Using HOLD Bit
Not Using HOLD Bit
HOLD Bit ← 1
Read Register
S1 ~ W
Read BUSY Bit
Data of
DATA ← S1 ~ W
Register
Busy Bit= O?
YES
Write data into
or Read data from
registers S1 ~ W
HOLD Bit ← 0
*
NO
Read Register
S1 ~ W
HOLD Bit ← 0
Idling Time
* In the inside of LSI, the CLEAR of BUSY bit is performed when
HOLD bit = 0, but, if the period of HOLD bit =0 is extermely
narrow as compared with the period of HOLD bit = 1, there is
some case that the CLEAR of BUSY bit delays so that the
BUSY bit can be cleared by sampling HOLD bit = 0 at approximate
16KHz. It is recommended to allow an idling time of 62ms or more.
Figure 10. Reading and Writing of Registers S1 ~ W
Second
DATA1 = DATA2
DATA1 = DATA2
YES
32
First
NO
¡ Semiconductor
MSM6242B
Reading Method 2 when Not Using HOLD Bit
*1
t1
t0
*2
ITRPT/STNT
MASK
Initialization only at power ON
• *1 and *2 represent the minimum required
time out.
For example
t1 = 0 and tO = 1 when required to a
unit of second;
t1 = 1 and tO = 0 when required to a
unit of minute; and
t1 = 1 and tO = 1 when required to a
unit of hour;
1
0
0
IRQ FLAG
Reading Method 3 when Not Using HOLD Bit
Initialization only at power ON
• *1 and *2 represent the minimum required
time unit.
*1
t1
For example
t0
*2
t1 = 0 and tO = 1 when required to a
ITRPT/STNT
1
unit of second;
0
MASK
t1 = 1 and tO = 0 when required to a
CPU senses the unit of minute; and
interruption.
t1 = 1 and tO = 1 when required to a
unit of hour;
REGISTER CD READ
WAIT t
See Note
below
Retried the reading, since a
carry occurred during the
operation.
TIME DATA READ
NO
The other IC causes
the interruption.
The interruption is caused by
this IC due to the occurrence
of a carry.
TIME DATA READ
NO
(Note)
YES
YES
WAIT t
REGISTER CD READ
IRQ FLAG = 0
IRQ FLAG = 1
Do this process within the following
time requirements by combination
between t1 and t0:
IRQ FLAG
0
The IRQ FLAG is cleared to
read the next time data.
Normal read
t1 = 0 and tO = 1 . . . Less than 1 second
t1 = 1 and tO = 0 . . . Less than 1 minute
t1 = 1 and tO = 1 . . . Less than 1 hour
t : 12 HOUR MODE . . . 35µS
24 HOUR MODE . . . 3µS
END
CD REGISTER (Control D Register)
a)
b)
c)
d)
HOLD (D0) –
Setting this bit to a "1" inhibits the 1Hz clock to the S1 counter, at which
time the Busy status bit can be read. When Busy = 0, register's S1 ~ W
can be read or written. During this procedure if a carry occurs the S1
counter will be incremented by 1 second after HOLD = 0 (this condition
is guaranteed as long as HOLD = 1 does not exceed 1 second in
duration). If CS1 = 0 then HOLD = 0 irrespective of any condition.
BUSY (D1) –
Status bit which shows the interface condition with microcontroller/
microprocessors. As for the method of writing into and reading from
S1 ~ W (address φ ~ C), refer to the flow chart described in Figure 10.
IRQ FLAG (D2) – This status bit corresponds to the output level of the STD.P output.
When STD.P = 0, then IRQ = 1; when STD.P = 1, then IRQ = 0. The IRQ
FLAG indicates that an interrupt has occurred to the microcomputer if
IRQ = 1. When D0 of register CE (MASK) = 0, then the STD.P output
changes according to the timing set by D3 (t1) and D2 (t0) of register E.
When D1 of register E (ITRPT/STND) = 1 (interrupt mode), the STD.P
output remains low until the IRQ FLAG is written to a "0". When IRQ
= 1 and timing for a new interrupt occurs, the new interrupt is ignored.
When ITRPT/STND = 0 (Standard Pulse Output mode) the STD.P
output remains low until either "0" is written to the IRQ FLAG;
otherwise, the IRQ FLAG automatically goes to "0" after 7.8125ms.
When writing the HOLD or 30 second adjust bits of register D, it is
necessary to write the IRQ FLAG bit to a "1".
±30 ADJ (D3) –
When 30-second adjustment is necessary, a "1" is written to bit D3
during which time the internal clock registers should not be read from
or written to 125µs after bit D3 = 1 it will automatically return to a "0",
and at that time reading or writing of registers can occur.
33
MSM6242B
¡ Semiconductor
START
START
30-SECOND
ADJ BIT = 1
30-SECOND
ADJ BIT = 1
READ 30-SECOND
ADJ BIT
125µs PASS?
30-SECOND
ADJ BIT = 0?
NO
YES
NO
END
YES
(B)
END
(A)
Figure 11. Writing 30-Second Adj. bit (Two Ways A, B)
CE REGISTER (Control E Register)
a)
MASK (D0) –
b)
ITRPT/STND (D1) –
c)
T0 (D2), T1 (D3) –
"1"
MASK BIT
This bit controls the STD.P output. When MASK = 1, then STD.P
= 1 (open); when MASK = 0, then STD.P = output mode. The
relationship between the MASK bit and STD.P output is shown
Figure 12.
The ITRPT/STND input is used to switch the STD.P output
between its two modes of operation, interrupt and Standard
timing waveforms. When ITRPT/STND = 0 a fixed cycle waveform with a low-level pulse width of 7.8125ms is present at the
STD.P output. At this time the MASK bit must equal 0, while the
period in either mode is determined by T0 (D2) and T1 (D3) of
Register E.
These two bits determine the period of the STD.P output in both
interrupt and Fixed timing waveform modes. The tables below
show the timing associated with the T0, T1 inputs as well as their
relationship to INTRPT/STND and STD.P.
"1"
"0"
"0"
"INTERRUPT" DOES
NOT OCCUR BECAUSE
MASK BIT IS "1"
"0"
"1"
"0"
OUTPUT DOES NOT OCCUR
AT LOW LEVEL BECAUSE
MASK BIT IS "1"
STD.P
OUTPUT
OPEN
STD.P OUTPUT
"1"
MASK BIT
OPEN
LOW LEVEL
LOW LEVEL
"INTERRUPT" TIMING
WRITE "0" INTO IRQ FLAG BIT
OUTPUT TIMING
AUTOMATIC RETURN
INTRT/STND BIT = "1"
INTRT/STND BIT = "0"
Figure 12.
TABLE 2
34
t1
t0
Period
Duty CYCLE of "0" level when
ITRPT/STND bit is "0".
0
0
1
1
0
1
0
1
1/64 second
1 second
1 minute
1 hour
1/2
1/128
1/7680
1/460800
¡ Semiconductor
MSM6242B
The timing of the STD.P output designated by T1 and T0 occurs the moment that a carry occurs to a clock digit.
(EXAMPLE) WHEN t1 = 1, t0 = 1 and MASK = 0.
PM1:00
PM12:00
OPEN
LOW LEVEL
WHEN ITRPT/STND
BIT is "1" STD.P OUTPUT
WHEN ITRPT/STND
BIT is "0"
d)
e)
f)
g)
h)
OPEN
LOW LEVEL
The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125ms
independent of T0/T1 inputs.
The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time
base. (See Figure 14).
During ±30 second adjustment a carry can occur that will cause the STD.P output to go low
when T0/T1 = 1,0 or 1,1. However, when T1/T0 = 0, 0 and ITRPT/STND = 0, carry does
not occur and the STD.P output resumes normal operation.
The STD.P output is held (frozen) at the point at which STOP = 1 while ITRPT/STND = 0.
No STD.P output change occurs as a result of writing data to registers S1 ~ H1.
CF REGISTER (Control F Register)
a)
REST (D0) –
"RESET"
b)
STOP (D1) –
This bit is used to clear the clock's internal divider/counter of less than a
second. When REST = 1, the counter is Reset for the duration of REST. In
order to release this counter from Reset, a "0" must be written to the REST
bit. If CSI = 0 then REST = 0 automatically.
The STOP FLAG Only inhibits carries into the 8192Hz divider stage.
There may be up to 122µs delay before timing starts or stops after
changing this flag; 1 = STOP/0 = RUN.
"1"
STOP BIT
"0"
"1"
"0"
"1"
"0"
"0"
TIMING OF
"CARRY"
TO 8192Hz
"CARRY" EXECUTED
"CARRY" NOT EXECUTED
Figure 13
c)
24/12 (D2) –
"24/HOUR/
12 HOUR"
d)
TEST (D3) –
This bit is for selection of 24/12 hour time modes. If D2 = 1–24 hour mode
is selected and the PM/AM bit is invalid. If D2 = 0–12 hour mode is
selected and the PM/AM bit is valid.
Setting of the 24/12 hour bit is as follows:
1) REST bit = 1
2) 24/12 hour bit = 0 or 1
3) REST bit = 0
* REST bit must = 1 to write to the 24/12 hour bit.
When the TEST flag is a "1", the input to the SECONDS counter comes
from the counter/divider stage instead of the 15th divider stage. This
makes the SECONDS counter count at 5.4163KHz instead of 1Hz. When
TEST = 1 (Test Mode) the STOP & REST (Reset) flags do not inhibit internal
counting. When Hold = 1 during Test (Test = 1) internal counting is
inhibited; however, when the HOLD FLAG goes inactive (Hold = 0)
counter updating is not guaranteed.
35
MSM6242B
¡ Semiconductor
TYPICAL APPLICATION INTERFACE WITH MSM6242B AND
MICROCONTROLLERS
MSM6242B
ALE
RD
WR
DECODER
A8 ~ A15
S1
S0
IO/M
R1
R2
D3
D2
D1
D0
A/D
D3
D2
D1
D0
AD3
AD2
AD1
AD0
MSM6242B
8085
A8 ~ A12
A3
A2
A1
A0
CS0
A8 ~ A15
S1
S0
IO/M
ALE
RD
WR
RD
WR
A3
A2
A1
A0
CS0
DECODER
8085
R1
R2
ALE
RD
WR
I/O MAPPED
MEMORY MAPPED
Note : If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of
MSM6242B, R1 and R2 are not required.
Figure 15.
MSM6242B
Z80
D3
D2
D1
D0
D3
D2
D1
D0
A3
A2
A1
A0
A3
A2
A1
A0
A4 ~ A15
IORQ
MREQ
RD
WR
DECODER
VDD
G1
G2
CS0
ALE
RD
WR
MSM6242B
MCS48
D3
D2
D1
D0
BUS3
BUS2
BUS1
BUS0
DECODER
BUS 4-7
CS0
ALE
RD
WR
ALE
RD
WR
Note : It depends upon the switching
characterisrics decided by a X'tal used
for a Z80 that either of IORQ and MREQ
is used.
Figure 16.
36
A3
A2
A1
A0
Figure 17.
¡ Semiconductor
MSM6242B
TYPICAL APPLICATIONS — INTERFACE WITH MSM80C49
100µf
3.9V ★
4.7µf (tantalum)
LITHIUM
BATTERY
★
22pf
2
X1
26
VDD
INT
ALE
4.553 KHz
22pf
6
11
8
RD
3
WR
MSM
80C49RS
DB0
40
VCC
DB1
DB2
DB3
1
T0
DB7
38
P27
X2
P17
★ (VFWD = < 0.3V)
i.e. GERMANIUM
DIODE
18
18K
15pf
VDD
17
1
XT
SDT.P
3
ALE
32.768 KHz
8
RD
16
10
XT
WR
5-35pf
MSM
6242BRS
4/14
A/D0
5/13
A/D1
6/12
A/D2
7/11
A/D3
2
CS0
15
CS1
9
TR1
VSS
10K
10
12
13
14
15
19
34
VSS
20
820
1.8K
1.8K
TR2
1.8K
RS232
DB25
CONNECTOR
2
3
7
5
20
★
TR3
TR1 = 2N2907
TR2 = 2N2907
TR3 = 2N2222
★ = 1N4148
220
1.8K
★
1.8K
10µf
RS232
INTERFACE
220
5.2V
Figure 18.
37
MSM6242B
¡ Semiconductor
APPLICATION NOTE
1. Power Supply
VDD = 5V
START
STD.P
Output = undifined
Power On
TEST Bit ← 0
REST Bit ← 0
24/12 Bit ← 1*
STOP Bit ← 1
1* = 2*
(1 or 0)
REST Bit ← 0
24/12 Bit ← 2*
Set the current
time
HOLD Bit ← 0
STOP Bit ← 0
Start Operation
2. Adjustment of Frequency
VDD
Screwdriver
18
VDD
17
16
VDD XT XT
CD, CF = (0, 0, 0, 0)
CE = (t1, t0, 0, 0)
SDT.P
1
2
3
Frequency
counter
38
0.1 INCH
b
Eye
CD ~ CF are to be set at as described in the
figure and the capacitor is to be adjusted
to meet the settle frequency of t0 and t1.
If the right oscillation can not be obtained,
1. Check the waveform of XT
2. Check CD ~ CF content
3. Check the noise
c
d
2
VDD
1
XT
XT
1
2
a
a
b
: INHIBIT
≥ 0.3 INCH
≥ 0.2 INCH
¡ Semiconductor
MSM6242B
3. CH1 (Chip Select)
VIH and VIL of CH1 has 3 functions.
a) To accomplish the interface with a microcontroller/microprocessor.
b) To inhibit the control bus, data bus and address bus and to reduce input gate pass
current in the stand-by mode.
c) To protect internal data when the mode is moved to and from standby mode.
To realize the above functions:
a) More than 4/5 VDD shoud be applied to the MSM6242B for the interface with a
microcontroller/microprocessor in 5V operation.
b) In moving to the standby mode, 1/5 VDD should be applied so that all data buses should
be disabled. In the standby mode, approx. 0V should be applied.
c) To and from the standby mode, obey following Timing chart.
To Standby Mode
From Standby Mode
4 ~ 6V
VDD
4V
4V
2 ~ 4V
2µs (MIN)
2µs (MIN)
2V
5 DD
CS1
4
V
5 DD
1
V
5 DD
CS0 : H
or WR : H
4. Set SDT.P at alarm mode
Set alarm at 9:00
MASK BIT ← 0
ITRPT/STND BIT ← 1
t1, t0 ← 1
Start interruption
CPU Activation
Read Register CD
D2 = 1?
NO
YES
Repeat
Read H10 and
H10 Cotent
AM 9:00?
YES
NO
CPU HALT
or
CPU STAND BY
39
MSM6242B
¡ Semiconductor
TYPICAL APPLICATION — POWER SUPPLY CIRCUIT
VCE (SAT.) = 0.1V
+5V
RIPPLE
OPERATING: 20mV P-P
BATTERY BACKUP: 0mV
22µf
+5V
RL
4.7µf
RL
M
C
100Ω
VDD
51K
10K
100Ω
1.2 x 3 = 3.6V
Ni – Cd
4.7µf
B
MSM
6242B
1.5 x 2 = 3V
DRY CELLS
VSS
VDD
MSM
6242B
VSS
10K
Figure 20.
Figure 19.
220Ω
VDD
MSM
6242B
VSS
4.7µf
100Ω
RL
~ 6.5V
D1
+5V
1.2 x 3 = 3.6V
Ni – Cd
Figure 21.
4.7µF: tantalum
SUPPLEMENTARY DESCRIPTION
•
•
*
When "0" is written to the IRQ FLAG bit, the IRQ FLAG bit is cleared. However, if "0" is
assigned to the IRQ FLAG bit when written to the other bits, the 30-sec ADJ bit and the
HOLD bit, the IRQ FLAG = 1 and was generated before the writing and IRQ FLG = 1
generated in a moment then will be cleared. To avoid this, always set "1" to the IRQ
FLAG unless "0" is written to it intentionally. By writing "1" to it, the IRQ FLAG bit
does not become "1".
Since the IRQ FLAG bit becomes "1" in some cases when rewriting either of the t1, t0, or
ITRPT/STND bit of register CE, be sure to write "0" to the IRQ FLAG bit after writing to
make valid the IRQ FLAG = 1 to be generated after it.
The relationship between SDT.P OUT and IRQ FLAG bit is shown below:
open
STD.P OUT
IRQ FLAG bit
"L"
1
0
approx. 1.95 ms
40