PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74ALVCH16270 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • PI74ALVCH16270 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors Industrial operation at –40°C to +85°C Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) The PI7ALVCH16270 is used in applications where data must be transferred from a narrow high-speed bus to a wider lower frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two stage pipeline is provided in the A-to1B path,with a single storage register in the A-to-2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus direction changes with the CLK. Logic Block Diagram To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 1 PS8171A 03/05/03 PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Truth Tables(1) Pin Name OE CLK Description Output Enable Input (Active LOW) Clock SEL CLKEN A,1B,2B GND V CC Select (Active Low) Clock Enable (Active Low) 3-State Outputs Ground Power Inputs Outputs CLK OEA OEB A 1B, 2B H H Z Z H L Z Active L H Active Z L L Active Active A to B Storage (OEB = L) Product Pin Configuration INPUTS OUTPUTS CLKENA1 CLKENA2 CLK OEA CLKEN1B 1 2 56 55 OEB 2B3 3 4 5 54 53 52 2B4 GND 2B2 2B1 V CC A1 6 7 8 56-PIN 51 A56 50 V56 CLKENA2 GND 2B5 2B6 V CC 49 2B7 9 10 48 47 2B8 11 12 13 46 45 44 GND 2B10 14 15 16 43 42 41 2B12 17 18 40 39 1B10 GND 38 37 36 1B9 A12 19 20 21 V CC 22 V CC 1B1 1B2 23 24 35 34 33 GND 1B3 25 26 32 31 GND CLKEN2B 27 28 30 29 CLKENA1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 SEL 2B9 2B11 A 1B 2B L H X X 1B0(3) 2B0(3) L H X X 1B0(3) 2B0(3) L L L L(2) L L L H H(2) H H L L 1B0(3) L H L H 1B0(3) H H H X X 1B0(3) 2B0(3) B to A Storage (OEA = L) 1B12 Inputs 1B11 CLKEN1B 1B8 1B7 1B6 1B5 1B4 CLKEN2B CLK SEL 1B 2B Outputs A H X X H X X A0(3 ) X H X L X X A0(3 ) L X H L X L L X H H X H X L L X L L X L L X H H Notes: 1. H = High Signal Level L = Low Signal Level X = Irrelevant Z = High Impedance ↑ = Transition, Low to High 2. Two CLK edges are needed to propagate data. 3. Output level before the indicated steady state input conditions were established. CLK 2 PS8171A 03/05/03 PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ –65°C to +150°C Ambient Temperature with Power Applied .......................... –40°C to +85°C Input Voltage Range, VIN .................................................... –0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................. –0.5V to VCC +0.5V DC Input Voltage ................................................................... –0.5V to +5.0V DC Output Current .............................................................................. 100 mA Power Dissipation ................................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%) Test Conditions (1) Description VCC Supply Voltage VIH(3) Input HIGH Voltage VIL(3) Input LOW Voltage VIN(3) Input Voltage 0 VCC VOUT(3) Output Voltage 0 VCC VOH VOL IOH(3) IOL(3) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Min. Typ.(2) Parameters 2.3 VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 Max. 3.6 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 IOH = -100mA, VCC = Min. to Max. VCC -0.2 VIH = 1.7V, IOH = -6mA, VCC = 2.3V 2.0 VIH = 1.7V, IOH = -12mA, VCC = 2.3V 1.7 VIH = 2.0V, IOH = -12mA, VCC = 2.7V 2.2 VIH = 2.0V, IOH = -12mA, VCC = 3.0V 2.4 VIH = 2.0V, IOH = -24mA, VCC = 3.0V 2.0 V IOL = 100mA, VIL = Min. to Max. 0.2 VIL = 0.7V, IOL = 6mA, VCC = 2.3V 0.4 VIL = 0.7V, IOL = 12mA, VCC = 2.3V 0.7 VIL = 0.8V, IOL = 12mA, VCC = 2.7V 0.4 VIL = 0.8V, IOL = 24mA, VCC = 3.0V 0.55 VCC = 2.3V -12 VCC = 2.7V -12 VCC = 3.0V -24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 3 Units mA PS8171A 03/05/03 PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics-Continued (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%) Test Conditions (1) Parameters Description IIN Input Current Typ.(2) VIN = VCC or GND, VCC = 3.6V Input Hold Current IIN (HOLD) Min. Max. Units ±5 VIN = 0.7V, VCC = 2.3V 45 VIN = 1.7V, VCC = 2.3V -45 VIN = 0.8V, VCC = 3.0V 75 VIN = 2.0V, VCC = 3.0V -75 VIN = 0 to 3.6V, VCC = 3.6V ±500 IOZ Output Current (3-STATE Outputs) VOUT = VCC or GND, VCC = 3.6V ±10 ICC Supply Current VCC = 3.6V, IOUT = 0mA, VIN = GND or VCC 40 DICC Supply Current per Input @ TTL HIGH VCC = 3.0V to 3.6V One Input at VCC - 0.6V Other Inputs at VCC or GND 750 CI Control Inputs VIN = VCC or GND, VCC = 3.3V 3.5 CO Outputs VO = VCC or GND, VCC = 3.3V 9 mA pF Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating. Timing Requirements over Operating Range Parameters Description VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. 150 0 150 0 150 fCLOCK Clock frequency 0 tW Pulse duration, CLK HIGHor Low 3.3 3.3 3.3 A data before CLK 4.1 3.8 3.1 B data before CLK 0.9 1.2 0.9 CLKENA1 or CLKENA2 before CLK 3.5 3.2 2.7 CLKEN1B or CLKEN2B before CLK 3.4 3 2.6 OE data before CLK 4.4 3.9 3.2 A data after CLK 0 0 0.2 B data after CLK 1.4 1 1.7 CLKENA1 or CLKENA2 before CLK 0 0.1 0.3 CLKEN1B or CLKEN2B before CLK 0 0 0.6 OE after CLK 0 0 0.1 tSU tH Dt/DV(1) Setup time Hold time Input Transition Rise or Fall 0 10 0 10 0 Units Mhz ns 10 ns/V Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 4 PS8171A 03/05/03 PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Operating Range(1) Parame te rs From (IN PUT) V CC = 2.5V ± 0.2V To (OUTPUT) M ax. M in. (2) 150 V CC = 2.7V M in. (2) M ax. V CC = 3.3V ± 0.3V M in.(2) 150 150 C LK B 2 6.5 5.8 1.1 5.1 C LK A 1.7 6 5.4 1 4.7 tPD SEL A 1.9 6.8 6.4 1 5.5 tEN C LK A or B 1.6 7.5 6.8 1 6 tDIS C LK A or B 2.6 7.4 6.5 1.1 5.8 F M AX Units M ax. (2) ns Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25ºC Parameter CPD Power Dissipation Capacitance Test Conditions Outputs Enabled Outputs Disabled CL = 50pF, f = 10 MHz VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical 87 120 80.5 118 Units pF Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8171A 03/05/03