SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999 D D D D D D D D D DGG PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family Supports SSTL_2 Signal Data Inputs and Outputs Supports LVTTL Switching Levels on the RESET Pin Differential CLK Signal Flow-Through Architecture Optimizes PCB Layout Meets SSTL_2 Class II Specifications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Packaged in Plastic Thin Shrink Small-Outline Package Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 description This 14-bit registered buffer is designed for 2.3-V to 3.6-V VCC operation and SSTL_2 data input and output levels. All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 D1 D2 GND VCC D3 D4 D5 D6 D7 CLK CLK VCC GND VREF RESET D8 D9 D10 D11 D12 VCC GND D13 D14 When RESET is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The SN74SSTL16857 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS RESET CLK CLK D OUTPUT Q L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999 logic diagram (positive logic) RESET CLK CLK VREF D1 34 38 39 35 48 1D C1 1 Q1 R To 13 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. Current flows only when the output is in the high state and VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999 recommended operating conditions (see Note 4) MIN NOM VDDQ 2.3 MAX UNIT VCC VDDQ Supply voltage VREF VTT Reference voltage (VREF = VDDQ/2) VI VIH Input voltage AC high-level input voltage Data inputs VIL VIH AC low-level input voltage Data inputs DC high-level input voltage Data inputs VIL VIH DC low-level input voltage Data inputs High-level input voltage RESET VIL VICR Low-level input voltage RESET Common-mode input voltage range CLK, CLK 0.97 VI(PP) IOH Peak-to-peak input voltage CLK, CLK 360 High-level output current –20 mA IOL TA Low-level output current 20 mA 70 _C Output supply voltage 1.15 Termination voltage VREF–40 mV 0 1.25 VREF 3.6 V 2.7 V 1.35 V VREF+40 mV VCC V VREF+350 mV V VREF–350 mV VREF+180 mV Operating free-air temperature V V VREF–180 mV 2 V V 0.8 0 V 1.53 V V mV NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II = –18 mA IOH = –100 µA VOH IOH = –8 mA IOH = –16 mA 23V 2.3 VI = 2.7 V or 0 VI = 1.7 V or 0.8V VI = 2.7 V or 0 VI = 1.7 V or 0.8V CLK CLK CLK, VI = 2.7 V or 0 VI = 1.7 V or 0.8V VI = 2.7 V or 0 RESET VREF ICC RESET Ci Data inputs RESET TYP 27V 2.7 VREF = 1 1.15 15 V or 1 1.35 35 V 36V 3.6 VREF = 1 1.15 15 V or 1 1.35 35 V 27V 2.7 15 V or 1 35 V VREF = 1 1.15 1.35 VI = VCC or GND VREF = 1 1.15 15 V or 1 1.35 35 V V V 0.2 0.35 ±5 ±5 ±5 ±1 ±1 ±1 ±5 ±5 2.7 V ±5 IO = 0 36V 3.6 1 7 V or 0.8 08V VI = 1.7 2 5 V† 2.5 VI = 1.7 1 7 V or 0.8 08V 3 3 V‡ 3.3 µA ±5 3.6 V VI = 1.7 V or 0.8 V VI = 2.7 V or 0 mA ±1 3.6 V 27V 2.7 µA ±5 2.7 V IO = 0 V 0.35 36V 3.6 VI = 1.7 V or 0.8 V VI = 2.7 V or 0 Data inputs † All typical values are at VCC = 2.5 V, TA = 25°C. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. UNIT –1.2 1.95 23V 2.3 VREF = 1 1.15 15 V or 1 1.35 35 V MAX VCC–0.2 1.95 2.3 V to 2.7 V IOL = 16 mA VI = 1.7 V or 0.8V Data inputs MIN 2.3 V to 2.7 V IOL = 100 µA IOL = 8 mA VOL II VCC 2.3 V 90 90 90 mA 90 3 2.5 pF 3 2.5 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V MIN 4 fclock tw Clock frequency tsu Setup time th Hold time, data after CLK↑, CLK↓ MAX VCC = 3.3 V ± 0.3 V MIN 150 Pulse duration, CLK, CLK high or low 150 3.3 3.3 Data before CLK↑, CLK↓ 1.1 1.75 RESET high before CLK↑, CLK↓ 0.6 1.1 0.7 0.7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX MHz ns ns ns SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX fmax tpd CLK and CLK Q 1.5 3.8 1.4 3.7 ns tPHL RESET Q 1.5 4.3 1.4 3.5 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 150 MHz 5 SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V AND VCC = 3.3 V ± 0.3 V VTT Test Point 25 Ω 25 Ω CL= 30 pF (see Note A) LOAD CIRCUIT Timing Input VREF† tsu Data Input VIL§ VIH‡ VREF† Output Control VIH‡ VREF† tPLH VOLTAGE WAVEFORMS PULSE DURATION VIL§ VIL§ Output Input VIL§ VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VREF† VIH‡ VREF† VREF† th VREF† Input tw VIH‡ VREF† VIL§ VOH VREF† VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS tPLZ tPZL Output Waveform 1 (see Note B) VIL§ VIL§ VTT VOL tPHZ tPZH tPHL VREF† VIH‡ VREF† VOH Output Waveform 2 (see Note B) VIH‡ VIH‡ VTT VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING † VREF = VDDQ/2 ‡ VIH = VREF + 350 mV (AC voltage levels) § VIL = VREF – 350 mV (AC voltage levels) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1.25 ns/V, tf ≤ 1.25 ns/V. D. The outputs are measured one at a time with one transition per measurement. E. VTT = VREF = VDDQ/2 F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. 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