ADS5287 www.ti.com SBAS428 – JANUARY 2008 10-Bit, Octal-Channel ADC Up to 65MSPS DESCRIPTION LCLKN 12x ADCLK PLL ADCLKP 1x ADCLK ADCLKN OUT1N OUT8P OUT8N Drive Current Test Patterns PowerDown Channels 2 to 7 ADC Control PD REFT REFB VCM ISET SCLK SDATA CS RESET Registers Reference INT/EXT Serializer Output Format Digital Gain (0dB to 12dB) Medical Imaging Wireless Base-Station Infrastructure Test and Measurement Instrumentation Digital OUT1P ¼ 10-Bit ADC Serializer ¼ ¼ IN8P IN8N Digital ¼ 10-Bit ADC ¼ IN1P IN1N 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Xilinx is a registered trademark of Xilinx, Inc. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2008, Texas Instruments Incorporated PRODUCT PREVIEW LVDD (1.8V) LCLKP 6x ADCLK Clock Buffer APPLICATIONS • • • AVDD (3.3V) (AVSS) CLKN The ADS5287 is a high-performance, low-power, octal channel analog-to-digital converter (ADC). Available in a 9mm × 9mm QFN package, with serialized low-voltage differential signaling (LVDS) outputs and a wide variety of programmable features, the ADS5287 is highly customizable for a diversity of applications and offers an unprecedented level of system integration. An application note, XAPP774 (available at www.xilinx.com) describes how to interface the serial LVDS outputs of TI's ADCs to Xilinx® field-programmable gate arrays (FPGAs). The ADS5287 is specified over the industrial temperature range of –40°C to +85°C. ¼ • Speed and Resolution Grades: – 10-bit, 65MSPS • Power Dissipation: – 46mW/Channel at 30MSPS – 53mW/Channel at 40MSPS – 62mW/Channel at 50MSPS – 74mW/Channel at 65MSPS • 61.7dBFS SNR at 10MHz IF • Analog Input Full-Scale Range: 2VPP • Low-Frequency Noise Suppression Mode • 6dB Overload Recovery in One Clock • External and Internal (Trimmed) Reference • 3.3V Analog Supply, 1.8V Digital Supply • Single-Ended or Differential Clock: – Clock Duty Cycle Correction Circuit (DCC) • Programmable Digital Gain: 0dB to 12dB • Serialized DDR LVDS Output • Programmable LVDS Current Drive, Internal Termination • Test Patterns for Enabling Output Capture • Straight Offset Binary or Two's Complement Output • Package Options: – 9mm × 9mm QFN-64 23 (ADCLK) CLKP FEATURES 1 ADS5287 www.ti.com SBAS428 – JANUARY 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. RELATED PRODUCTS MODEL RESOLUTION (BITS) SAMPLE RATE (MSPS) CHANNELS ADS5281 12 50 8 ADS5282 12 65 8 ADS5287 10 65 8 ADS5270 12 40 8 ADS5271 12 50 8 ADS5272 12 65 8 ADS5273 12 70 8 ADS5242 12 65 4 ORDERING INFORMATION (1) (2) PRODUCT PREVIEW (1) (2) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR ADS5287 QFN-64 RGC SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +85°C AZ5287 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5287IRGCT Tape and Reel, 250 ADS5287IRGCR Tape and Reel, 2000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. These devices meet the following planned eco-friendly classification: Green (RoHS and No Sb/Br): Texas Instruments defines Green to mean Pb-free (RoHS compatible) and free of bromine (Br)- and antimony (Sb)-based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. These devices have a Cu NiPdAu lead/ball finish. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS5287 UNIT Supply voltage range, AVDD –0.3 to +3.9 V Supply voltage range, LVDD –0.3 to +2.2 V Voltage between AVSS and LVSS –0.3 to +0.3 V –0.3 to +3 V External voltage applied to REFB pin –0.3 to +2 V Voltage applied to analog input pins –0.3 to minimum [3.6, (AVDD + 0.3)] V Voltage applied to digital input pins –0.3 to minimum [3.9, (AVDD + 0.3)] V Peak solder temperature +260 °C Junction temperature +125 °C –65 to +150 °C External voltage applied to REFT pin Storage temperature range (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 RECOMMENDED OPERATING CONDITIONS ADS5287 PARAMETER MIN TYP MAX UNIT V SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES AVDD Analog supply voltage 3.0 3.3 3.6 LVDD Digital supply voltage 1.7 1.8 1.9 Differential input voltage range Input common-mode voltage V 2 VPP VCM ± 0.05 V REFT External reference mode 2.5 V REFB External reference mode 0.5 V CLOCK INPUTS ADCLK input sample rate 1/ tC 10 50, 65 MSPS Input clock amplitude differential (VCLKP–VCLKN) peak-to-peak Sine wave, ac-coupled 3.0 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP Input clock CMOS, single-ended (VCLKP) VIL 0.6 2.2 Input clock duty cycle V V 50 PRODUCT PREVIEW VIH % DIGITAL OUTPUTS ADCLKP and ADCLKN outputs (LVDS) 10 1x (sample rate) 50, 65 MHz LCLKP and LCLKN outputs (LVDS) 60 6x (sample rate) 300, 390 MHz CLOAD Maximum external capacitance from each pin to LVSS RLOAD Differential load resistance between the LVDS output pairs TA Operating free-air temperature 5 pF Ω 100 –40 +85 °C INITIALIZATION REGISTERS After the device has been powered up, the following registers must be written to (in the exact order listed) through the serial interface as part of an initialization sequence. ADDRESS (hex) DATA (hex) 03 0002 Initialization register 2 01 0010 Initialization register 3 C7 8001 Initialization register 4 DE 01C0 Initialization register 1 If the analog input is ac-coupled, register 5 must be be written to. Initialization register 5 ADDRESS (hex) DATA (hex) E2 00C0 Initializing these registers configures the device for the most optimum mode of operation. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 3 ADS5287 www.ti.com SBAS428 – JANUARY 2008 DIGITAL CHARACTERISTICS DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. At CLOAD = 5pF (1), IOUT = 3.5mA (2), RLOAD = 100Ω (2), and no internal termination, unless otherwise noted. ADS5287 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 1.4 V Low-level input voltage 0.3 V High-level input current 33 µA Low-level input current –33 µA 3 pF High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, |VOD| 350 mV Common-mode voltage of OUTP and OUTN 1200 mV Output capacitance inside the device, from either output to ground 2 pF Input capacitance LVDS OUTPUTS VOS output offset voltage Output capacitance PRODUCT PREVIEW (1) (2) 4 CLOAD is the effective external single-ended load capacitance between each output pin and ground. IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 ELECTRICAL CHARACTERISTICS Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless otherwise noted.Typical values at +25°C. ADS5287 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE VOLTAGES VREFB Reference bottom 0.5 VREFT Reference top 2.5 VCM V V VREFT – VREFB 1.95 2.0 2.05 Common-mode voltage (internal) 1.425 1.5 1.575 VCM output current V V ±2 mA EXTERNAL REFERENCE VOLTAGES VREFB Reference bottom 0.4 0.5 0.6 V VREFT Reference top 2.4 2.5 2.6 V VREFT – VREFB 1.9 2.0 2.1 V ANALOG INPUT 2.0 Differential input capacitance Analog input bandwidth VPP 3 pF 520 MHz Analog input common-mode range DC-coupled input VCM ± 0.05 V Analog input common-mode current Per input pin per MSPS of sampling speed 2.5 µA/MHz per pin Recovery from 6dB overload to within 1% accuracy 1 Clock cycle Standard deviation seen on a periodic first data within full-scale range in a 6dB overloaded sine wave 1 LSB Voltage overload recovery time Voltage overload recovery repeatability PRODUCT PREVIEW Differential input voltage range DC ACCURACY Offset error –1.25 Offset error temperature coefficient (1) +1.25 %FS ±5 ppm/°C Channel gain error Excludes error in internal reference –0.8 %FS Channel gain error temperature coefficient Excludes temperature coefficient of internal reference ±10 ppm/°C ±15 ppm/°C 1.5 mV/V Internal reference error temperature coefficient (2) DC PSRR ±0.2 DC power-supply rejection ratio (3) POWER-DOWN MODES Power in complete power-down mode Power in partial power-down mode 45 mW 135 mW 88 mW 5MHz full-scale signal applied to seven channels, measurement taken on channel with no input signal –90 dBc f1 = 9.5MHz at –7dBFs f2 = 10.2MHz at –7dBFs –92 dBFS Clock at 65MSPS Power with no clock DYNAMIC PERFORMANCE Crosstalk Two-tone, third-order intermodulation distortion DC ACCURACY No missing codes DNL Differential nonlinearity INL Integral nonlinearity (1) (2) (3) Assured –0.5 ±0.1 +0.5 LSB –1 ±0.1 +1 LSB The offset temperature coefficient in ppm/°C is defined as (O1 – O2) × 106/(T1 – T2)/1024, where O1 and O2 are the offset codes in LSB at the two extreme temperatures, T1 and T2. The internal reference temperature coefficient is defined as (REF1 – REF2) × 106/(T1 – T2)/2, where REF1 and REF2 are the internal reference voltages (REFT – REFB) at the two extreme temperatures, T1 and T2. DC PSRR is defined as the ratio of the change in the ADC output (expressed in mV) to the change in supply voltage (in volts). Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 5 ADS5287 www.ti.com SBAS428 – JANUARY 2008 ELECTRICAL CHARACTERISTICS (continued) Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless otherwise noted.Typical values at +25°C. ADS5287 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 139 TBD mA 87 TBD mA 615 TBD mW POWER SUPPLY—INTERNAL REFERENCE MODE IAVDD Analog supply current ILVDD Digital current Zero input to all channels Total power Incremental power saving Obtained on powering down one channel at a time 61 mW 132 mA POWER SUPPLY—EXTERNAL REFERENCE MODE IAVDD Analog supply current ILVDD Digital current Zero input to all channels 87 mA 592 mW Obtained on powering down one channel at a time 59 mW Current drawn by the eight ADCs from the external reference voltages; sourcing for REFT, sinking for REFB. 3.5 mA 85 dBc 80 dBc 85 dBc 82 dBc 85 dBc 80 dBc 80 dBc 78 dBc 61.7 dBc 61.7 dBc 61.6 dBc 61.6 dBc Total power Incremental power saving EXTERNAL REFERENCE LOADING PRODUCT PREVIEW Switching current DYNAMIC CHARACTERISTICS SFDR HD2 HD3 THD SNR SINAD 6 Spurious-free dynamic range Magnitude of second harmonic Magnitude of third harmonic Total harmonic distortion Signal-to-noise ratio Signal-to-noise and distortion fIN = 5MHz, single-ended clock 73 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 73 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 73 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 70 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 60.5 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock fIN = 30MHz, differential clock Submit Documentation Feedback 60.4 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 PIN CONFIGURATION 54 53 52 51 50 49 IN1P 1 48 IN8N IN1N 2 47 IN8P AVSS 3 46 AVSS IN2P 4 45 IN7N IN2N 5 44 IN7P AVSS 6 43 AVSS IN3P 7 42 IN6N IN3N 8 AVSS 9 40 AVSS IN4P 10 39 IN5N IN4N 11 38 IN5P LVSS 12 37 AVSS PD 13 36 LVSS LVSS 14 35 LVDD OUT1P 15 34 OUT8N OUT1N 16 33 OUT8P 41 IN6P 19 20 21 22 23 24 25 26 27 28 29 30 OUT2N OUT3P OUT3N OUT4P OUT4N ADCLKP ADCLKN LCLKP LCLKN OUT5P OUT5N OUT6P OUT6N 31 32 OUT7N 18 OUT7P 17 OUT2P ADS5287 PRODUCT PREVIEW 55 AVDD 56 ISET 57 AVDD 58 TP 59 VCM CLKN 60 REFB AVDD 61 REFT CS 62 INT/EXT SDATA 63 AVDD SCLK 64 CLKP RESET QFN-64 PowerPAD TOP VIEW Table 1. PIN DESCRIPTIONS: QFN-64 PIN NAME PIN NUMBER # OF PINS ADCLKN DESCRIPTION LVDS frame clock (1X)—negative output 24 1 ADCLKP LVDS frame clock (1X)—positive output 23 1 AVDD Analog power supply, 3.3V AVSS Analog ground 49, 50, 57, 60 4 3, 6, 9, 37, 40, 43, 46 7 CLKN Negative differential clock input Tie CLKN to 0V for a single-ended clock 59 1 CLKP Positive differential clock input 58 1 Serial enable chip select—active low digital input 61 1 IN1N Negative differential input signal, channel 1 2 1 CS IN1P Positive differential input signal, channel 1 1 1 IN2N Negative differential input signal, channel 2 5 1 IN2P Positive differential input signal, channel 2 4 1 IN3N Negative differential input signal, channel 3 8 1 IN3P Positive differential input signal, channel 3 7 1 IN4N Negative differential input signal, channel 4 11 1 IN4P Positive differential input signal, channel 4 10 1 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 7 ADS5287 www.ti.com SBAS428 – JANUARY 2008 Table 1. PIN DESCRIPTIONS: QFN-64 (continued) PIN NAME PIN NUMBER # OF PINS IN5N Negative differential input signal, channel 5 39 1 IN5P Positive differential input signal, channel 5 38 1 IN6N Negative differential input signal, channel 6 42 1 IN6P Positive differential input signal, channel 6 41 1 IN7N Negative differential input signal, channel 7 45 1 IN7P Positive differential input signal, channel 7 44 1 IN8N Negative differential input signal, channel 8 48 1 IN8P Positive differential input signal, channel 8 47 1 Internal/external reference mode select input 56 1 Bias pin—56.2kΩ to ground 51 1 LCLKN LVDS bit clock (6X)—negative output 26 1 LCLKP LVDS bit clock (6X)—positive output 25 1 LVDD Digital and I/O power supply, 1.8V 35 1 LVSS Digital ground INT/EXT ISET PRODUCT PREVIEW 12, 14, 36 3 OUT1N LVDS channel 1—negative output 16 1 OUT1P LVDS channel 1—positive output 15 1 OUT2N LVDS channel 2—negative output 18 1 OUT2P LVDS channel 2—positive output 17 1 OUT3N LVDS channel 3—negative output 20 1 OUT3P LVDS channel 3—positive output 19 1 OUT4N LVDS channel 4—negative output 22 1 OUT4P LVDS channel 4—positive output 21 1 OUT5N LVDS channel 5—negative output 28 1 OUT5P LVDS channel 5—positive output 27 1 OUT6N LVDS channel 6—negative output 30 1 OUT6P LVDS channel 6—positive output 29 1 OUT7N LVDS channel 7—negative output 32 1 OUT7P LVDS channel 7—positive output 31 1 OUT8N LVDS channel 8—negative output 34 1 OUT8P LVDS channel 8—positive output 33 1 PD Power-down input 13 1 REFB Negative reference input/output 54 1 REFT Positive reference input/output 55 1 RESET 8 DESCRIPTION Active low RESET input 64 1 SCLK Serial clock input 63 1 SDATA Serial data input 62 1 TP Test pin, do not use 52 1 VCM Common-mode output pin, 1.5V output 53 1 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 LVDD (1.8V) AVDD (3.3V) (AVSS) CLKN (ADCLK) CLKP FUNCTIONAL BLOCK DIAGRAM LCLKP 6x ADCLK Clock Buffer LCLKN 12x ADCLK PLL ADCLKP 1x ADCLK ADCLKN IN4P IN4N IN5P IN5N IN6P IN6N IN7P IN7N IN8P 10-Bit ADC Digital 10-Bit ADC Digital 10-Bit ADC Digital 10-Bit ADC Digital 10-Bit ADC Digital Digital Gain (0dB to 12dB) IN8N Digital REFT REFB VCM ISET OUT3P Serializer OUT3N OUT4P Serializer OUT4N OUT5P Serializer OUT5N OUT6P Serializer OUT6N OUT7P Serializer OUT7N OUT8P Serializer OUT8N Registers Reference INT/EXT OUT2N PRODUCT PREVIEW IN3N 10-Bit ADC OUT2P Serializer Drive Current IN3P Digital OUT1N PowerDown ADC Control PD IN2N 10-Bit ADC OUT1P Serializer Test Patterns IN2P Digital Output Format IN1N 10-Bit ADC SCLK SDATA CS RESET IN1P Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 9 ADS5287 www.ti.com SBAS428 – JANUARY 2008 LVDS TIMING DIAGRAM Sample n Analog Input Sample n + 12 tD(A) Sample n + 13 Clock Input tSAMPLE 12 clocks latency LCLKN 6X ADCLK LCLKP OUTP SERIAL DATA 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OUTN ADCLKN 1X ADCLK ADCLKP tPROP DEFINITION OF SETUP AND HOLD TIMES PRODUCT PREVIEW LCLKN LCLKP OUTN OUTP tH1 tSU1 tH2 tSU2 tSU = min(tSU1, tSU2) tH = min(tH1, tH2) TIMING CHARACTERISTICS (1) ADS5287 PARAMETER tA TEST CONDITIONS Aperture delay Aperture delay variation tJ Wake-up time Channel-to-channel within the same device (3σ) 10 MAX UNIT 4.5 ns ±20 ps 400 fs Time to valid data after coming out of COMPLETE POWER-DOWN mode 50 µs Time to valid data after coming out of PARTIAL POWER-DOWN mode (with clock continuing to run during power-down) 2 µs Time to valid data after stopping and restarting the input clock 40 µs 12 Clock cycles Data latency (1) TYP 1.5 Aperture jitter tWAKE MIN Timing parameters are ensured by design and characterization; not production tested. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 LVDS OUTPUT TIMING CHARACTERISTICS (1) Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, sampling frequency = as specified, CLOAD = 5pF (2), IOUT = 3.5mA, RLOAD = 100Ω (3), and no internal termination, unless otherwise noted. ADS5287 PARAMETER TEST CONDITIONS (4) MIN TYP 50MSPS MAX MIN TYP 65MSPS MAX MIN TYP MAX UNIT tSU Data setup time (5) Data valid (6) to zero-crossing of LCLKP 0.67 0.47 0.27 ns tH Data hold time (5) Zero-crossing of LCLKP to data becoming invalid (6) 0.85 0.65 0.4 ns tPROP Clock propagation delay Input clock (ADCLK) rising edge cross-over to output clock (ADCLKP) rising edge cross-over 10 14 16.6 10 12.5 14.1 9.7 11.5 14 LVDS bit clock duty cycle Duty cycle of differential clock, (LCLKP – LCLKN) 45.5 50 53 45 50 53.5 41 50 57 ns Bit clock cycle-to-cycle jitter 250 250 250 ps, pp Frame clock cycle-to-cycle jitter 150 150 150 ps, pp tRISE, tFALL Data rise time, data fall time Rise time is from –100mV to +100mV Fall time is from +100mV to –100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time Rise time is from –100mV to +100mV Fall time is from +100mV to –100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns (1) (2) (3) (4) (5) (6) Timing parameters are ensured by design and characterization; not production tested. CLOAD is the effective external single-ended load capacitance between each output pin and ground. IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margin. Data valid refers to a logic high of +100mV and a logic low of –100mV. LVDS OUTPUT TIMING CHARACTERISTICS (1) Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, sampling frequency = as specified, CLOAD = 5pF (2), IOUT = 3.5mA, RLOAD = 100Ω (3), and no internal termination, unless otherwise noted. ADS5287 30MSPS PARAMETER TEST CONDITIONS (4) MIN TYP 20MSPS MAX MIN TYP 10MSPS MAX MIN TYP MAX UNIT tSU Data setup time (5) Data valid (6) to zero-crossing of LCLKP 0.8 1.5 3.7 ns tH Data hold time (5) Zero-crossing of LCLKP to data becoming invalid (6) 1.2 1.9 3.9 ns Clock propagation delay Input clock (ADCLK) rising edge cross-over to output clock (ADCLKP) rising edge cross-over 9.5 13.5 17.3 9.5 14.5 17.3 10 14.7 17.1 LVDS bit clock duty cycle Duty cycle of differential clock, (LCLKP – LCLKN) 46.5 50 52 48 50 51 49 50 51 tPROP Bit clock cycle-to-cycle jitter Frame clock cycle-to-cycle jitter ns 250 250 750 ps, pp 150 150 500 ps, pp tRISE, tFALL Data rise time, data fall time Rise time is from –100mV to +100mV Fall time is from +100mV to –100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time Rise time is from –100mV to +100mV Fall time is from +100mV to –100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns (1) (2) (3) (4) (5) (6) Timing parameters are ensured by design and characterization; not production tested. CLOAD is the effective external single-ended load capacitance between each output pin and ground. IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margin. Data valid refers to a logic high of +100mV and a logic low of –100mV. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 11 PRODUCT PREVIEW 40MSPS ADS5287 www.ti.com SBAS428 – JANUARY 2008 RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING(1) t1 AVDD (3V to 3.6V) AVDD t2 LVDD LVDD (1.7V to 1.9V) t3 t4 t7 High-Level RESET (1.4V to 3.6V) t5 RESET t6 Device Ready for PRODUCT PREVIEW High-Level CS (1.4V to 3.6V) CS Serial Register Write Start of Clock (2) Device Ready for Data Conversion ADCLK t8 10µs < t1 < 50ms, 10µs < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100µs. (1) The AVDD and LVDD power-on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations apply while shutting down the device. (2) Write initialization registers listed in the Initialization Registers table. POWER-DOWN TIMING 1ms tWAKE PD Device Fully Powers Down Device Fully Powers Up Power-up time shown is based on 1µF bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up completely from power-down mode. The ADS5287 has two power-down modes: complete power-down mode and partial power-down mode. The device can be configured in partial power-down mode through a register setting. tWAKE < 50µs for complete power-down mode. tWAKE < 2µs for partial power-down mode (provided the clock is not shut off during power-down). 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 SERIAL INTERFACE The ADS5287 has a set of internal registers that can be accessed through the serial interface formed by pins CS (chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the following actions occur: • Serial shift of bits into the device is enabled • SDATA (serial data) is latched at every rising edge of SCLK • SDATA is loaded into the register at every 24th SCLK rising edge If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16 bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds (a few hertz) and also with a non-50% SCLK duty cycle. After power-up, the internal registers must be initialized to the respective default values. Initialization can be done in one of two ways: 1. Through a hardware reset, by applying a low-going pulse on the RESET pin; or 2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the internal registers to the respective default values and then self-resets the RST bit low. In this case, the RESET pin stays high (inactive). After all registers have been initialized to the respective default values through a RESET operation, the registers detailed in the Initialization Registers table must be written into. The write process must be done after every hardware or software RESET operation in order to configure the device for the best mode of operation. SERIAL INTERFACE TIMING Start Sequence End Sequence CS t6 t1 t7 t2 Data latched on rising edge of SCLK SCLK t3 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDATA t4 t5 ADS5287 PARAMETER DESCRIPTION MIN t1 SCLK period 50 TYP MAX UNIT ns t2 SCLK high time 20 ns t3 SCLK low time 20 ns t4 Data setup time 5 ns t5 Data hold time 5 ns t6 CS fall to SCLK rise 8 ns t7 Time between last SCLK rising edge to CS rising edge 8 ns Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 13 PRODUCT PREVIEW Register Initialization ADS5287 www.ti.com SBAS428 – JANUARY 2008 SERIAL REGISTER MAP Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) (2) (3) (4) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 X X X X X X X D0 NAME X RST X X DESCRIPTION DEFAULT Self-clearing software RESET. Inactive PDN_CH<8:1> Channel-specific ADC power-down mode. Inactive PDN_PARTIAL Partial power-down mode (fast recovery from power-down). Inactive PDN_COMPLETE Register mode for complete power-down (slower recovery). Inactive 0F X X X 11 X X X X X X PRODUCT PREVIEW PDN_PIN_CFG Configures the PD pin for partial power-down mode. Complete power-down ILVDS_LCLK<2:0> LVDS current drive programmability for LCLKN and LCLKP pins. 3.5mA drive LVDS current drive programmability for ADCLKN and ADCLKP pins. 3.5mA drive ILVDS_DAT<2:0> LVDS current drive programmability for OUTN and OUTP pins. 3.5mA drive EN_LVDS_TERM Enables internal termination for LVDS buffers. Termination disabled TERM_LCLK<2:0> Programmable termination for LCLKN and LCLKP buffers. Termination disabled TERM_FRAME <2:0> Programmable termination for ADCLKN and ADCLKP buffers. Termination disabled TERM_DAT<2:0> Programmable termination for OUTN and OUTP buffers. Termination disabled ILVDS_FRAME <2:0> X X X 1 X X X 12 1 X 1 X X X X X 14 X X X X X X X X LFNS_CH<8:1> Channel-specific, low-frequency noise suppression mode enable. Inactive 24 X X X X X X X X INVERT_CH<8:1> Swaps the polarity of the analog input pins electrically. INP is positive input X 0 0 EN_RAMP Enables a repeating full-scale ramp pattern on the outputs. Inactive 0 X 0 DUALCUSTOM_ PAT Enables the mode wherein the output toggles between two defined codes. Inactive 0 0 X SINGLE_CUSTOM _PAT Enables the mode wherein the output is a constant specified code. Inactive BITS_CUSTOM1 <9:8> 2MSBs for a single custom pattern (and for the first code of the dual custom pattern). <9> is the MSB. Inactive BITS_CUSTOM2 <9:8> 2MSBs for the second code of the dual custom pattern. Inactive Inactive 25 X X X X 26 X X X X X X X X BITS_CUSTOM1 <7:0> 8 lower bits for the single custom pattern (and for the first code of the dual custom pattern). <0> is the LSB. 27 X X X X X X X X BITS_CUSTOM2 <7:0> 8 lower bits for the second code of the dual custom pattern. Inactive GAIN_CH1<3:0> Programmable gain channel 1. 0dB gain GAIN_CH2<3:0> Programmable gain channel 2. 0dB gain GAIN_CH3<3:0> Programmable gain channel 3. 0dB gain X X X X X X X X 2A X X X X X X X X GAIN_CH4<3:0> Programmable gain channel 4. 0dB gain X X X X GAIN_CH5<3:0> Programmable gain channel 5. 0dB gain GAIN_CH6<3:0> Programmable gain channel 6. 0dB gain GAIN_CH7<3:0> Programmable gain channel 7. 0dB gain GAIN_CH8<3:0> Programmable gain channel 8. 0dB gain X X X X 2B X X X X X (1) (2) (3) (4) 14 X X X The unused bits in each register (identified as blank table cells) must be programmed as '0'. X = Register bit referenced by the corresponding name and description (default is 0). Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed. Multiple functions in a register should be programmed in a single write operation. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (continued) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 1 1 D0 NAME X DIFF_CLK X DESCRIPTION EN_DCC Differential clock mode. X 1 X X Singleended clock Enables the duty-cycle correction circuit. Disabled EXT_REF_VCM Drives the external reference mode through the VCM pin. External reference drives REFT and REFB PHASE_DDR<1:0> Controls the phase of LCLK output relative to data. 90 degrees 42 1 DEFAULT 0 X PAT_DESKEW Enables deskew pattern mode. X 0 Inactive PAT_SYNC Enables sync pattern mode. Inactive BTC_MODE Binary two's complement format for ADC output. MSB_FIRST Serialized ADC output comes out MSB-first. 45 1 1 1 1 1 X EN_SDR 1 1 FALL_SDR 1 X X X Straight offset binary LSB-first output Enables SDR output mode (LCLK becomes a 12x input clock). DDR output mode Controls whether the LCLK rising or falling edge comes in the middle of the data window when operating in SDR output mode. Rising edge of LCLK in middle of data window PRODUCT PREVIEW 46 1 SUMMARY OF FEATURES FEATURES POWER IMPACT (relative to default) AT fS = 65MSPS DEFAULT SELECTION Internal or external reference (driven on the REFT and REFB pins) N/A Pin External reference driven on the VCM pin Off Register 42 Approximately 9mW less power on AVDD Duty cycle correction circuit Off Register 42 Approximately 7mW more power on AVDD Low-frequency noise suppression Off Register 14 With zero input to the ADC, low-frequency noise suppression causes digital switching at fS/2, thereby increasing LVDD power by approximately 7mW/channel Single-ended or differential clock Single-ended Register 42 Differential clock mode takes approximately 7mW more power on AVDD Off Pin and register 0F ANALOG FEATURES Power-down mode Internal reference mode takes approximately 23mW more power on AVDD Refer to the Power-Down Modes section in the Electrical Characteristics table DIGITAL FEATURES Programmable digital gain (0dB to 12dB) Straight offset or BTC output 0dB Registers 2A and 2B No difference Straight offset Register 46 No difference Off Register 24 No difference Swap polarity of analog input pins LVDS OUTPUT PHYSICAL LAYER LVDS internal termination LVDS current programmability Off Register 12 Approximately 7mW more power on AVDD 3.5mA Register 11 As per LVDS clock and data buffer current setting LSB-first Register 46 No difference DDR Register 46 SDR mode takes approximately 2mW more power on LVDD (at fS = 30MSPS) Refer to Figure 1 Register 42 No difference LVDS OUTPUT TIMING LSB- or MSB-first output DDR or SDR output LCLK phase relative to data output Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 15 ADS5287 www.ti.com SBAS428 – JANUARY 2008 DESCRIPTION OF SERIAL REGISTERS SOFTWARE RESET ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 D0 NAME X RST Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears to '0'. POWER-DOWN MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X X X X X PDN_CH<8:1> X PDN_PARTIAL 0F 0 X PDN_COMPLETE X 0 PDN_PIN_CFG Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for the ADC channel <N>. PRODUCT PREVIEW In addition to channel-specific power-down, the ADS5287 also has two global power-down modes—partial power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip; recovery from this mode is much quicker, provided that the clock has been running for at least 50µs before exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and involves a much longer recovery time. In addition to programming the device for either of these two power-down modes (through either the PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin is high, the device enters partial power-down mode. LVDS DRIVE PROGRAMMABILITY ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 11 D7 D6 X X X D5 X D4 X X D3 D2 D1 D0 NAME X X X ILVDS_LCLK<2:0> ILVDS_FRAME<2:0> ILVDS_DAT<2:0> The LVDS drive strength of the bit clock (LCLKP or LCLKN) and the frame clock (ADCLKP or ADCLKN) can be individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTN can also be programmed to the same value. 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 3 shows an example of how the drive strength of the bit clock is programmed (the method is similar for the frame clock and data drive strengths). Table 3. Bit Clock Drive Strength (1) (1) ILVDS_LCLK<2> ILVDS_LCLK<1> ILVDS_LCLK<0> LVDS DRIVE STRENGTH FOR LCLKP AND LCLKN 0 0 0 3.5mA (default) 0 0 1 2.5mA 0 1 0 1.5mA 0 1 1 0.5mA 1 0 0 7.5mA 1 0 1 6.5mA 1 1 0 5.5mA 1 1 1 4.5mA Current settings lower than 1.5mA are not recommended. LVDS INTERNAL TERMINATION PROGRAMMABILITY D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X EN_LVDS_TERM 1 X X X TERM_LCLK<2:0> 12 1 X 1 X X X X TERM_FRAME<2:0> X TERM_DAT<2:0> The LVDS buffers have high-impedance current sources driving the outputs. When driving traces whose characteristic impedance is not perfectly matched with the termination impedance on the receiver side, there may be reflections back to the LVDS output pins of the ADS5287 that cause degraded signal integrity. By enabling an internal termination (between the positive and negative outputs) for the LVDS buffers, the signal integrity can be significantly improved in such scenarios. To set the internal termination mode, the EN_LVDS_TERM bit should be set to '1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table 4 shows an example of how the internal termination of the LVDS buffer driving the bit clock is programmed (the method is similar for the frame clock and data drive strengths). These termination values are only typical values and can vary by up to ±20% across temperature and from device to device. Table 4. Bit Clock Drive Strengths TERM_LCLK<2> TERM_LCLK<1> TERM_LCLK<0> INTERNAL TERMINATION BETWEEN LCLKP AND LCLKN IN Ω 0 0 0 None 0 0 1 260 0 1 0 150 0 1 1 94 1 0 0 125 1 0 1 80 1 1 0 66 1 1 1 55 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 17 PRODUCT PREVIEW ADDRESS IN HEX ADS5287 www.ti.com SBAS428 – JANUARY 2008 LOW-FREQUENCY NOISE SUPPRESSION MODE ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 14 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X X X X X LFNS_CH<8:1> The low-frequency noise suppression mode is specifically useful in applications where good noise performance is desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of the ADS5287 to approximately fS/2, thereby moving the noise floor around dc to a much lower value. LFNS_CH<8:1> enables this mode individually for each channel. ANALOG INPUT INVERT ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 24 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X X X X X INVERT_CH<8:1> Normally, the INP pin represents the positive analog input pin, and INN represents the complementary negative input. Setting the bits marked INVERT_CH<8:1> (individual control for each channel) causes the inputs to be swapped. INN now represents the positive input, and INP the negative input. LVDS TEST PATTERNS PRODUCT PREVIEW ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 25 D7 D6 D5 D4 X 0 0 D3 D2 D1 0 X 0 DUALCUSTOM_PAT 0 0 X SINGLE_CUSTOM_PAT X X X X X X X X X 27 X X X X X X X X NAME EN_RAMP X 26 D0 X X BITS_CUSTOM1<9:8> BITS_CUSTOM2<9:8> BITS_CUSTOM1<7:0> BITS_CUSTOM2<7:0> 0 X PAT_DESKEW X 0 PAT_SYNC 45 The ADS5287 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern. The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the full-scale code, it returns back to zero code and ramps again. The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and programming the desired code in BITS_CUSTOM1<9:0>. In this mode, BITS_CUSTOM<9:0> take the place of the 10-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as normal ADC data are. The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT to '1'. The two codes are represented by the contents of BITS_CUSTOM1<9:0> and BITS_CUSTOM2<9:0>. In addition to custom patterns, the device may also be made to output two preset patterns: 1. Deskew patten: Set using PAT_DESKEW, this mode causes the 12 serial bits to come out as 010101010101 (the rightmost bit representing the first bit in the LSB-first mode) 2. Sync pattern: Set using PAT_SYNC, this mode causes the 12 serial bits to come out as 111111000000 (the rightmost bit representing the first bit in the LSB-first mode) Note that only one of the above patterns should be active at any given instant. 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 PROGRAMMABLE GAIN ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 X D6 X D5 D4 X D3 D2 D1 D0 NAME X X X X GAIN_CH1<3:0> X GAIN_CH2<3:0> 2A X X X X X X X X X X X X GAIN_CH3<3:0> GAIN_CH4<3:0> GAIN_CH5<3:0> X X X X GAIN_CH6<3:0> 2B X X X X GAIN_CH7<3:0> X X X X GAIN_CH8<3:0> In applications where the full-scale swing of the analog input signal is much less than the 2VPP range supported by the ADS5287, a programmable gain can be set to achieve the full-scale output code even with a lower analog input swing. The programmable gain not only fills the output code range of the ADC, but also enhances the SNR of the device by utilizing quantization information from some extra internal bits. The programmable gain for each channel can be individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain setting is coded in binary from 0dB to 12dB, as shown in Table 5. GAIN_CH1<2> GAIN_CH1<1> GAIN_CH1<0> CHANNEL 1 GAIN SETTING 0 0 0 0 0dB 0 0 0 1 1dB 0 0 1 0 2dB 0 0 1 1 3dB 0 1 0 0 4dB 0 1 0 1 5dB 0 1 1 0 6dB 0 1 1 1 7dB 1 0 0 0 8dB 1 0 0 1 9dB 1 0 1 0 10dB 1 0 1 1 11dB 1 1 0 0 12dB 1 1 0 1 Do not use 1 1 1 0 Do not use 1 1 1 1 Do not use Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 PRODUCT PREVIEW Table 5. Gain Setting for Channel 1 GAIN_CH1<3> 19 ADS5287 www.ti.com SBAS428 – JANUARY 2008 CLOCK, REFERENCE, AND DATA OUTPUT MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 1 1 X D1 D0 NAME X DIFF_CLK EN_DCC 42 1 X 1 X 1 1 1 1 EXT_REF_VCM X PHASE_DDR<1:0> X X BTC_MODE MSB_FIRST 46 1 1 X 1 X EN_SDR 1 1 FALL_SDR INPUT CLOCK The ADS5287 is configured by default to operate with a single-ended input clock—CLKP is driven by a CMOS clock and CLKN is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a differential input clock on CLKP and CLKN. Operating with a low-jitter differential clock usually gives better SNR performance, especially at input frequencies greater than 30MHz. In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'. PRODUCT PREVIEW EXTERNAL REFERENCE The ADS5287 can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode, the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The advantage of using the external reference mode is that multiple ADS5287 units can be made to operate with the same external reference, thereby improving parameters such as gain matching across devices. However, in applications that do not have an available high drive, differential external reference, the ADS5287 can still be driven with a single external reference voltage on the VCM pin. When EXT_REF_VCM is set as '1' (and the INT/EXT pin is set to '0'), the VCM pin is configured as an input pin, and the voltages on REFT and REFB are generated as shown in Equation 1 and Equation 2. VCM VREFT = 1.5V + 1.5V (1) VCM VREFB = 1.5V 1.5V (2) 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 BIT CLOCK PROGRAMMABILITY The output interface of the ADS5287 is normally a DDR interface, with the LCLK rising edge and falling edge transitions in the middle of alternate data windows. Figure 1 shows this default phase. ADCLKP LCLKP OUTP Figure 1. Default Phase of LCLK The phase of LCLK can be programmed relative to the output frame clock and data using bits PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 2. PHASE_DDR<1:0> = '10' ADCLKP ADCLKP LCLKP LCLKP OUTP OUTP PHASE_DDR<1:0> = '01' PRODUCT PREVIEW PHASE_DDR<1:0> = '00' PHASE_DDR<1:0> = '11' ADCLKP ADCLKP LCLKP LCLKP OUTP OUTP Figure 2. Phase Programmability Modes for LCLK Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 21 ADS5287 www.ti.com SBAS428 – JANUARY 2008 In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two manners shown in Figure 3. As shown in Figure 3, only the LCLK rising (or falling) edge is used to capture the output data in SDR mode. EN_SDR = '1', FALL_SDR = '0' ADCLKP LCLKP OUTP PRODUCT PREVIEW EN_SDR = '1', FALL_SDR = '1' ADCLKP LCLKP OUTP Figure 3. SDR Interface Modes The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high. DATA OUTPUT FORMAT MODES The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the MSB, and the output becomes binary two's complement mode. Also by default, the first two bits of the frame (following the rising edge of ADCLKP) are zeroes, followed by the LSB of the ADC output. Programming the MSB_FIRST mode inverts the bit order in the word. Thus, in the MSB_FIRST mode, the MSB is output as the first bit following the ADCLKP rising edge. The two zeroes come after the LSB at the end of the word. 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 APPLICATION INFORMATION The ADS5287 is an 8-channel, high-speed, CMOS ADC. Two zeroes are appended on the LSB side to the 10 bits given out by each channel. The resulting 12 bits are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the ADS5287 operate from a single clock (ADCLK). The sampling clocks for each of the eight channels are generated from the input clock using a carefully matched clock buffer tree. The 12x clock required for the serializer is generated internally from ADCLK using a phase-locked loop (PLL). A 6x and a 1x clock are also output in LVDS format, along with the data, to enable easy data capture. The ADS5287 operates from internally-generated reference voltages that are trimmed to achieve a high level of accuracy. Trimmed references improve the gain matching across devices, and provide the option to operate the devices without having to externally drive and route reference lines. The nominal values of REFT and REFB are 2.5V and 0.5V, respectively. The references are internally scaled down differentially by a factor of 2. This scaling results in a differential input of –1V to correspond to the zero code of the ADC, and a differential input of +1V to correspond to the full-scale code (1023 LSB). VCM (the common-mode voltage of REFT and REFB) is also made available externally through a pin, and is nominally 1.5V. The ADC employs a pipelined converter architecture that consists of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 10-bit level. The ADC output goes to a serializer that operates from a 12x clock generated by the PLL. The 12 data bits from each channel are serialized and sent LSB first. In addition to serializing the data, the serializer also generates a 1x clock and a 6x clock. These clocks are generated in the same way the serialized data are generated, so these clocks maintain perfect synchronization with the data. The data and clock outputs of the serializer are buffered externally using LVDS buffers. Using LVDS buffers to transmit data externally has multiple advantages, such as a reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the analog circuit inside the ADS5287. The ADS5287 operates from two sets of supplies and grounds. The analog supply and ground set is identified as AVDD and AVSS, while the digital set is identified by LVDD and LVSS. ANALOG INPUT The analog input consists of a switched-capacitor based, differential sample-and-hold architecture. This differential topology results in very good ac performance, even for high input frequencies at high sampling rates. The INN and INP pins must be externally biased around a common-mode voltage of 1.5V, available on VCM. For a full-scale differential input, each input pin (INN and INP) must swing symmetrically between VCM + 0.5V and VCM – 0.5V, resulting in a 2VPP differential input swing. The maximum input peak-to-peak differential swing is determined to be the difference between the internal reference voltages REFT (2.5V nominal) and REFB (0.5V nominal). Figure 4 illustrates the model of the input driving circuit. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 23 PRODUCT PREVIEW THEORY OF OPERATION ADS5287 www.ti.com SBAS428 – JANUARY 2008 5nH to 9nH (TQFP-80) 2nH to 3nH (QFN-64) IN OUT INP 1.5pF to 2.5pF 15W to 25W 5W to 10W 1W IN 1.5pF to 2.4pF 15W to 30W OUT IN 1000W to 1440W OUT OUT OUTP 0.2pF to 0.3pF IN OUTN 1000W to 1440W 16W to 32W 5W to 10W PRODUCT PREVIEW 5nH to 9nH (TQFP-80) 2nH to 3nH (QFN-64) 15W to 25W IN 1.5pF to 2.4pF OUT 15W to 30W IN OUT INN 1.5pF to 2.5pF Switches that are ON in SAMPLE phase. 1W Switches that are ON in HOLD phase. IN OUT Figure 4. Analog Input Circuit Model Input Common-Mode Current The input stage of all eight ADCs together sinks a common-mode current on the order of 2mA at 50MSPS. Equation 3 describes the dependency of the common-mode current and the sampling frequency. (2mA) ´ fS 50MSPS ac-coupling by increasing VCM by roughly 75mV. When operating above 50MSPS, it is recommended that additional parallel resistors be added externally to restore the input common-mode to at least 1.4V, if the inputs are to be ac-coupled. ADS5287 INP 1.2kW (3) Input Circuitry If the driving stage is dc-coupled to the inputs, then Equation 3 can be used to determine its common-mode drive capability and impedance. The inputs can also be ac-coupled to the INN and INP pins. In that case, the input common-mode is set by two internal 1.2kΩ resistors connecting the input pins to VCM. This architecture is shown in Figure 5. When the inputs are ac-coupled, there is a drop in the voltages at INP and INN relative to VCM. This can be computed from Equation 3. At 50MSPS, for example, the drop at each of the 16 input pins is 150mV, which is not optimal for ADC operation. The initialization register 5 described in the Initialization Registers table can be used to partially reduce the effect of this input common-mode drop during 24 1.2kW INN Internal Voltage Reference VCM CM Buffer Dashed area denotes one of eight channels. Figure 5. Common-Mode Biasing of Input Pins Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 Driving Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps to minimize this mismatch, and good performance is obtained for high-frequency input signals. An additional termination resistor pair is required between the two transformers, as shown in Figure 7. The center point of this termination is connected to ground to improve the balance between the positive and negative sides. The values of the terminations between the transformers and on the secondary side must be chosen to achieve an overall 50Ω (in the case of 50Ω source impedance). For optimum performance, the analog inputs must be driven differentially. This approach improves the common-mode noise immunity and even-order harmonic rejection. Input configurations using RF transformers suitable for low and high input frequencies are shown in Figure 6 and Figure 7, respectively. The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated by 50Ω resistor on the secondary side. Placing the termination on the secondary side helps to shield the kicks caused by the input sampling capacitors from the RF transformer leakage inductances. The termination is accomplished by two 25Ω resistors, connected in series, with the center point connected to the 1.5V common-mode. The 4.7Ω resistor in series with each input pin is required to damp the ringing caused by the device package parasitics. PRODUCT PREVIEW 4.7W 0.1mF INP 1:1 25W 0.1mF 25W 4.7W INN VCM Figure 6. Drive Circuit at Low Input Frequencies 1:2 2:1 INP 0.1mF 200W 0.1mF 200W 50W 50W INN VCM Figure 7. Drive Circuit at High Input Frequencies Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 25 ADS5287 www.ti.com SBAS428 – JANUARY 2008 CLOCK INPUT The eight channels on the device operate from a single ADCLK input. To ensure that the aperture delay and jitter are the same for all channels, a clock tree network is used to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point to the sampling circuit. This architecture ensures that the performance and timing for all channels are identical. The use of the clock tree for matching introduces an aperture delay that is defined as the delay between the rising edge of ADCLK and the actual instant of sampling. The aperture delays for all the channels are matched to the best possible extent. A mismatch of ±20ps (±3σ) could exist between the aperture instants of the eight ADCs within the same chip. However, the aperture delays of ADCs across two different chips can be several hundred picoseconds apart. PRODUCT PREVIEW The ADS5287 can be made to operate either in CMOS single-ended clock mode (default is DIFF_CLK = 0) or differential clock mode (SINE, LVPECL, or LVDS). When operating in the single-ended clock mode, CLKN must be forced to 0VDC, and the single-ended CMOS applied on the CLKP pin. This operation is shown in Figure 8. CMOS Single-Ended Clock VCM VCM 5kW 5kW CLKP CLKN Figure 9. Internal Clock Buffer 0.1mF CLKP Differential Sine-Wave, PECL, or LVDS Clock Input 0.1mF CLKN Figure 10. Differential Clock Driving Circuit (DIFF_CLK = 1) CLKP 0.1mF CMOS Clock Input 0V CLKP CLKN 0.1mF Figure 8. Single-Ended Clock Driving Circuit (DIFF_CLK = 0) When configured to operate in the differential clock mode (register bit DIFF_CLK = 1) the ADS5287 clock inputs can be driven differentially (SINE, LVPECL, or LVDS) with little or no difference in performance between them, or with a single-ended (LVCMOS). The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors, as shown in Figure 9. This method allows using transformer-coupled drive circuits for a sine wave clock or ac-coupling for LVPECL and LVDS clock sources, as shown in Figure 10. When operating in the differential clock mode, the single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKN (pin 11) connected to ground with a 0.1µF capacitor, as shown in Figure 11. 26 CLKN Figure 11. Single-Ended Clock Driving Circuit When DIFF_CLK = 1 For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass filtering of the clock source can help reduce the effect of jitter. If the duty cycle deviates from 50% by more than 2% or 3%, it is recommended to enable the DCC through register bit EN_DCC. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 ADS5287 www.ti.com SBAS428 – JANUARY 2008 INPUT OVER-VOLTAGE RECOVERY ADS5287 The differential peak-to-peak full-scale range supported by the ADS5287 is nominally 2.0V. The ADS5287 is specially designed to handle an over-voltage condition where the differential peak-to-peak voltage can be up to twice the ADC full-scale range. If the input common-mode is not considerably off from VCM during overload (less than 300mV around the nominal value of 1.5V), recovery from an over-voltage pulse input of twice the amplitude of a full-scale pulse is expected to be within one clock cycle when the input switches from overload to zero signal. ISET REFT REFB 0W to 2W 0.1mF 2.2mF 56.2kW 0W to 2W 2.2mF 0.1mF The digital beam-forming algorithm in an ultrasound system relies on gain matching across all receiver channels. A typical system would have about 12 octal ADCs on the board. In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the ADCs to be the same. Matching references within the eight channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures that the reference voltages are well-matched across different chips. All bias currents required for the internal operation of the device are set using an external resistor to ground at the ISET pin. Using a 56.2kΩ resistor on ISET generates an internal reference current of 20µA. This current is mirrored internally to generate the bias current for the internal blocks. Using a larger external resistor at ISET reduces the reference bias current and thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56.2kΩ so that the internal bias margins for the various blocks are proper. Buffering the internal bandgap voltage also generates the common-mode voltage VCM, which is set to the midlevel of REFT and REFB, and is accessible on pin 53. It is meant as a reference voltage to derive the input common-mode if the input is directly coupled. It can also be used to derive the reference common-mode voltage in the external reference mode. The suggested decoupling for the reference pins is shown in Figure 12. The device also supports the use of external reference voltages. There are two methods to force the references externally. The first method involves pulling INT/EXT low and forcing externally REFT and REFB to 2.5V and 0.5V nominally, respectively. In this mode, the internal reference buffer goes to a 3-state output. The external reference driving circuit should be designed to provide the required switching current for the eight ADCs inside the chip. It should be noted that in this mode, VCM and ISET continue to be generated from the internal bandgap voltage, as in the internal reference mode. It is therefore important to ensure that the common-mode voltage of the externally-forced reference voltages matches to within 50mV of VCM. The second method of forcing the reference voltages externally can be accessed by pulling INT/EXT low, and programming the serial interface to drive the external reference mode through the VCM pin (register bit called EXT_REF_VCM). In this mode, VCM becomes configured as an input pin that can be driven from external circuitry. The internal reference buffers driving REFT and REFB are active in this mode. Forcing 1.5V on the VCM pin in the mode results in REFT and REFB coming to 2.5V and 0.5V, respectively. In general, the voltages on REFT and REFB in this mode are given by Equation 4 and Equation 5, respectively: VCM VREFT = 1.5V + 1.5V (4) VCM VREFB = 1.5V 1.5V (5) Table 6 describes the state of the reference voltage internal buffers during various combinations of the PD, INT/EXT, and EXT_REF_VCM register bits. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 27 PRODUCT PREVIEW Figure 12. Suggested Decoupling on the Reference Pins REFERENCE CIRCUIT ADS5287 www.ti.com SBAS428 – JANUARY 2008 Table 6. State of Reference Voltages for Various Combinations of PD and INT/EXT REGISTER BIT (1) INTERNAL BUFFER STATE PD 0 0 1 1 0 0 1 1 INT/EXT 0 1 0 1 0 1 0 1 EXT_REF_VCM 0 0 0 0 1 1 1 1 REFT buffer 3-state 2.5V 3-state 2.5V (1) 1.5V + VCM/1.5V Do not use 2.5V (1) Do not use REFB buffer 3-state 0.5V 3-state 0.5V (1) 1.5V – VCM/1.5V Do not use 0.5V (1) Do not use VCM pin 1.5V 1.5V 1.5V 1.5V Force Do not use Force Do not use Weakly forced with reduced strength. NOISE COUPLING ISSUES PRODUCT PREVIEW High-speed mixed signals are sensitive to various types of noise coupling. One primary source of noise is the switching noise from the serializer and the output buffers. Maximum care is taken to isolate these noise sources from the sensitive analog blocks. As a starting point, the analog and digital domains of the device are clearly demarcated. AVDD and AVSS are used to denote the supplies for the analog sections, while LVDD and LVSS are used to denote the digital supplies. Care is taken to ensure that there is minimal interaction between the supply sets within the device. The extent of noise coupled and transmitted from the digital to the analog sections depends on: 1. The effective inductances of each of the supply and ground sets. 2. The isolation between the digital and analog supply and ground sets. 28 Smaller effective inductance of the supply and ground pins leads to better noise suppression. For this reason, multiple pins are used to drive each supply and ground. It is also critical to ensure that the impedances of the supply and ground lines on the board are kept to the minimum possible values. Use of ground planes in the printed circuit board (PCB) as well as large decoupling capacitors between the supply and ground lines are necessary to obtain the best possible SNR performance from the device. It is recommended that the isolation be maintained onboard by using separate supplies to drive AVDD and LVDD, as well as separate ground planes for AVSS and LVSS. The use of LVDS buffers reduces the injected noise considerably, compared to CMOS buffers. The current in the LVDS buffer is independent of the direction of switching. Also, the low output swing as well as the differential nature of the LVDS buffer results in low-noise coupling. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5287 PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5287IRGCR PREVIEW QFN RGC 64 2000 TBD Call TI Call TI ADS5287IRGCT PREVIEW QFN RGC 64 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee® Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated