SAMSUNG S3P863A

S3C8639/C863A/P863A
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide
range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned
to specific interrupt levels.
S3C8639/C863A/P863A MICROCONTROLLERS
S3C8639/C863A/P863A single-chip 8-bit
microcontrollers are based on the powerful SAM8
CPU architecture. The internal register file is logically
expanded to increase the on-chip register space.
S3C8639/C863A/P863A contain 32/48 Kbytes of onchip program ROM.
In line with Samsung's modular design approach, the
following peripherals are integrated with the SAM8
core:
— Four programmable I/O ports (total 27 pins)
— One 8-bit basic timer for oscillation stabilization
and watchdog functions
— One 8-bit general-purpose timer/counter with
selectable clock sources
— One 12-bit counter with selectable clock sources,
including Hsync or Csync input
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,
Csync input, and Clamp signal output)
— DDC Multi-master and slave-only IIC-Bus
— 4-channel A/D converter (8-bit resolution)
S3C8639/C863A/P863A are a versatile
microcontrollers which are ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, A/D converter, and multi-master
IIC-bus support with DDC. They are available in a
42-pin SDIP or a 44-pin QFP package.
— One interval timer
OTP
S3C8639/C863A microcontrollers are also available in OTP (One Time Programmable) version named,
S3P863A. S3P863A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of
masked ROM. S3P863A is comparable to S3C8639/C863A, both in function and pin configuration except its
ROM size.
1-1
PRODUCT OVERVIEW
S3C8639/C863A/P863A
FEATURES
CPU
•
SAM88RC CPU core
Memory
•
•
Low Voltage Reset (LVR)
•
LVR level is 2.4 V ± 200 mV
Pulse Width Modulator (PWM)
S3C8639: 32-Kbyte internal program memory
(ROM)
S3C863A: 48-Kbyte internal program memory
(ROM)
•
S3C8639: 784-byte general-purpose
register area
S3C863A: 1040-byte general-purpose
register area
•
Vsync-I, Hsync-I, Csync-I input and Vsync-O,
Hsync-O, Clamp-O output pins
•
Programmable Pseudo sync signal generation
•
Auto SOG detection
Instruction Set
8-bit PWM: 7-CH
(6-bit basic frame with 2-bit extension)
Sync-Processor Block
•
Auto H-/V-sync polarity detection
•
78 instructions
•
Composite sync detection
•
IDLE and STOP instructions added for
power-down modes
DDC Multi-Master IIC-Bus 1-Ch
Instruction Execution Time
•
Minimum 333 ns (with 12 MHz CPU clock)
Interrupts
•
Ten interrupt sources/vectors
•
Eight interrupt level
•
Fast interrupt feature
•
Serial Peripheral Interface
•
Support for Display Data Channel
(DDC1/DDC2B/DDC2Bi/DDC2B+)
Slave Only IIC-Bus 1-Ch
•
A/D Converter
•
General I/O
•
Four I/O Ports (total 27pins)
8-Bit Basic Timer
Serial Peripheral Interface
4-channel; 8-bit resolution
Oscillator Frequency
•
8 MHz to 12 MHz crystal operation
•
Internal Max. 12 MHz CPU clock
•
Programmable timer for oscillation stabilization
interval control or watchdog timer function
Operating Temperature Range
•
Three selective internal clock frequencies
•
Timer/Counters
•
One 8-bit Timer/Counter with several clock
sources (Capture mode)
•
One 12-bit Counter with H-/C-sync and several
clock sources
•
1-2
One Interval Timer
– 40 °C to + 85 °C
Operating Voltage Range
•
3.0 V to 5.5 V
Package Types
•
42-pin SDIP, 44-pin QFP
S3C8639/C863A/P863A
PRODUCT OVERVIEW
BLOCK DIAGRAM
RESET
P0.0-P0.7/INT0-INT2
P2.0-P2.7
Port 0
Port 2
INT0-INT2
XIN
XOUT
VDD1, VDD2
VSS1, V SS2
TEST
Main
Osc
Port 1
P1.0-P1.2
Port 3
P3.0-P3.7
ADC
AD0-AD3
I/O Port and Interrupt
Control
PWM0
8-Bit
PWM
(7-Ch)
PWM6
Vsync-I
Hsync-I
Csync-I
Vsync-O
Hsync-O
Clamp-O
TM0CAP
SAM8 CPU
SyncProcessor
8-Bit
Counter
(Timer M0)
* S3C8639
- 32 Kbyte ROM
- 784 Byte RAM
* S3C863A
- 48 Kbyte ROM
- 1040 Byte RAM
32/48Kbyte
ROM
12-Bit
Counter
(Timer M1)
784/1040Byte
Register File
Interval
Timer
(Timer M2)
Slave
Only
IIC-Bus
SCL1
SDA1
Multi-master IIC-Bus
and DDC1/2B/2Bi/2B+
SCL0
SDA0
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C8639/C863A/P863A
PIN ASSIGNMENTS
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
P0.4/TM0CAP
P0.5
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
VDD1
VSS1
XOUT
XIN
TEST (GND)
SDA0
SCL0
RESET
P1.2
P2.0/PWM0
P2.1/PWM1
NOTE:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3C8639
/C863A
(42-SDIP)
The TEST pin must connect to V
SS (GND)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
VDD2
VSS2
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
in the normal operation mode.
Figure 1-2. S3C8639/C863A 42-SDIP Pin Assignment
1-4
PRODUCT OVERVIEW
44
43
42
41
40
39
38
37
36
35
34
P0.4/TM0CAP
P0.3
P0.2/INT2
P0.1/INT1
N.C.
P0.0/INT0
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
S3C8639/C863A/P863A
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
S3C8639
/C863A
44-QFP
(Top View)
P3.2/AD2
P3.1/AD1
P3.0/AD0
VDD2
VSS2
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P1.2
P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
N.C.
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
P2.6/PWM6
SCL0
NOTE:
RESET
12
13
14
15
16
17
18
19
20
21
22
P0.5
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
VDD1
VSS1
XOUT
XIN
TEST (GND)
SDA0
The TEST pin must connect to V
SS (GND)
in the normal operation mode.
Figure 1-3. S3C8639/C863A 44-QFP Pin Assignment
1-5
PRODUCT OVERVIEW
S3C8639/C863A/P863A
PIN DESCRIPTIONS
Table 1-1. S3C8639/C863A Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
SDIP Pin
Numbers
Shared
Functions
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
I/O
General-purpose, 8-bit I/O port. Shared
functions include three external interrupt inputs
and I/O for timer M0. Selective configuration of
port 0 pins to input or output mode is
supported.
D-1
D-1
D-1
D-1
D-1
D-1
D-1
D-1
1
2
3
4
5
6
7
8
INT0
INT1
INT2
P1.0
P1.1
P1.2
I/O
General-purpose, 8-bit I/O port. Selective
configuration is available for port 1 pins to
input, push-pull output, n-channel open-drain
mode, or IIC-bus clock and data I/O.
E-1
E-1
E-1
9
10
19
SDA1
SCL1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
I/O
General-purpose, 8-bit I/O port Selective
configuration of port 2 pins to input or output
mode is supported. The port 2 pin circuits are
designed to push-pull PWM output and Csync
(SOG) signal input.
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
20
21
22
23
24
25
26
32
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
P3.0–P3.3
P3.4–P3.7
I/O
General-purpose, 8-bit I/O port Selective
configuration port 3 pins to input or output
mode is supported. Multiplexed for alternative
use as A/D converter inputs AD0–AD3.
E-1
E
35–38
39–42
AD0–AD3
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
SCL0
I
I
O
O
O
I/O
I/O
The pins are sync processor signal I/O and IICbus clock and data I/O.
A-3
A-3
A
A
A
G-3
G-3
31
30
27
28
29
16
17
–
TM0CAP
VDD1, VSS1,
VDD2, VSS2
–
Power pins
–
–
11, 12
34, 33
–
XIN, XOUT
–
System clock I/O pins
–
14, 13
–
RESET
I
System RESET pin
B
18
–
TEST
I
Factory test pin input
0 V: Normal operation, 5 V: Factory test mode
–
15
–
1-6
S3C8639/C863A/P863A
PRODUCT OVERVIEW
PIN CIRCUITS DIAGRAM
VDD
VDD
Input
Data
Output
Output
300 kΩ
Typical
VSS
VSS
VSS
Figure 1-5. Pin Circuit Type A-3
Figure 1-4. Pin Circuit Type A
VDD
Data or
Other
Function
VDD
Output
Disable
280 kΩ
RESET
Output
Noise
Filter
VSS
Digital Input,
TTL Input
NOTE:
Figure 1-6. Pin Circuit Type B (RESET)
The noise filter must be built in the
external interrupts.
Figure 1-7. Pin Circuit Type D-1
1-7
PRODUCT OVERVIEW
S3C8639/C863A/P863A
VDD
Typical
47 kΩ
VDD
Pull-up
Enable
Data
VDD
Output
Open
Drain
Data
Output
Open
Drain
Output
Disable
VSS
Digital Input
or ADC Input
Output
Disable
VSS
Input
Figure 1-8. Pin Circuit Type E
Figure 1-9. Pin Circuit Type E-1
Output
Data
VSS
Input
Figure 1-10. Pin Circuit Type G-3
1-8
S3C8639/C863A/P863A
19
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, S3C8639/C863A electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in stop mode
— Stop mode release timing when initiated by a reset
— I/O capacitance
— A/D Converter electrical characteristics
— A.C. electrical characteristics
— Input timing measurement points for P0.0–P0.2 and TM0CAP
— Oscillation characteristics
— Oscillation stabilization time
— Clock timing measurement points for XIN
— Schmitt trigger characteristics
— Power-on reset circuit characteristics
19-1
ELECTRICAL DATA
S3C8639/C863A/P863A
Table 19-1. Absolute Maximum Ratings
(TA = 25°C)
Symbol
Conditions
Rating
Unit
Supply voltage
Parameter
VDD
–
– 0.3 to + 6.5
V
Input voltage
VI1
Type G-3 (n-channel open drain)
VI2
All port pins except VI1
– 0.3 to VDD + 0.3
Output voltage
VO
All output pins
– 0.3 to VDD + 0.3
Output current
High
I OH
One I/O pin active
– 10
All I/O pins active
– 60
Output current
Low
I OL
One I/O pin active
+ 30
Total pin current except port 3
+ 100
Sync-processor I/O pins and IIC-bus
clock and data pins
–
+ 150
Operating
temperature
Storage
temperature
TA
TSTG
– 0.3 to + 7.0
mA
°C
– 40 to + 85
–
– 65 to + 150
Table 19-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)
Min
Typ
Max
Unit
Input High
Parameter
VIH1
All input pins except VIH2, VIH3 and VIH4
0.8 VDD
–
VDD
V
voltage
VIH2
XIN
VDD–0.5
VDD
VIH3
TTL input (Hsync-I, Vsync-I, and Csync-I)
2.0
VDD
VIH4
SCL0/SDA0, SCL1/SDA1
0.7VDD
VDD
Input Low
VIL1
All input pins except VIL2 and VIL3
–
0.2 VDD
voltage
VIL2
XIN
VIL3
TTL input (Hsync-I, Vsync-I, and Csync-I)
VIL4
SCL0/SDA0, SCL1/SDA1
VOH1
VDD = 5 V ± 10%; IOH = – 15 mA;
Port 3.6–3.7
VOH2
VDD = 5 V ± 10%; IOH = – 4 mA;
Port 1.2, Port 3.0–3.5
VOH3
VDD = 5 V ± 10%; IOH = – 2 mA;
Port 0, 2, Clamp-O, H, and Vsync-O
VOH4
VDD = 5 V ± 10%; IOH = – 6 mA;
Port 1.0–P1.1, SCL0 and SDA0
Output High
voltage
19-2
Symbol
Conditions
0.4
0.8
0.3VDD
VDD – 1.0
–
S3C8639/C863A/P863A
ELECTRICAL DATA
Table 19-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
–
–
0.4
V
VOL1
VDD = 5 V ± 10%; IOL = 15 mA
Port 3.6–3.7
VOL2
VDD = 5 V ± 10%; IOL = 4 mA
Port 3.0–3.5 and Port 1.2
0.4
VOL3
VDD = 5 V ± 10%; IOL = 2 mA
Port 0, 2, Clamp-O, H, and Vsync-O
0.4
VOL4
VDD = 5 V ± 10%; IOL = 6 mA
Port 1.0–1.1; SCL0 and SDA0
0.6
ILIH1
VIN = VDD
All input pins except XIN, XOUT
–
–
3
ILIH2
VIN = VDD; XOUT only
–
–
20
ILIH3
VIN = VDD; XIN only
2.5
6
20
ILIL1
VIN = 0 V; All input pins except XIN,
XOUT, RESET , HsyncI & VsyncI
–
–
–3
ILIL2
VIN = 0 V; XOUT only
–
–
– 20
ILIL3
VIN = 0 V; XIN only
– 2.5
–6
– 20
Output High
leakage current
ILOH1
VOUT = VDD
–
–
3
Output Low
leakage current
ILOL1
VOUT = 0 V
–
–
–3
Pull-up resistor
RU1
VIN = 0 V; VDD = 5 V ± 10%
Ports 3.7–3.4
20
47
80
RU2
VIN = 0 V; VDD = 5 V ± 10%
RESET only
150
280
480
Pull-down
resistor
RD
VIN = 0 V; VDD = 5 V ± 10%
HsyncI & VsyncI
150
300
500
Supply current
IDD1
VDD = 5 V ± 10%
Operation mode; 12 MHz crystal
C1 = C2 = 22pF
–
10
20
IDD2
VDD = 5 V ± 10%
Idle mode; 12 MHz crystal
C1 = C2 = 22pF
4
8
IDD3
VDD = 5 V ± 10%
Stop mode
100
150
Output Low
voltage
Input High
leakage current
Input Low
leakage current
(note)
µA
kΩ
mA
µA
NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.
19-3
ELECTRICAL DATA
S3C8639/C863A/P863A
Table 19-3. Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
VDDDR
Stop mode
2
–
5.5
V
Data retention
supply current
IDDDR
Stop mode, VDDDR = 2.0 V
–
–
5
µA
NOTES:
1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped.
2.
Supply current does not include drawn through internal pull–up resistors and external output current loads.
RESET
occurs
~
~
Oscillation
Stabilzation
Time
Stop Mode
Data Retention Mode
~
~
VDD
Normal
Operating
Mode
VDDDR
Execution of
STOP Instrction
RESET
NOTE: t WAIT is the same as 4096 x 16 x 1/f
tWAIT
OSC.
Figure 19-1. Stop Mode Release Timing When Initiated by a Reset
Table 19-4. Input/Output Capacitance
(TA = –40 °C to + 85 °C, VDD = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
capacitance
CIN
f = 1 MHz; unmeasured pins
are connected to VSS
–
–
10
pF
Output
capacitance
COUT
I/O capacitance
19-4
CIO
S3C8639/C863A/P863A
ELECTRICAL DATA
Table 19-5. A/D Converter Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Resolution
VDD = 5 V
Conversion time = 5 µs
Total accuracy
Min
Typ
Max
Unit
–
8
–
bit
–
–
±2
LSB
Integral linearity error
ILE
AVREF = 5 V
–
±1
Differential linearity error
DLE
AVSS = 0 V
–
±1
Offset error of top
EOT
±1
±2
Offset error of bottom
EOB
± 0.5
±2
Conversion time (1)
tCON
8 bit conversion
40 x n/fOSC (3), n=1,4,8,16
20
–
170
µs
Analog input voltage
VIAN
–
AVSS
–
AVREF
V
Analog input impedance
RAN
–
2
1000
–
MΩ
Analog reference voltage
AVREF
–
2.5
–
VDD
V
Analog ground
AVSS
–
VSS
–
VSS + 0.3
V
Analog input current
IADIN
AVREF = VDD = 5V
–
–
10
µA
Analog block Current (2)
IADC
AVREF = VDD = 5V
–
1
3
mA
AVREF = VDD = 3V
0.5
1.5
mA
AVREF = VDD = 5V
When power down mode
100
500
nA
NOTES:
1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.
2. IADC is an operating current during the A/D conversion.
3. fOSC is the main oscillator clock.
19-5
ELECTRICAL DATA
S3C8639/C863A/P863A
Table 19-6. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5V)
Parameter
Noise Filter
Symbol
tNF1H
tNF1L
tNF2
Conditions
INT0–2 and TM0CAP (RC
delay)
RESET only (RC delay)
tNF1L
Min
Typ
Max
Unit
300
–
–
ns
1000
–
–
tNF1H
tNF2
0.8 VDD
0.2 VDD
Figure 19-2. Input Timing Measurement Points for P0.0–P0.2 and TM0CAP
19-6
S3C8639/C863A/P863A
ELECTRICAL DATA
Table 19-7. Oscillation Characteristics
(TA = – 40 °C + 85 °C)
Oscillator
Main crystal or
ceramic
Clock Circuit
Conditions
C1
XIN
Min
Typ
Max
Unit
VDD = 3.0 V to 5.5 V
8
–
12
MHz
VDD = 3.0 V to 5.5 V
8
–
12
MHz
XOUT
C2
External clock
(main)
XIN
XOUT
NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot
select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.
Table 19-8. Oscillation Stabilization Time
(TA = – 40 °C + 85 °C, VDD = 3.0 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
ms
Crystal
VDD = 3.0 V to 5.5 V
–
–
20
Ceramic
VDD = 3.0 V to 5.5V
–
–
10
External clock
XIN input high and low level width
(tXH, tXL)
25
–
500
ns
NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a
power-on occurs, or when Stop mode is released.
1/fx
tXL
tXH
XIN
VDD - 0.5 V
0.4 V
Figure 19-3. Clock Timing Measurement Points for XIN
19-7
ELECTRICAL DATA
S3C8639/C863A/P863A
VOUT
VDD
A = 0.2 V DD
B = 0.4 V DD
C = 0.6 V DD
D = 0.8 V DD
VSS
A
B
C
D
VIN
Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)
Table 19-9. Power-on Reset Circuit Characteristics
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)
Parameter
Min
Typ
Max
Unit
VODLVD
2.7
–
5.5
V
VLVD
2.2
2.4
2.6
V
Power supply voltage
rise time
tr
10
–
(1)
us
Power supply voltage off
time
toff
10
–
–
ms
Power-on reset circuit
consumption current (2)
IDDPR
VDD = 5 V ± 10%
100
150
µA
VDD = 3 V
60
100
µA
Power-on reset release
voltage
Power-on reset detection
voltage
Symbol
Conditions
NOTES:
1. 216/fOSC (= 5.46 ms at fOSC/12MHz)
2.
19-8
Current contained when power-on reset circuit is provided internally.
S3C8639/C863A/P863A
ELECTRICAL DATA
VDD
VDDLVD
VLVD
toff
tr
Figure 19-5. Power-on Reset Timing
19-9
S3C8639/C863A/P863A
20
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The S3C8639/C863A microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP600) and a 44-QFP package (Samsung part number 44-QFP-1010B).
#22
0.2
5
42-SDIP-600
+0
- 0 .1
.05
0-15
15.24
14.00 ± 0.2
#42
(1.77)
NOTE:
1.00 ± 0.1
1.778
5.08 MAX
0.50 ± 0.1
± 0.3
39.10 ± 0.2
3.30
39.50 MAX
3.50 ± 0.2
#21
0.51 MIN
#1
Dimensions are in millimeters.
Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
20-1
MECHANICAL DATA
S3C8639/C863A/P863A
13.20 ± 0.3
0-8
10.00 ± 0.2
10.00 ± 0.2
+ 0.10
- 0.05
0.10 MAX
44-QFP-1010B
0.80 ± 0.20
13.20 ± 0.3
0.15
#44
#1
+ 0.10
0.35 - 0.05
0.80
0.05 MIN
(1.00)
2.05 ± 0.10
2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
20-2
S3C8639/C863A/P863A
21
S3P863A OTP
S3P863A OTP
OVERVIEW
The S3P863A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C8639/C863A microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P863A is fully compatible with the S3C8639/C863A, both in function and in pin configuration. Because of
its simple programming requirements, the S3P863A is ideal for use as an evaluation chip for the
S3C8639/C863A.
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
P0.4/TM0CAP
P0.5
P0.6
P0.7
SDAT/P1.0/SDA1
SCLK/P1.1/SCL1
VDD1
VSS
XOUT
XIN
VPP/TEST (GND)
SDA0
SCL0
RESET/RESET
P1.2
P2.0/PWM0
P2.1/PWM1
NOTE:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3P863A
42-SDIP
(Top View)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
VDD2
VSS2
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
The bolds indicate an OTP pin name.
Figure 21-1. S3P863A Pin Assignments (42-SDIP Package)
21-1
S3C8639/C863A/P863A
44
43
42
41
40
39
38
37
36
35
34
P0.4/TM0CAP
P0.3
P0.2/INT2
P0.1/INT1
N.C.
P0.0/INT0
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
S3P863A OTP
1
2
3
4
5
6
7
8
9
10
11
S3P863A
44-QFP
(Top View)
33
32
31
30
29
28
27
26
25
24
23
P3.2/AD2
P3.1/AD1
P3.0/AD0
VDD2
VSS2
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P1.2
P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
N.C.
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
P2.6/PWM6
SCL0
NOTE:
RESET /RESET
12
13
14
15
16
17
18
19
20
21
22
P0.5
P0.6
P0.7
SDAT/P1.0/SDA1
SCLK/P1.1/SCL1
VDD1
VSS1
XOUT
XIN
VPP/TEST (GND)
SDA0
The bolds indicate an OTP pin name.
Figure 21-2. S3P863A Pin Assignments (44-QFP Package)
21-2
S3C8639/C863A/P863A
S3P863A OTP
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P1.0
SDAT
9 (4)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a
Input/push-pull output port.
P1.1
SCLK
10 (5)
I
Serial clock pin. Input only pin.
TEST
VPP (TEST)
15 (10)
I
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
RESET
RESET
18 (13)
I
Chip Initialization
VDD1/VSS1
VDD1/VSS1
11/12 (6/7)
I
Logic power supply pin. VDD should be tied to +5 V
during programming.
NOTE: Parentheses indicate 44-QFP OTP pin number.
Table 21-2. Comparison of S3P863A and S3C8639/C863A Features
Characteristic
S3P863A
S3C8639/C863A
Program Memory
48-Kbyte EPROM
32/48-Kbyte mask ROM
Operating Voltage (VDD)
3.0 V to 5.5 V
3.0 V to 5.5V
OTP Programming Mode
VDD = 5 V, VPP (TEST)=12.5V
Pin Configuration
42SDIP, 44QFP
42SDIP, 44QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P863A, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 21-3. Operating Mode Selection Criteria
VDD
VPP (TEST)
REG/MEM
Address (A15–A0)
R/W
Mode
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
21-3
S3P863A OTP
S3C8639/C863A/P863A
D.C. ELECTRICAL CHARACTERISTICS
Table 21-4. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Input High
leakage current
ILIH1
Min
Typ
Max
Unit
VIN = VDD
All input pins except XIN, XOUT
–
–
3
µA
ILIH2
VIN = VDD; XOUT only
–
–
20
ILIH3
VIN = VDD; XIN only
2.5
6
20
ILIL1
VIN = 0 V; All input pins except XIN,
XOUT, RESET , Hsync-I and Vsync-I
–
–
–3
ILIL2
VIN = 0 V; XOUT only
–
–
– 20
ILIL3
VIN = 0 V; XIN only
– 2.5
–6
– 20
Output High
leakage current
ILOH1
VOUT = VDD
–
–
3
Output Low
leakage current
ILOL1
VOUT = 0 V
–
–
–3
Pull-up resistor
RU1
VIN = 0 V; VDD = 5 V ± 10%
Port 3.7–3.4
20
47
80
RU2
VIN = 0 V; VDD = 5 V ± 10%
RESET only
150
280
480
Pull-down
resistor
RD
VIN = 0 V; VDD = 5 V ± 10%
Hsync-I and Vsync-I
150
300
500
Supply current
IDD1
VDD = 5 V ± 10%
Operation mode; 12 MHz crystal
C1 = C2 = 22pF
–
10
20
IDD2
VDD = 5 V ± 10%
Idle mode; 12 MHz crystal
C1 = C2 = 22pF
4
8
IDD3
VDD = 5 V ± 10%
Stop mode
100
150
Input Low
leakage current
(note)
Conditions
NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.
21-4
kΩ
mA
µA