S3C8454/P8454 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM87 RC PRODUCT FAMILY Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RC microcontrollers have an external interface that provides access to external memory and other peripheral devices. The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C8454 MICROCONTROLLER The S3C8454 single-chip microcontroller is fabricated using a highly advanced CMOS process. Its design is based on the powerful SAM87RC CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. The size of the internal register file is logically expanded, increasing the addressable on-chip register space to 1040 bytes. A flexible yet sophisticated external interface is used to access up to 64-Kbytes of program and data memory. The S3C8454 is a versatile microcontroller that is ideal for use in a wide range of general-purpose applications such as CD-ROM/DVD-ROM drives. Using the SAM87RC modular design approach, the following peripherals were integrated with the SAM87RC CPU core: — Five configurable 8-bit general I/O ports — One 2-bit general I/O ports — Full-duplex serial data port with one synchronous operating modes — Two 8-bit timers with interval timer — Two 16-bit timers/counters with PWM operating modes or capture modes — One voltage level detector pin — Four embedded chip selection pins (CS0–CS4) or normal I/O ports — Two programmable 8-bit PWM modules with corresponding output pins — A/D converter with 4 selectable input pins OTP The S3C8454 microcontroller is also available in OTP(One Time Programmable) version, S3P8454 The S3P8454 microcontroller has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM. The S3P8454 is comparable to S3C8454, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS88C4504/P4504 FEATURES CPU General I/O Ports • • Five 8-bit general I/O ports (port 0, 1, 2, 3, 4) • One 2-bit general I/O port (port 5) • Port 2 can drive LED directly SAM87RC CPU core Memory • 1040-byte internal register file • 4-Kbyte internal program memory External Interface • 64 Kbyte external data memory • 64 Kbyte external program memory area (ROMless) • 60 Kbyte external program memory and 4 Kbyte internal program memory ADC • Can be used as a general input/output port • 8-bit resolution four channels SIO Interrupts • Six edge-driven external interrupts • Two level-driven external interrupts • Fast interrupt mode processing PWM • Four output channels (PWM0, PWM1, TCPWM, TDPWM) • 8-bit resolution with a 4-bit prescaler (PWM0, PWM1) • From 16-bit counter (Timer C/D) (TCPWM, TDPWM) Embedded chip selection • 8-bit transmit/receive mode • 8-bit receive mode • LSB-first or MSB-first transmission selectable • Internal or external clock mode • Voltage level detector • 8-bit Timers • Two 8-bit timers with interval timer mode (Timer A and B) 16-bit Timer/Counters To reduce interface glue logic, chip selection logic is bold To prevent MCU from malfunctioning in an unstable power level, a voltage level detector circuit is inserted Operating Voltage Range • 2.7 V to 5.5 volts (@12 MHz) • Two programmable 16-bit timer/counters Operating Temperature Range • Interval, or event counter mode operation • • 16-bit capture and 16-bit PWM mode • Internal or external clock source – 40 °C to + 85 °C Package Types • 80-pin QFP or TQFP Basic Timer (Watchdog Timer) • Overflow signal makes a system reset Operating frequency • 8-bit timer with interval timer mode • 1-2 25 MHz (4.5 V to 5.5 V) S3C8454/P8454 PRODUCT OVERVIEW BLOCK DIAGRAM External Address/Data (A0-A7) (A8-A15) (D0-D7) External Interface Block RESET EA P5.1 P5.0(WAIT ) SAM8 BUS SO SI SCK Port 1 P1.0-P1.4 P1.5-P1.7/ SI, SO, SCK Port 2 P2.0-P2.7/ INT0-INT7 Port 3 P3.0-P3.7/ TDCK, TCCK TDCAP, TCCAP TCOUT, TDOUT PWM0, PWM1 Watchdog Timer Port4/ Chip Selection Logic SAM87 RC CPU Timers A and B TCCK TDCK TCOUT TDOUT P0.0-P0.3 P0.4-P0.7/ ADC0-ADC3 Port 5 Port I/O & Interrupt Control P4.0-P4.7/ CS0-CS4 Port 0 Timers C and D 1040-Byte Register File Serial Port SAM8 BUS AVSS (Internal) AVREF A/D Converter ADC0/P0.4ADC3/P0.7 4-Kbyte ROM VDD1, VSS1 VDD2, VSS2 PWM Module PWM0 PWM1 Figure 1-1. S3C8454 Block Diagram 1-3 PRODUCT OVERVIEW KS88C4504/P4504 PIN ASSIGNMENT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 CS1/P4.5 CS0/P4.4 VDD1 VSS1 XOUT XIN EA P4.3 P4.2 RESET P4.1 P4.0 PWM1/P3.7 PWM0/P3.6 TDOUT/P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 KS88C4504 80-QFP (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK/ P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT Figure 1-2. S3C8454 Pin Assignments 1-4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D7 D6 D5 D4 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 S3C8454/P8454 PRODUCT OVERVIEW PIN ASSIGNMENTS (Continued) D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 CS1/P4.5 CS0/P4.4 VDD1 VSS1 XOUT XIN EA P4.3 P4.2 RESET P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 KS88C4504 80-TQFP (Top View) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK/ P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT TDOUT/P3.5 PWM0/P3.6 PWM1/P3.7 P4.0 Figure 1-3. S3C8454 Pin Assignments 1-5 PRODUCT OVERVIEW KS88C4504/P4504 PIN DESCRIPTIONS Table 1-1. S3C8454/P8454 Pin Descriptions Pin Name Pin Type Pin Description Circuit Type Pin Number Share Pins P0.0–P0.7 I/O Bit programmable port; input or output mode selected by software; normal input or push-pull output with software assignable pull-up (P0.0–P0.3) or pull-down (P0.4–P0.7). Alternately, P0.4–P0.7 can be use as a ADC input port with 8-bit resolution. 2, 3 56–54, 51, 49–46 ADC0– ADC3 P1.0–P1.7 I/O Bit programmable port; input or output mode selected by software; normal input or push-pull output with software assignable pull-up. P1.5–P1.7 can be used as a synchronous SIO port P1.5/SI P1.6/SO P1.7/SCK 3 45–38 SI, SO, SCK P2.0–P2.7 I/O General I/O port with normal input or push-pull output with software; assignable pull-up. Bit programmable. Alternately, P2.0–P2.7 can be used as inputs for external interrupts, INT0–INT7 (with noise filter and interrupt control). INT0/INT1 is level interrupts. 4 37–30 INT0– INT7 P3.0–P3.7 I/O General I/O port with bit programmable pins. Normal input or push-pull output with software assignable pull-up. Input or output mode is selectable by software. Respectively, each pin can serve as (with noise filters): P3.0/timer D clock input (TDCK) P3.1/timer C clock input (TCCK) P3.2/timer D capture input (TDCAP) P3.3/timer C capture input (TCCAP) P3.4/timer C out (TCOUT)/PWM out (TCPWM) P3.5/timer D out (TDOUT)/PWM out (TDPWM) P3.6/PWM0 output port P3.7/PWM1 output port 3, 5 29–22 TDCK TCCK TDCAP TCCAP TDOUT/ TDPWM TCOUT/ TCPWM PWM0 PWM1 P4.0–P4.7 I/O General I/O port with bit programmable pins. Normal input or push-pull output with software assignable pull-up. Input or output mode is selectable by software. P4.0–P4.7 can alternately be used as inputs for embedded chip selection output. P4.4/CS0 P4.5/CS1 P4.6/CS2 P4.7/CS3 3, 5 21, 20, 18, 17, 11–8 CS0–CS3 1-6 S3C8454/P8454 PRODUCT OVERVIEW Table 1-1. S3C8454/P8454 Pin Descriptions (Continued) Pin Name Pin Type Pin Description Circuit Type QFP Pin Number Share Pins I/O General I/O port with bit programmable pins. Normal input or push-pull, output mode. Alternately It can use as external interface control signal P5.0/WAIT signal 5 7 WAIT ADC0–ADC3 I Analog input pins for A/D converter module. Alternatively used as general-purpose I/O 2 49–46 P0.4–P0.7 AVREF – A/D converter reference voltage AVSS is connected to ground internally 50 – PWM0, PWM1 O Pulse width modulation output pins 5 23,22 P3.6, P3.7 INT0–INT7 I External interrupt input pins 4 37–30 P2.0–P2.7 TCCK, TDCK I External clock input for timer C and timer D 3 28,29 P3.1/P3.0 TCCAP,TDCAP I Timer C/ timer D capture input 3 26,27 P3.3/P3.2 WAIT I Input pin for the slow memory timing signal from the external interface 5 7 P5.0 RESET I System reset pin (pull-up resistor: 240 kΩ) 1 19 – EA I 5V: ROMless operating 0V: internal 4 K and external 60 K addressing mode – 16 – VDD1, VSS1 – Power input pins for CPU operation (internal) and Power input for OTP writing – 12,13 – VDD2, VSS2 – Power input pins for port output (external) – 53, 52 – XIN, XOUT – Main oscillator pins – 15, 14 – P5.0–P5.1 SI, SO, SCK I/O synchronous SIO communication port 3 40,39,38 P1.5/P1.6 P1.7 A0–A15 O Address output for external device 6 65–80 – D0–D7 I/O Data I/O for external device 7 57–64 – PM,DM O External memory selection output – 1, 2 – RD,WR O Memory read/write output – 3, 4 – CS0–CS3 O Embedded chip selection output 5 11–8 P4.4–P4.7 TCOUT,TDOUT O 16-bit timer PWM mode output 5 25, 24 P3.4, P3.5 VLD – Voltage Level Detect Pin – 5 – NOTE: VDD1 must be connected to VDD2 in users application circuit, VSS1 & VSS2 also. 1-7 PRODUCT OVERVIEW KS88C4504/P4504 PIN CIRCUITS Table 1-2. Pin Circuit Assignments for the S3C8454/P8454 Circuit Number Circuit Type 1 Input 2 I/O A/D converter input pins, ADC0–ADC3, P0.4–P0.7 3 I/O Port 0, 1, 3, 4, and 5 4 I/O P2 (INT0–INT7) 5 I/O P3 (TDCK, TCCK, TDCAP, TCCAP, TCOUT, TDOUT, TCPWM, TDPWM, PWM0, PWM1) 6 Output 7 I/O 1-8 S3C8454 Assignments RESET pin A0–A15,PM, DM, RD, WR D0–D7 S3C8454/P8454 PRODUCT OVERVIEW VDD Pull-up Resistor (Typical 240 kΩ) Input Figure 1-4. Pin Circuit Type 1 (RESET RESET) VDD Data I/O Output Disable Vss Normal Input ADC Port Selection ADC In Pull-Down Enable Enable ADC Figure 1-5. Pin Circuit Type 2 (ADC0–ADC3) 1-9 PRODUCT OVERVIEW KS88C4504/P4504 VDD Pull-Up Enable VDD Data I/O Output Disable Normal Input SCK Input Noise Filter Figure 1-6. Pin Circuit Type 3 VDD Pull-Up Resistor Pull-Up Enable VDD Data I/O Output Disable Vss External Interrupt Input Noise Filter Normal Input Figure 1-7. Pin Circuit Type 4 1-10 S3C8454/P8454 PRODUCT OVERVIEW VDD Pull-Up Resistor Pull-Up Enable VDD Selection bits for ports or other function Data I/O Output Disable Vss Input Other Function Figure 1-8. Pin Circuit Type 5 VDD In Out Figure 1-9. Pin Circuit Type 6 1-11 PRODUCT OVERVIEW KS88C4504/P4504 VDD Data I/O Output Disable Normal Input Figure 1-10. Pin Circuit Type 7 1-12 S3C8454/P8454 18 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3C8454 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — I/O capacitance — Oscillation characteristics — Oscillation stabilization time 18-1 ELECTRICAL DATA S3C8454/P8454 Table 18-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply voltage Symbol Conditions VDD Rating Unit – 0.3 to + 6.5 V Input voltage VI All ports (in input mode) – 0.3 to VDD + 0.3 Output voltage VO All ports (in output mode) – 0.3 to VDD + 0.3 V Output current high I OH One I/O pin active – 18 mA All I/O pins active – 60 One I/O pin active + 30 Total pin current for port + 100 Output current low Operating temperature Storage temperature 18-2 I OL mA TA – 40 to +85 °C TSTG – 65 to +150 °C S3C8454/P8454 ELECTRICAL DATA Table 18-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Operating voltage Input high voltage Input low voltage Output high voltage Output low voltage Input high leakage current Input low leakage current Symbol VDD Conditions Min Typ Max Unit f OSC = 25 MHz (instruction clock = 6.25 MHz) 4.5 – 5.5 V f OSC = 12 MHz (instruction clock = 3 MHz) 2.7 – 5.5 – VDD V – 0.2 VDD V VIH1 All input pins except VIH2, VIH3 0.51 VDD VIH2 XIN VDD – 0.5 VIH3 Test, RESET VIL1 All input pins except VIL2, VIL3 VIL2 XIN VIL3 Test, RESET 0.2VDD VOH VDD= 5 V IOH = – 1 mA VDD – 1.0 – – IOH = – 100 uA VDD – 0.5 – – 0.8VDD – 0.4 – VOL1 VDD = 5 V IOL = 2 mA All output pins except port 2 – – 0.4 VOL2 VDD = 5 V IOL = 15 mA, port 2 – 0.5 1.0 ILIH1 VIN = VDD All input pins except XIN – – 3 ILIH2 VIN = VDD XIN ILIL1 VIN = 0 V All input pins except XIN and V V µA 20 – – –3 RESET ILIL2 VIN = 0 V, – 20 XIN, RESET Output high leakage current ILOH VOUT = VDD All I/O pins and output pins – – 5 Output low leakage current ILOL VOUT = 0 V All I/O pins and output pins – –0 –5 Pull-up and pull-down resistor RL1 VIN = 0 V; VDD = 5 V ± 10% 30 46 80 VIN = 0 V; VDD = 5 V ± 10% 120 240 320 kΩ Ports 0-5, TA = 25 °C RL2 TA = 25 °C, RESET only 18-3 ELECTRICAL DATA S3C8454/P8454 Table 18-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Supply current (note) Symbol IDD1 IDD2 IDD3 Conditions Min Typ Max Unit VDD = 5 V ± 10 % 20 MHz oscillation 20 40 mA VDD = 2.7 V 12 MHz oscillation 7 14 Idle mode; VDD = 5 V ± 10 % 20 MHz oscillation 8 16 Idle mode; VDD = 2.7 V 12 MHz oscillation 3 6 110 220 Stop mode; VDD = 5 V ± 10 % µA LVD enable, TA = 25 °C NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. Table 18-3. A.C. Electrical Characteristics (TA = -40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width (P2.0–P2.7) tINTH, tINTL VDD = 5 V 180 – – nS RESET input low width tRSL VDD = 5 V 1000 – – nS NOTES: 1. The unit tCPU means one CPU clock period. 2. The oscillator frequency is the same as the CPU clock frequency. tINTL tINTH 0.8 VDD 0.2 VDD Figure 18-1. Input Timing for External Interrupts (Ports 2) 18-4 S3C8454/P8454 ELECTRICAL DATA tRSL RESET 0.2 VDD Figure 18-2. Input Timing for RESET Table 18-4. Input/Output Capacitance (TA = – 40 °C to + 85 °C, VDD = 0 V) Parameter Symbol Input capacitance CIN Output capacitance Conditions f = 1 MHz; unmeasured pins are connected to VSS Min Typ Max Unit – – 10 pF COUT I/O capacitance CIO Table 18-5. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Conditions Stop mode, VDDDR = 2.0 V Min Typ Max Unit 2 – 5.5 V – – 50 µA NOTES: 1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. 2. Supply current does not include drawn through internal pull–up resistors and external output current loads. 18-5 ELECTRICAL DATA S3C8454/P8454 Oscillation Stabilization Time Reset Occurs ~ ~ Normal Operating Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction RESET 0.2 VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. tWAIT Figure 18-3. Stop Mode Release Timing Initiated by RESET 18-6 S3C8454/P8454 ELECTRICAL DATA Table 18-6. A/D Converter Electrical Characteristics (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Resolution Total accuracy VDD = 5 V Min Typ Max Unit – 8 – bit – – ±2 LSB Integral linearity error ILE Conversion time = 5 us – ±1 Integral linearity error DLE AVREF = 5 V – ±1 Offset error of top EOT AVSS = 0 V ±1 ±2 Offset error of bottom EOB ± 0.5 ±2 tCON 17 – 170 µs Analog input voltage VIAN AVss – AVREF V Analog input impedance RAN – 2 1000 – MΩ Analog reference voltage AVREF – 2.5 – VDD V Analog ground AVSS – VSS – VSS+ 0.3 V Analog input current IADIN AVREF = VDD = 5 V – – 10 uA Analog block IADC AVREF = VDD = 5 V 1 3 mA AVREF = VDD = 3 V 0.5 1.5 mA AVREF = VDD = 5 V When power down mode 100 500 nA Conversion time current (2) (1) NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion. 18-7 ELECTRICAL DATA S3C8454/P8454 VDD Reference Voltage Input R AVREF 10 pF + - C 103 VDD Analog Input Voltage ADC0-ADC3 S3C8454 C 101 VSS NOTE: The symbol 'R' signifies an offset resistor with a value of from 50 to 100. If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs. Figure 18-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy 18-8 S3C8454/P8454 ELECTRICAL DATA Table 18-7. Synchronous SIO Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V, VSS = 0 V, fOSC = 10 MHz oscillator) Parameter Symbol Conditions Min Typ Max Unit SCK cycle time tCYC – 200 – – nS Serial clock high width tSCKH – 60 – – Serial clock low width TSCKL – 60 – – Serial output data delay time TOD – – – 50 Serial input data set up time TID – 40 – – Serial input data hold time TIH – 100 – – tCYC tSCKL tSCKH SCK 0.8 VDD 0.2 VDD tID tIH 0.8 VDD SI Input Data 0.2 VDD tOD SO Output Data Figure 18-5. Serial Data Transfer Timing 18-9 ELECTRICAL DATA S3C8454/P8454 Table 18-8. Main Oscillator Frequency (fOSC1) (TA = – 40 °C + 85 °C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Clock Circuit XIN XOUT C1 Ceramic External clock Test Condition XIN Min Typ Max Unit CPU clock oscillation frequency 4 – 25 MHz CPU clock oscillation frequency 4 – 25 MHz XIN input frequency 4 – 25 MHz Min Typ Max Unit C2 XOUT C1 C2 XIN XOUT Table 18-9. Main Oscillator Clock Stabilization Time (tST1) (TA = -40 °C + 85 °C, VDD = 4.5 V to 5.5 V) Oscillator Test Condition Crystal VDD = 4.5 V to 5.5 V – – 10 ms Ceramic Stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 4 ms External clock XIN input high and low level width (tXH, tXL) 50 – – ns NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore be held at low level until the tST1 time has elapsed. 18-10 S3C8454/P8454 ELECTRICAL DATA 1/fOSC1 tXL tXH XIN VDD - 0.5 V 0.4 V Figure 18-6. Clock Timing Measurement at XIN Table 18-10. Characteristics of Voltage Level Detect circuit (TA = – 40 °C + 85 °C) Parameter Symbol Conditions Min Typ Max Unit VDDVLD – 2.7 – 5.5 V Detect Voltage VVLD – 1.15 1.40 1.51 V Current consumption IVLD VDD = 5.5 V – 100 200 uA Operating Voltage of VLD 18-11 ELECTRICAL DATA S3C8454/P8454 fCPU fOSC B 25 MHz 6.25 MHz 18 MHz 16 MHz 14 MHz 4.5 MHz 4 MHz 3.5 MHz 3 MHz A 12 MHz 1 MHz 4 MHz 1 2 3 2.7 4 5 6 7 4.5 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 18-7. Operating Voltage Range 18-12 S3C8454/P8454 MECHANICAL DATA 19 MECHANICAL DATA OVERVIEW The S3C8454 microcontroller is available in a 80-pin QFP package (80-QFP-1420C) and a 80-pin TQFP package (80-TQFP-1212AN). 23.90 ± 0.30 0-8 20.00 ± 0.20 + 0.10 14.00 ± 0.20 0.10 MAX 80-QFP-1420C 0.80 ± 0.20 17.90 ± 0.30 0.15 - 0.05 #80 #1 0.80 0.35 + 0.10 0.05 MIN 0.15 MAX (0.80) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 19-1. 80-QFP-1420C Package Dimensions 19-1 MECHANICAL DATA S3C8454/P8454 14.00 BSC 0-7 12.00 BSC 12.00 BSC 80-TQFP-1212 0.60 ± 0.15 14.00 BSC 0.09-0.20 #80 #1 0.17-0.27 0.50 0.05-0.15 (1.25) 1.00 ± 0.05 1.20 MAX NOTE: Dimensions are in millimeters. Figure 19-2. 80-TQFP-1212AN Package Dimensions 19-2 S3C8454/P8454 20 S3P8454 OTP S3P8454 OTP OVERVIEW The S3P8454 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8454 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format. S3P8454 is fully compatible with S3C8454, both in function and in pin configuration. As it has simple programming requirements, S3P8454 is ideal for use as an evaluation chip for the S3C8454. 20-1 S3P8454 OTP S3C8454/P8454 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 SDAT/CS1/P4.5 SCLK/CS0/P4.4 VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/EA P4.3 P4.2 RESET/RESET RESET P4.1 P4.0 PWM1/P3.7 PWM0/P3.6 TDOUT/P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3P8454 80-QFP (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT NOTE: The bolds indicates OTP pin name. Figure 20-1. S3P8454 Pin Assignments (80-QFP Package) 20-2 D7 D6 D5 D4 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 S3C8454/P8454 S3P8454 OTP D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 SDAT/CS1/P4.5 SCLK/CS0/P4.4 VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/EA P4.3 P4.2 RESET/RESET RESET P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3P8454 80-TQFP (Top View) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT TDOUT/P3.5 PWM0/P3.6 PWM1/P3.7 P4.0 Figure 20-2. S3P8454 Pin Assignments (80-TQFP Package) 20-3 S3P8454 OTP S3C8454/P8454 Table 20-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P4.5 SDAT 10 I/O Serial data pin (Output when reading, Input when writing) Input and push-pull output port can be assigned. P4.4 SCLK 11 I Serial clock pin (Input only pin) VPP 16 I EPROM cell writing power supply pin (Indicates OTP mode entering) When writing 12.5 V is applied and when reading 5 V is applied (Option). RESET RESET 19 I Chip Initialization VDD1/VSS1 VDD/VSS 12/13 I Logic Power Supply Pin. VDD should be tied to 5 V during programming. EA Table 20-2. Comparison of S3P8454 and S3C8454 Features Characteristic S3P8454 S3C8454 Program Memory 4 Kbyte EPROM 4 Kbytes mask ROM Operating Voltage (VDD) 2.7 V to 5.5 V 2.7 V to 5.5V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5V Pin Configuration 80 QFP, 80 TQFP 80 QFP, 80 TQFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of S3P8454, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 20-3 below. Table 20-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) REG /MEM Address (A15–A0) R/W 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 20-4 Mode S3C8454/P8454 S3P8454 OTP D.C. ELECTRICAL CHARACTERISTICS Table 20-4. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Operating voltage Input high voltage Input low voltage Output high voltage Output low voltage Input high leakage current Input low leakage current Symbol VDD Conditions Min Typ Max Unit f OSC = 25 MHz (instruction clock = 6.25 MHz) 4.5 – 5.5 V f OSC = 12 MHz (instruction clock = 3 MHz) 2.7 – 5.5 – VDD V – 0.2 VDD V VIH1 All input pins except VIH2, VIH3 0.51 VDD VIH2 XIN VDD – 0.5 VIH3 Test, RESET VIL1 All input pins except VIL2, VIL3 VIL2 XIN VIL3 Test, RESET 0.2VDD VOH VDD= 5 V IOH = – 1 mA VDD – 1.0 – – IOH = – 100 uA VDD – 0.5 – – 0.8VDD – 0.4 – VOL1 VDD = 5 V, IOL = 2 mA All output pins except port 2 – – 0.4 VOL2 VDD = 5 V, IOL = 15 mA, port 2 – 0.5 1.0 ILIH1 VIN = VDD All input pins except XIN – – 3 ILIH2 VIN = VDD, XIN ILIL1 VIN = 0 V All input pins except XIN and V V µA 20 – – –3 RESET ILIL2 VIN = 0 V, XIN, RESET Output high leakage current ILOH VOUT = VDD All I/O pins and output pins – – 5 Output low leakage current ILOL VOUT = 0 V All I/O pins and output pins – –0 –5 Pull-up and pull-down resistor RL1 VIN = 0 V; VDD = 5 V ± 10% 30 46 80 VIN = 0 V; VDD = 5 V ± 10% 120 240 320 – 20 kΩ Ports 0-5, TA = 25 °C RL2 TA = 25 °C, RESET only 20-5 S3P8454 OTP S3C8454/P8454 Table 20-4. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Symbol Output high leakage current ILOH Output low leakage current ILOL Pull-up and pulldown resistor RL1 Conditions Min Typ Max Unit VOUT = VDD All I/O pins and output pins – – 5 µA VOUT = 0 V All I/O pins and output pins – –0 –5 VIN = 0 V; VDD = 5 V ± 10 % 30 46 80 VIN = 0 V; VDD = 5 V ± 10 % 120 240 320 – 20 40 VDD = 2.7 V 12 MHz oscillation 7 14 Idle mode; VDD = 5 V ± 10 % 20 MHz oscillation 8 16 Idle mode; VDD = 2.7 V 12 MHz oscillation 3 6 110 220 kΩ Ports 0-5, TA = 25 °C RL2 TA = 25 °C, RESET only Supply current (note) IDD1 IDD2 IDD3 VDD = 5 V ± 10 % 20 MHz oscillation Stop mode; VDD = 5 V ± 10%, LVD enable mA µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. 20-6