SAMSUNG S3P9434

S3C9432/C9434/P9434
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9432/C9434 MICROCONTROLLER
The S3C9432/C9434 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM87Ri CPU core. The S3C9432/C9434 is a versatile microcontroller, with its A/D
converter, timer, PWM, and SIO it can be used in a wide range of general purpose applications.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9432/C9434 have 2K-bytes or 4Kbytes of program memory on-chip (ROM) and 112-bytes of general purpose register area RAM.
Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
— Three configurable I/O ports (13 pins)
— Five interrupt sources with one vector and one interrupt level
— One 8-bit timer/counter with time interval mode
— Analog to digital converter with five input channels and 10-bit resolution
— One synchronous SIO module
— One 12-bit PWM output
The S3C9432/C9434 microcontroller is ideal for use in a wide range of electronic applications requiring simple
timer/counter, PWM, ADC, and SIO. S3C9432/C9434 is available in a 20/18/16-pin DIP and a 20-pin SOP
package.
OTP
The S3P9434 is an OTP (One Time Programmable) version of the S3C9432/C9434 microcontroller. The
S3P9434 has on-chip 4K-byte one-time-programmable EPROM instead of masked ROM. The S3P9434 is fully
compatible with the S3C9432/C9434, in function, in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9432/C9434/P9434
FEATURES
CPU
Timer/Counters
•
•
One 8-bit basic timer for watchdog function
•
One 8-bit timer/counter for the time interval
mode
SAM87RI CPU core
Memory
•
2/4K-byte internal program memory (ROM)
•
112-byte general purpose register area (RAM)
Instruction Set
•
41 instructions
•
The SAM87RI core provides all the SAM87 core
instruction except the word-oriented instruction,
multiplication, division, and some one-byte
instruction.
Instruction Execution Time
•
600 ns at 10 MHz fOSC (minimum cycles)
•
375 ns at 16 MHz fOSC (minimum cycles)
Interrupts
•
5 interrupt sources with one vector and one
level interrupt structure
PWM Module
•
12-bit PWM 1-ch (Max: 250 kHz)
•
6-bit base + 6-bit extension frame
A/D Converter
•
Five analog input pins
•
10-bit conversion resolution
Buzzer Frequency Range
•
200 Hz to 20 kHz signal can be generated
Oscillation Frequency
•
1 MHz to 16 MHz external crystal oscillator
•
Maximum 16 MHz CPU clock
•
4 MHz RC oscillator
General I/O
Operating Temperature Range
•
Two I/O ports (Toatal 13 pins)
•
•
One output only port (port 2)
•
Bit programmable ports
Serial I/O
•
One synchronius serial I/O module
•
Selectable transmit and receive rates
Built-in reset Circuit (LVD)
•
1-2
Low voltage detector for safe reset
- 40°C to + 85°C
Operating Voltage Range
•
3.0 V to 5.5 V
OTP Interface Protocol Spec
•
Serial OTP
Package Types
•
20-pin DIP-300
•
20-pin SOP-375
•
18-pin DIP-300
•
16-pin DIP-300
S3C9432/C9434/P9434
PRODUCT OVERVIEW
BLOCK DIAGRAM
Basic
Timer
P0.0-P0.3
BUZ, PWM, INT0, INT1
P1.0-P1.4
ADC0-ADC4
SCK, SO, SI, CLO
Port 0
Port 1
XIN
OSC
XOUT
I/O Port and
Interrupt Control
P0.2/T0CK
Timer 0
P2.0/SCK
Port 2
P2.1/SO
P2.2
P2.3
P0.0/BUZ
BUZ
SAM87RI CPU
ADC0-ADC4
ADC
P0.1/PWM
PWM
2-KB ROM
4-KB ROM
SIO
SCK (P1.3 or P2.0)
SO (P1.2 or P2.1)
SI (P1.1)
112-Byte
Register File
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9432/C9434/P9434
PIN ASSIGNMENTS
VSS
1
20
VDD
XIN
2
19
P0.3/INT1 (SCL)
XOUT
3
18
P1.0/ADC0 (SDA)
TEST (VPP)
4
17
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
16
P1.2/ADC2/SO
P0.1/PWM
6
15
P1.3/ADC3/SCK
RESET
7
14
P1.4/ADC4/CL0
P0.0/BUZ
8
13
AVREF
P2.0/SCK
9
12
P2.1/SO
10
11
P2.3
P2.2
S3C9432/C9434
20-DIP
(Top View)
Figure 1-2. Pin Assignment Diagram (20-Pin DIP Package)
1-4
S3C9432/C9434/P9434
PRODUCT OVERVIEW
VSS
1
20
VDD
XIN
2
19
P0.3/INT1
XOUT
3
18
P1.0/ADC0
TEST
4
17
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
16
P1.2/ADC2/SO
P0.1/PWM
6
15
P1.3/ADC3/SCK
RESET
7
14
P1.4/ADC4/CLO
P0.0/BUZ
8
13
AVREF
P2.0/SCK
9
12
P2.1/SO
10
11
P2.3
P2.2
S3C9432/C9434
20-SOP
(Top View)
Figure 1-3. Pin Assignment Diagram (20-Pin SOP Package)
1-5
PRODUCT OVERVIEW
S3C9432/C9434/P9434
VSS
1
18
VDD
XIN
2
17
P0.3/INT1
XOUT
3
16
P1.0/ADC0
TEST
4
15
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
S3C9432/C9434
18-DIP
14
P1.2/ADC2/SO
P0.1/PWM
6
(Top View)
13
P1.3/ADC3/SCK
RESET
7
12
P1.4/ADC4/CL0
P0.0/BUZ
8
11
AVREF
P2.0/SCK
9
10
P2.1/SO
Figure 1-4. Pin Assignment Diagram (18-Pin DIP Package)
VSS
1
16
VDD
XIN
2
15
P0.3/INT1
XOUT
3
14
P1.0/ADC0
TEST
4
13
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
12
P1.2/ADC2/SO
P0.1/PWM
6
11
P1.3/ADC3/SCK
RESET
7
10
P1.4/ADC4/CLO
P0.0/BUZ
8
9
S3C9432/C9434
16-DIP
(Top View)
AVREF
Figure 1-5. Pin Assignment Diagram (16-Pin DIP Package)
1-6
S3C9432/C9434/P9434
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C9432/C9434 Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Bit-programmable I/O port for Schmitt trigger
input or push-pull, open-drain output. Pull-up
resistors are assignable by software. Port 0 pins
can also be used as alternative function.
Circuit
Type
Share
Pins
E
BUZ
PWM
INT0/T0CK
INT1
ADC0-ADC4
SI
SO
SCK
CLO
SCK
SO
P0.0-P0.3
I/O
P1.0-P1.4
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull, open-drain output. Pull-up
resistors are assignable by software. Port 1 pins
can also be used as alternative function.
E-1
P2.0-P2.3
O
E-2
XIN, XOUT
–
Push-pull or open-drain output port. Pull up
resistors are assignable by software. Port 2.0-2.1
pins can also be used as alternative function.
Crystal/ceramic, or RC oscillator signal for system
clock.
–
–
RESET
TEST
I
B
–
I
System RESET signal input pin.
Test signal input pin (for factory use only: must be
connected to VSS)
–
–
VDD, VSS
–
Voltage input pin and ground
–
–
AVREF
–
A/D converter reference voltage input and ground
–
–
E-1
E-2
E-1
E-2
E-1
E-1
E
P1.3 or
P2.0
P1.2 or
P2.1
P1.1
P1.4
P0.0
E
E
P0.1
P0.2
P0.3
P0.2
P1.0-P1.4
AVSS
Bonded to VSS internally
SCK
I/O
Serial interface clock I/O
SO
O
Serial data output
SI
CLO
BUZ
I
O
O
PWM
INT0-INT1
O
I
Serial data input
System clock output port
200 Hz- 20 kHz frequency output for buzzer
sound
12-bit PWM output
External interrupt input port
T0CK
ADC0-ADC4
I
I
Timer 0 external clock input
A/D converter input
E
E-1
1-7
PRODUCT OVERVIEW
S3C9432/C9434/P9434
PIN CIRCUITS
VDD
VDD
P-Channel
P-Channel
Data
In
Out
N-Channel
Figure 1-6. Pin Circuit Type A
N-Channel
Output
DIsable
Figure 1-8. Pin Circuit Type C
VDD
VDD
Pull-Up
Resistor
In
Pull-up
Enable
Data
Output
DIsable
P-Channel
Circuit
Type C
I/O
Data
Figure 1-7. Pin Circuit Type B
1-8
Figure 1-9. Pin Circuit Type D
S3C9432/C9434/P9434
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Open-Drain
VDD
VDD
Open-Drain
VDD
Pull-up
Enable
P-CH
Output
Data
P-CH
I/O
N-CH
Output
Data
Output
DIsable
Pull-up
Resistor
Pull-up
Enable
I/O
N-CH
Output
DIsable
Input
Figure 1-12. Pin Circuit Type E-2
Figure 1-10. Pin Circuit Type E
VDD
Open-Drain
VDD
P-CH
Output
Data
Pull-up
Resistor
Pull-up
Enable
I/O
N-CH
Output
DIsable
Digital
Input
Analog
Input
Figure 1-11. Pin Circuit Type E-1
1-9
S3C9432/C9434/P9434
14
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9432/C9434 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— Input Timing Measurement Points
— Oscillator characteristics
— Oscillation stabilization time
— Operating Voltage Range
— Schmitt trigger input characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a RESET
— A/D converter electrical characteristics
— LVD circuit characteristics
— LVD reset Timing
— Serial I/O timing characteristics
— Serial data transfer timing
14-1
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
–
Rating
Unit
- 0.3 to + 6.5
V
Input voltage
VI
All input ports
- 0.3 to VDD + 0.3
V
Output voltage
VO
All output ports
- 0.3 to VDD + 0.3
V
Output current high
I OH
One I/O pin active
- 25
All I/O pins active
- 80
One I/O pin active
+ 30
All I/O pins active
+ 150
Output current low
Operating temperature
Storage temperature
I OL
mA
mA
TA
–
- 40 to + 85
°C
TSTG
–
- 65 to + 150
°C
Table 14-2. DC Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Typ
Max
Unit
0.8 VDD
–
VDD
V
–
0.2 VDD
V
VIH1
Ports 0, 1, and
VIH2
XIN and XOUT
VIL1
Ports 0, 1, and
VIL2
XIN and XOUT
Output high
voltage
VOH
IOH = - 10 mA
ports 0, 1, 2
VDD= 4.5 to 5.5 V
VDD - 1.5
VDD - 0.4
–
V
Output low
voltage
VOL
IOL = 25 mA
port 0, 1, and 2
VDD= 4.5 to 5.5 V
–
0.4
2.0
V
Input high
voltage
Input low
voltage
14-2
RESET
RESET
VDD= 3.0 to 5.5 V
Min
VDD - 0.1
VDD= 3.0 to 5.5 V
–
0.1
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-2. DC Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Input high leakage
current
ILIH1
All inputs except ILIH2 VIN = VDD
ILIH2
XIN, XOUT
VIN = VDD
ILIL1
All inputs except
ILIL2 and RESET
VIN = 0 V
ILIL2
XIN, XOUT
VIN = 0 V
Output high
leakage current
ILOH
All outputs
VOUT = VDD
–
–
2
uA
Output low
leakage current
ILOL
All outputs
VOUT = 0 V
–
–
-2
uA
Pull-up resistors
RP
VIN = 0 V
Ports 0-2
VDD = 5 V
30
47
70
kΩ
RESET
VDD = 5 V
100
200
350
Run mode
16 MHz CPU clock
VDD = 5V ± 10%
–
11
20
8 MHz CPU clock
VDD = 3.3 V
3
6
Idle mode
16 MHz CPU clock
VDD = 5V ± 10%
5
8
8 MHz CPU clock
VDD = 3.3 V
0.7
2.5
Stop mode
VDD = 5V ± 10%
65
100
45
80
Input low leakage
current
Supply current
IDD1
IDD2
IDD3
Conditions
VDD = 3.3 V
Min
Typ
Max
Unit
–
–
1
uA
20
–
–
-1
uA
-20
–
–
mA
uA
NOTE: D.C electrical values for supply current (IDD, to IDD3) do not include current drawn through internal pull-up
resisters, output port drive current and ADC module.
14-3
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-3. AC Electrical Characteristics
(TA = –40°C to + 85°C, VDD = 3.0 V to 5.5 V)
Parameter
Interrupt input
high, low width
RESET input
low width
Symbol
Conditions
Min
Typ
Max
Unit
tINTH,
tINTL
INT0, INT1
VDD = 5V ± 10%
–
200
–
ns
tRSL
Input
VDD = 5V ± 10%
–
1
–
us
tINTL
tINTH
tRSL
0.8 VDD
0.2 VDD
Figure 14-1. Input Timing Measurement Points
14-4
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-4. Oscillator Characteristics
(TA = - 40°C to + 85°C)
Oscillator
Main crystal or
ceramic
Clock Circuit
XIN
XOUT
C1
Test Condition
Min
Typ
Max
Unit
VDD = 4.5 to 5.5 V
VDD = 3.0 to 4.5 V
1
1
–
–
16
8
MHz
C2
External clock
XIN
XOUT
VDD = 4.5 to 5.5 V
VDD = 3.0 to 4.5 V
1
1
–
–
16
8
RC oscillator
XIN
XOUT
VDD = 5 V, R = 10 KΩ
VDD = 3 V, R = 22 KΩ
–
–
4
2
–
–
R
Table 14-5. Oscillation Stabilization Time
(TA = - 40°C to + 85°C, VDD = 3.0 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
ms
Main crystal
f OSC > 1.0 MHz
–
–
20
Main ceramic
Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage range.
–
–
10
External clock
(main system)
XIN input high and low width (tXH, tXL)
25
–
500
ns
Oscillator
stabilization
tWAIT when released by a reset (1)
–
216/fOSC
–
ms
wait time
tWAIT when released by an interrupt (2)
–
–
–
NOTES:
1. fOSC is the oscillator frequency.
2.
The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the
settings in the basic timer control register, BTCON.
14-5
ELECTRICAL DATA
S3C9432/C9434/P9434
CPU Clock
16MHz
8MHz
4MHz
3MHz
2MHz
1MHz
1
2 2.7 3
4
5 5.5 6
7
Supply Voltage (V)
Figure 14-2. Operating Voltage Range
VOUT
VDD
A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
A
B
0.3 VDD
C
D
VIN
0.7 VDD
Figure 14-3. Schmitt Trigger Input Characteristics Diagram
14-6
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-6. Data Retention Supply Voltage in Stop Mode
(TA = – 40°C to + 85°C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Data retention
supply voltage
VDDDR
Stop mode
Data retention
supply current
IDDDR
Stop mode; VDDDR = 2.0 V
Min
Typ
Max
Unit
2.0
–
5.5
V
–
0.1
5
uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Reset
Occurs
~
~
Stop Mode
Oscillation
Stabilization Time
Normal
Operating
Mode
Data Retention Mode
~
~
VDD
Execution Of
Stop Instrction
RESET
VDDDR
0.8 VDD
0.2 VDD
tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fosc
Figure 14-4. Stop Mode Release Timing When Initiated by a RESET
14-7
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-7. A/D Converter Electrical Characteristics
(TA = - 40°C to + 85°C, VDD = 3.0 V to 5.5 V, VSS = 0 V)
Parameter
Total accuracy
Symbol
–
Test Conditions
VDD = 5.12 V
Min
Typ
Max
Unit
–
–
±3
LSB
CPU clock = 10 MHz
AVREF = 5.12 V
AVSS = 0 V
Integral linearity
error
ILE
–
–
–
±2
Differential
linearity error
DLE
–
–
–
±1
Offset error of
top
EOT
–
–
±1
±3
Offset error of
bottom
EOB
–
–
±1
±2
Conversion
time (1)
tCON
–
50x4/ fOSC
–
µs
Analog input
voltage
VIAN
–
AVSS
–
AVREF
V
Analog input
impedance
RAN
–
2
–
–
MΩ
ADC reference
voltage
AVREF
–
3.0
–
VDD
V
ADC reference
ground
AVSS
–
VSS
–
VSS + 0.3
V
Analog input
current
IADIN
AVREF = VDD = 5 V
–
–
10
µA
Analog block
current (2)
IADC
AVREF = VDD = 5 V
conversion time = 20 µs
1
3
mA
AVREF = VDD = 3 V
conversion time = 20 µs
0.5
1.5
mA
AVREF = VDD = 5 V
when power down mode
100
500
nA
f OSC = 10 MHz
NOTES:
1. “Conversion time” is the time required from the moment a conversion operation starts until it ends.
2. IADC is operating current during A/D conversion.
14-8
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-8. LVD Circuit Characteristics
(TA = - 40°C to + 85°C, VDD = 3.0 V to 5.5V)
Parameter
Symbol
Conditions
Min
Power-on reset
voltage high
VDDH
3.0
Power-on reset
voltage low
VDDL
0
Power supply
voltage rise time
tr
10
Power supply
voltage off time
toff
0.5
Power-on reset
circuit
IDDPR
consumption
current
Typ
2.6
Max
Unit
5.5
V
3.0
V
(note)
us
sec
VDD = 5 V ± 10 %
65
100
uA
VDD = 3 V
45
80
uA
NOTE: Oscillation stabilization time = 216/fx (= 6.55 ms at fx = 10 MHz)
VDD
VDDH
VDDL
tOFF
tR
Figure 14-5. LVD Reset Timing
14-9
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-9. Serial I/O Timing Characteristics
(TA = – 40°C to + 85°C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
SCK Cycle Time
tCKY
SCK High, Low Width
tKH, tKL
SI Setup Time to SCK Low
SI Hold Time to SCK High
Output Delay for SCK to SO
tSIK
tKSI
tKSO
Conditions
Min
Typ
Max
Unit
External SCK source
1000
–
–
ns
Internal SCK source
1000
External SCK source
500
–
–
Internal SCK source
tKCY/2 – 50
External SCK source
250
–
–
Internal SCK source
250
External SCK source
400
–
–
Internal SCK source
400
External SCK source
–
–
300
Internal SCK source
250
NOTE: "SCK" means serial I/O clock frequency, "SI" means serial data input, and "SO" means serial data output.
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
SI
Input
0.2 VDD
tKSO
SO
Output Data
Figure 14-6. Serial Data Transfer Timing
14-10
IDD1 (mA)
S3C9432/C9434/P9434
ELECTRICAL DATA
11.0
10.5
10.0
9.5
fx = 16 MHz
9.0
8.5
8.0
7.5
7.0
6.5
fx = 10 MHz
6.0
5.5
5.0
fx = 8 MHz
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
2.0
3.0
4.0
5.0
VDD (V)
Figure 14-7. IDD1 vs VDD
14-11
ELECTRICAL DATA
S3C9432/C9434/P9434
IOL (mA)
VDD = 5.5 V
80
75
VDD = 5.0 V
70
65
VDD = 4.5 V
60
55
50
45
40
35
30
25
20
15
10
5
0.0
1.0
2.0
3.0
4.0
5.0
VOL (V)
Figure 14-8. IOL vs VOL
14-12
IOH (mA)
S3C9432/C9434/P9434
ELECTRICAL DATA
-80
-75
-70
-65
-60
VDD = 5.5 V
-55
-50
-45
VDD = 5.0 V
VDD = 4.5 V
-40
-35
-30
-25
-20
-15
-10
-5
0.0
1.0
2.0
3.0
4.0
5.0
VOH (V)
Figure 14-9. IOH vs VOH
14-13
S3C9432/C9434/P9434
15
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The S3C9432/C9434 is available in a 20-pin SDIP package (Samsung: 20-DIP-300A), a 20-pin SOP package
(Samsung: 20-SOP-375), a 18-pin DIP package (Samsung: 18-DIP-300A). Package dimensions are shown in
Figure 15-1, 15-2, and 15-3.
#11
0-15
0.2
5
20-DIP-300A
+0
- 0 .10
.05
7.62
6.40 ± 0.20
#20
0.46 ±
0.10
(1.77)
1.52 ±
0.10
NOTE:
2.54
0.20
26.40 ± 0.20
0.51 MIN
3.25 ±
26.80 MAX
5.08 MAX
#10
3.30 ± 0.30
#1
Dimensions are in millimeters.
Figure 15-1. 20-DIP-300A Package Dimensions
15-1
MECHANICAL DATA
S3C9432/C9434/P9434
0-8
0.203
12.74 ± 0.20
0.10
2.30 ±
13.14 MAX
+ 0.10
- 0.05
1.27
(0.66)
0.40
NOTE:
+ 0.10
- 0.05
0.05 MIN
0.10 MAX
Dimensions are in millimeters.
Figure 15-2. 20-SOP-375 Package Dimensions
15-2
0.20
#10
0.85 ±
#1
9.53
20-SOP-375
0.20
7.50 ±
#11
2.50 MAX
10.30 ± 0.30
#20
S3C9432/C9434/P9434
MECHANICAL DATA
#10
0-15
0.2
5
18-DIP-300A
+0
- 0 .10
.05
7.62
6.40 ± 0.20
#18
0.46 ±
0.10
(1.32)
1.52 ±
0.10
NOTE:
2.54
0.20
22.95 ± 0.20
0.51 MIN
3.25 ±
23.35 MAX
5.08 MAX
#9
3.30 ± 0.30
#1
Dimensions are in millimeters.
Figure 15-3. 18-DIP-300A Package Dimensions
15-3
MECHANICAL DATA
S3C9432/C9434/P9434
#9
#1
#8
0.2
5
6.40
7.62
#16
2.54
5.08
1.50
3.30
(0.81)
3.25
0.46
0.38
19.80
Figure 15-4. 16-DIP-300A Package Dimensions
15-4
S3C9432/C9434/P9434
16
S3P9434 OTP
S3P9434 OTP
OVERVIEW
The S3P9434 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C9432/C9434 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9434 is fully compatible with the S3C9432/C9434, in function, in D.C. electrical characteristics, and in
pin configuration. Because of its simple programming requirements, the S3P9434 is ideal for use as an
evaluation chip for the S3C9432/C9434.
VSS/VSS
1
20
VDD/VDD
XIN
2
19
P0.3/INT1/SCLK
XOUT
3
18
P1.0/ADC0/SDAT
VPP/TEST
4
17
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
16
P1.2/ADC2/SO
P0.1/PWM
6
15
P1.3/ADC3/SCK
RESET /RESET
7
14
P1.4/ADC4/CLO
P0.0/BUZ
8
13
AVREF
P2.0/SCK
9
12
P2.1/SO
10
11
P2.3
P2.2
NOTE:
S3P9434
20-DIP
(Top View)
The bolds indicate an OTP pin name.
Figure 16-1. Pin Assignment Diagram (20-Pin DIP Package)
16-1
S3P9434 OTP
S3C9432/C9434/P9434
VSS/VSS
1
20
VDD/VDD
XIN
2
19
P0.3/INT1/SCLK
XOUT
3
18
P1.0/ADC0/SDAT
VPP/TEST
4
17
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
16
P1.2/ADC2/SO
P0.1/PWM
6
15
P1.3/ADC3/SCK
RESET /RESET
7
14
P1.4/ADC4/CLO
P0.0/BUZ
8
13
AVREF
P2.0/SCK
9
12
P2.1/SO
10
11
P2.3
P2.2
NOTE:
S3P9434
20-SOP
(Top View)
The bolds indicate an OTP pin name.
Figure 16-2. Pin Assignment Diagram (20-Pin SOP Package)
16-2
S3C9432/C9434/P9434
S3P9434 OTP
VSS/VSS
1
18
VDD/VDD
XIN
2
17
P0.3/INT1/SCLK
XOUT
3
16
P1.0/ADC0/SDAT
VPP/TEST
4
15
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
S3C9432/C9434
18-DIP
14
P1.2/ADC2/SO
P0.1/PWM
6
(Top View)
13
P1.3/ADC3/SCK
RESET /RESET
7
12
P1.4/ADC4/CLO
P0.0/BUZ
8
11
AVREF
P2.0/SCK
9
10
P2.1/SO
NOTE:
The bolds indicate an OTP pin name.
Figure 16-3. Pin Assignment Diagram (18-Pin DIP Package)
16-3
S3P9434 OTP
S3C9432/C9434/P9434
VSS/VSS
1
16
VDD/VDD
XIN
2
15
P0.3/INT1/SCLK
XOUT
3
14
P1.0/ADC0/SDAT
VPP/TEST
4
13
P1.1/ADC1/SI
P0.2/T0CK/INT0
5
12
P1.2/ADC2/SO
P0.1/PWM
6
11
P1.3/ADC3/SCK
RESET /RESET
7
10
P1.4/ADC4/CLO
P0.0/BUZ
8
9
NOTE:
S3P9434
16-DIP
(Top View)
AVREF
The bolds indicate an OTP pin name.
Figure 16-4. Pin Assingment Diagram (16-Pin DIP Package)
16-4
S3C9432/C9434/P9434
S3P9434 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.3
SDAT
18 (20-pin)
16 (18-pin)
I/O
P0.2
SCLK
19 (20-pin)
17 (18-pin)
I
Serial clock pin (input only pin)
TEST
VPP (TEST)
4
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
RESET
7
I
Chip Initialization
VDD/VSS
20 (20-pin), 18 (18-pin)
1 (20-pin), 1 (18-pin)
I
Logic power supply pin.
RESET
VDD/VSS
Serial data pin (output when reading, Input
when writing) Input and push-pull output
port can be assigned
NOTE: ( ) means the SOP OTP pin number.
Table 16-2. Comparison of S3P9434 and S3C9432/C9434 Features
Characteristic
S3P9434
S3C9432/C9434
4 Kbyte EPROM
2K/4K byte mask ROM
Operating Voltage (VDD)
3.0 V to 5.5 V
3.0 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Program Memory
Pin Configuration
20 DIP/20 SOP/18 DIP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P9434, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
VPP
REG/MEM
MEM
(TEST)
5V
ADDRESS
R/W
MODE
(A15-A0)
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-5