SAMSUNG KS88C0716

KS88C0716/P0716
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.
KS88C0716/P0716 MICROCONTROLLERS
KS88C0716/P0716 single-chip 8-bit microcontrollers are based on the powerful SAM87 CPU architecture. The
internal register file is logically expanded to increase the on-chip register space. The KS88C0716 has 16-Kbyte
mask-programmable ROM. The KS88P0716 has 16-Kbyte one-time-programmable EPROM.
Following Samsung's modular design approach, the following peripherals are integrated with the SAM87 core:
— Seven programmable I/O ports (total 56 pins)
— One 8-bit basic timer for oscillation stabilization and watchdog functions
— One synchronous operating mode and three full-duplex asynchronous UART modes
— Two 8-bit timers with interval timer and PWM modes
— Two 16-bit general-purpose timer/counters
OTP
The KS88C0716 microcontroller is also available in OTP (One Time Programmable) version, KS88P0716.
KS88P0716 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM.
The KS88P0716 is comparable to KS88C0716, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS88C0716/P0716
FEATURES
CPU
•
SAM87 CPU core
Memory
•
272-byte general purpose register area
•
16-Kbyte internal program memory
•
ROM-less operating mode
General I/O
•
Four nibble-programmable ports
•
One bit-programmable port
•
Two bit-programmable ports for external
interrupts
Timers
•
External Interface
•
64-Kbyte external data memory area
•
64-Kbyte external program memory area (ROMless mode)
Two 8-bit timers with interval timer and PWM
modes
Timer/Counters
•
Two 16-bit general-purpose timer/counters
Instruction Set
Basic Timer
•
78instructions
•
•
IDLE and STOP instructions for power-down
mode
Instruction Execution Time
•
One 8-bit basic timer (BT) for oscillation
stabilization control and watch dog timer function.
Serial Port
•
500 ns at 12 MHz fCPU (Min.)
One synchronous operating mode and three fullduplex asynchronous UART modes
Operating Temperature Range
Interrupts
•
– 40°C to + 85°C
•
17 interrupt sources
•
17 interrupt vectors
Operating Voltage Range
•
Eight interrupt levels
•
•
Fast interrupt processing
2.7 V to 5.5 V
Package Types
•
1-2
64-pin SDIP, 64-pin QFP
KS88C0716/P0716
PRODUCT OVERVIEW
Table 1-1. Comparison Table
Feature
KS88C0116
KS88C0716
Core
SAM8
SAM87
ROM
16 K bytes
Same
RAM
272 bytes
Same
I/O
54
56 (add two pins)
Port 6
Open drain (9 V drive)
Normal C-MOS output
I/O option
None
Same
Timer
8-bit back-up timer
None
Timer A, B
— 8-bit
— Interval/PWM mode
— Timer A match interrupt
Same
(some differ in interval mode,
see manual)
Timer C, D
— Gate function
— Timer/counter
Same
Watchdog timer
None
Watchdog timer (with BT)
SIO
UART
— 8-bit/9-bit UART
— SIO
Same
Interrupt
External × 12
— P2.4–P2.7, P4.0–P4.7
Same
Internal × 6
— Timer A, C, D, SI, SO, Back-up
Internal × 5
— Timer A, C, D, SI, SO
Power down
Stop/idle
Same
Oscillator
Crystal, ceramic
Same
CPU clock divider
1/2
1/1, 1/2, 1/8, 1/16
Execution time (Min.)
0.6 µs at 20 MHz (fCPU = 10 MHz)
0.5 µs at 12 MHz (fCPU = 12 MHz)
Operating frequency
Max. 20 MHz (fCPU = 10 MHz)
Max. 12 MHz (at 4.5 V) (2)
Max. 4 MHz (at 2.7 V)
Operating voltage
4.5–5.5 V
2.7–5.5 V at 4 MHz
4.5–5.5 V at 12 MHz
OTP/MTP
MTP
OTP
Pin assignment
–
Different
Package
64SDIP/64QFP
Same
Start address
0020h
0100h
P5CON, P6CON
BANK0
BANK1
Interrupt pending bit clear
Write "1"
Write "0"
NOTES:
1. The KS88C0716 can replace the KS88C0116. Their functions are mostly the same, but there are some differences.
Table 1-1 shows the comparison of KS88C0716 and KS88C0116.
1-3
PRODUCT OVERVIEW
2.
KS88C0716/P0716
Operating frequency is maximum CPU clock; the maximum oscillation frequency is 22.1184 MHz.
BLOCK DIAGRAM
P0.0–P0.7
(A8–A15)
P1.0–P1.7
(AD0–AD7)
P2.0–P2.3,
P2.4/INT0–P2.7/INT3
PORT 0
PORT 1
PORT 2
RESET
EA
XIN
XOUT
BASIC
TIMER
TA
TB
SAM87 BUS
MAIN
OSC
PORT 3
P3.0–P3.7
PORT 4
P4.0/INT4 (TCG)
P4.1/INT5 (TDG)
P4.2/INT6–
P4.7/INT11
PORT 5
P5.0–P5.3
P5.4–P5.7
PORT 6
P6.0–P6.7
PORT I/O and
INTERRUPT CONTROL
TIMERS
A and B
SAM87 CPU
TCCK
TDCK
TIMERS
C and D
RxD
TxD
SERIAL
PORT
16-KB ROM
272-BYTE
REGISTER FILE
Figure 1-1. KS88C0716 Block Diagram
1-4
KS88C0716/P0716
PRODUCT OVERVIEW
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
P4.1/INT5/TDG
P4.0/INT4/TCG
VDD1
VSS1
XOUT
XIN
EA
P5.6
P5.7
RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
P3.4/TA
P3.3
P3.2
P3.1/TDCK
P3.0/TCCK
P6.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
KS88C0716
64-SDIP
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
VDD2
VSS2
P2.0/ AS
P2.1/ DS
P2.2/R/ W
P2.3/ DM
P2.4/INT0/ WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
Figure 1-2. KS88C0716 Pin Assignments (64-SDIP)
1-5
PRODUCT OVERVIEW
KS88C0716/P0716
P1.4/AD4
P1.3/AD3
P1.2/AD2
P1.1/AD1
P1.0/AD0
P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
52
53
54
55
56
57
58
59
60
61
62
63
64
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
P4.1/INT5/TDG
P4.0/INT4/TCG
VDD1
VSS1
XOUT
XIN
EA
P5.6
P5.7
RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
KS88C0716
64-QFP
(Top View)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P3.0/TCCK
P3.1/TDCK
P3.2
P3.3
P3.4/TA
Figure 1-3. KS88C0716 Pin Assignments (64-QFP)
1-6
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
VDD2
VSS2
P2.0/ AS
P2.1/ DS
P2.2/R/ W
P2.3/ DM
P2.4/INT0/ WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
KS88C0716/P0716
PRODUCT OVERVIEW
Table 1-2. KS88C0716 Pin Descriptions (64-SDIP)
Pin
Name
Pin
Type
Pin
Description
Circuit
Number
SDIP Pin
Number
Share
Pins
P0.0–P0.7
I/O
I/O port with nibble-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups; also
configurable as external interface address
lines A8-A15.
E
1–7, 64
A8–A15
P1.0–P1.7
I/O
Same general characteristics as port 0; also
configurable as external interface
address/data lines AD0–AD7.
E
56–63
AD0–AD7
P2.0–P2.3
I/O
I/O port with bit-programmable pins; Input
or push-pull output. Lower nibble pins 0–3
are configurable for external interface
signals; upper nibble pins 4–7 are bitprogrammable for external interrupts INT0–
INT3. P2.4 can also be used for external
input.
D-1 (lower
nibble);
40–47
AS, DS,
DM, R/W
P2.4–P2.7
P3.0–P3.7
I/O
I/O port with bit-programmable pins; Input
or push-pull output. Alternate functions
include software-selectable UART transmit
and receive on pins 3.7 and 3.6, timer B
and timer A outputs at pins 3.5 and 3.4, and
timer D and C clock inputs at pins 3.1 and
3.0.
P4.0–P4.7
I/O
I/O port with bit-programmable pins; Input
or push-pull output; software-assignable
pull-ups. Alternate functions include
external interrupt inputs INT4-INT11 (with
interrupt enable and pending control) and
timer C and D gate input at P4.0 and P4.1.
P5.0–P5.7
I/O
I/O port with nibble-programmable pins;
Input or push-pull, open-drain output;
software-assignable pull-ups.
P6.0–P6.7
O
Output port with nibble-programmable pins;
push-pull, open-drain output; softwareassignable pull-ups.
RxD
I/O
TxD
TA, TB
INT0–INT3,
D-1 (upper
nibble; with
noise filter)
WAIT
D-1
24– 31
TCCK,
TDCK, TA,
TB, TxD,
RxD
D
(with noise
filter)
8–15
INT4–
INT11,
TCG, TDG
E
21, 22,
50–55
–
E-8
32–39
–
Bi-directional serial data input pin
–
24
P3.7
I/O
Serial data output pin
–
25
P3.6
I/O
Timer A and B output pins
4
27, 26
P3.4, P3.5
TCCK, TDCK
I/O
Timer C and D external clock input pins
D-1
30, 31
P3.0, P3.1
INT0–INT3
I/O
External interrupts. I/O pin 2.4 (share pin
with INT0) is also configurable as a WAIT
signal input pin for the external interface.
D-1
(with noise
filter)
40–43
P2.4–P2.7
1-7
PRODUCT OVERVIEW
KS88C0716/P0716
Table 1-2. KS88C0716 Pin Descriptions (Continued)
Pin
Name
INT4–INT11
Pin
Type
I/O
Pin
Description
Bit-programmable external interrupt input
pins with interrupt pending and enable
/disable control
Circuit
Number
SDIP Pin
Number
Share
Pins
D
(with noise
filter)
8–15
P4.0–P4.7
XIN, XOUT
–
System clock input and output pins
–
18, 19
–
RESET
I
System reset pin
(internal pull-up: 280 KΩ)
B
23
–
EA
I
External access (EA) pin with three modes:
0 V: Normal operation (internal ROM)
5 V: ROM-less operation (external interface)
–
20
–
VDD2, VSS2
–
Power input pins for port output (external)
–
49, 48
–
VDD1, VSS1
–
Power input pins for CPU (internal)
–
16, 17
–
1-8
KS88C0716/P0716
PRODUCT OVERVIEW
PIN CIRCUIT
VDD
Pull-Up Resistor
(Typical Value: 47 KΩ)
Pull-Up
Enable
VDD
Data
In/Out
Open-Drain
Output Disable
In
Figure 1-4. Pin Circuit Type E (Ports 0, 1, 5)
VDD
Pull-Up Resistor
(Typical Value: 47 KΩ)
Pull-Up
Enable
VDD
Open-Drain
Data
In/Out
VSS
Figure 1-5. Pin Circuit Type E-8 (Ports 6)
1-9
PRODUCT OVERVIEW
KS88C0716/P0716
Select
VDD
Port 2 (Low Byte) Data
External Interface
(AS, DS, R/ W, DM )
M
U
X
Data
In/Out
Output Disable
VSS
In
Figure 1-6. Pin Circuit Type D-1 (P2.0–P2.3)
VDD
Port 2 (High Byte) Data
In/Out
Output Disable
Normal Input or
WAIT Input
External Interrupt
VSS
Noise Filter
Figure 1-7. Pin Circuit Type D-1 (P2.4–P2.7)
1-10
KS88C0716/P0716
PRODUCT OVERVIEW
Select
VDD
Port 3 Data
Control Output
M
U
X
Data
In/Out
Output Disable
VSS
In
Figure 1-8. Pin Circuit Type D-1 (Port 3)
VDD
Pull-Up Resistor
(Typical Value: 47 KΩ)
Pull-Up Enable
VDD
Data
In/Out
Output Disable
Input
External
Interrpt Input
VSS
Noise Filter
Figure 1-9. Pin Circuit Type D (Port 4)
1-11
PRODUCT OVERVIEW
KS88C0716/P0716
VDD
Pull-up Resistor
(Typical 210 K Ω)
RESET
Figure 1-10. Pin Circuit Type B (RESET)
1-12
KS88C0716/P0716
14
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, KS88C0716 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
14-1
ELECTRICAL DATA
KS88C0716/P0716
Table 14-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
Rating
Unit
– 0.3 to + 6.5
V
Input voltage
VI
All ports (in input mode)
– 0.3 to VDD + 0.3
Output voltage
VO
All ports (in output mode)
– 0.3 to VDD + 0.3
V
Output current high
I OH
One I/O pin active
– 10
mA
All I/O pins active
– 60
One I/O pin active
+ 30
Total pin current for ports 0–4
+ 100
Output current low
I OL
Total pin current for ports 5 and 6
Operating
temperature
Storage temperature
14-2
mA
+ 100
TA
– 40 to + 85
°C
TSTG
– 65 to + 150
°C
KS88C0716/P0716
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V)
Parameter
Input high
voltage
Symbol
Conditions
Min
Typ
Max
Unit
0.8 VDD
–
VDD
V
–
0.2 VDD
V
VIH1
All input pins except VIH2
VIH2
XIN
VIL1
All input pins except VIL2
VIL2
XIN
VOH1
VDD= 4.5 V to 5.5 V
IOH = – 4 mA
Port 5, 6
VOH2
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
All output pins except
port 5, 6
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Ports 5 and 6
VOL2
IOL = 2 mA
Ports 0–4
ILIH1
VIN = VDD
All input pins except XIN, XOUT
ILIH2
VIN = VDD, XIN, XOUT
ILIL1
VIN = 0 V
All input pins except XIN, XOUT
ILIL2
VIN = 0 V, XIN, XOUT
Output high
leakage current
ILOH
VOUT = VDD
All output pins
–
–
5
µA
Output low leakage
current
ILOL
VOUT = 0 V
–
–
–5
µA
Pull-up resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 0, 1, 4, 5 and 6
30
47
70
KΩ
RL2
VIN = 0 V; VDD = 5 V
RESET only
110
210
310
Input low voltage
Output high
voltage
Output low voltage
Input high leakage
current
Input low leakage
current
VDD – 0.5
–
0.4
VDD – 1.0
–
–
V
–
–
1.0
V
0.4
–
–
3
µA
20
–
–
–3
µA
– 20
14-3
ELECTRICAL DATA
KS88C0716/P0716
Table 14-2. D.C. Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V)
Parameter
Supply current
Symbol
(1)
IDD1
(2)
IDD2 (2)
IDD3
Conditions
Min
Typ
Max
Unit
–
12
25
mA
4-MHz oscillation
4.5
10
VDD = 3 V ± 10%
12-MHz oscillation
6
15
4-MHz oscillation
2.5
7
3
10
4-MHz oscillation
1.5
4
Idle mode; VDD = 3 V ± 10%
12-MHz oscillation
1.2
3
4-MHz oscillation
0.6
1.5
Stop mode:
VDD = 5 V ± 10%
0.1
3
VDD = 5 V ± 10%
12-MHz oscillation
Idle mode; VDD = 5 V ± 10%
12-MHz oscillation
µA
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. At supply current, the CPU clock frequency is same with oscillation frequency (CPU use non divided clock).
Table 14-3. Data Retention Supply Voltage in Stop Mode
(TA = – 40°C to + 85°C)
Min
Typ
Max
Unit
Data retention
supply voltage
Parameter
Symbol
VDDDR
Stop mode
Conditions
2
–
6
V
Data retention
supply current
IDDDR
Stop mode, VDDDR = 2.0 V
–
–
3
µA
NOTES:
1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped.
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
14-4
ELECTRICAL DATA
∼
∼
KS88C0716/P0716
Idle Mode
(Oscillation
Stabilzation Time)
Stop Mode
Data Retention Mode
∼
∼
VDD
VDDDR
Normal
Operating
Mode
Execution of
Stop Instruction
EXT INT
0.8 V DD
0.2 V DD
NOTE: t WAIT is the same as 16 x BT clock.
t WAIT
Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt
∼
∼
Reset Occurs
Stop Mode
∼
∼
Data Retention Mode
VDD
VDDDR
RESET
Oscillation
Stabilzation
Time
Normal
Operating
Mode
Execution of
Stop Instruction
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC.
t WAIT
Figure 14-2. Stop Mode Release Timing When Initiated by a Reset
14-5
ELECTRICAL DATA
KS88C0716/P0716
Table 14-4. Input/Output Capacitance
(TA = – 40°C to + 85°C, VDD = 0 V)
Parameter
Symbol
Input
capacitance
CIN
Output
capacitance
COUT
I/O capacitance
Conditions
f = 1 MHz; unmeasured
pins are connected to VSS
Min
Typ
Max
Unit
–
–
10
pF
CIO
Table 14-5. A.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V)
Parameter
Interrupt input high,
low width
RESET input low width
Symbol
tINTH,
tINTL
tRSL
Min
Typ
Max
Unit
P2.4–P2.7
Conditions
100
–
–
ns
P4.0–P4.7
100
Input
10
–
–
µs
NOTE: User must keep the larger value with the min value.
t INTL
t INTH
0.8 V DD
0.2 V DD
Figure 14-3. Input Timing for External Interrupts (Port 2 and 4)
14-6
KS88C0716/P0716
ELECTRICAL DATA
t RSL
RESET
0.2 V DD
Figure 14-4. Input Timing for RESET
Table 14-6. Oscillation Characteristics
(TA = – 20°C + 85°C, VDD = 4.5 V to 5.5 V)
Oscillator
Clock Circuit
Crystal
Min
Typ
Max
Unit
Oscillation frequency
Test Condition
1
–
22.1184
MHz
Oscillation frequency
1
–
22.1184
MHz
XIN input frequency
1
–
22.1184
MHz
XIN
C1
C2
XOUT
Ceramic
XIN
C1
C2
XOUT
External clock
XIN
XOUT
14-7
ELECTRICAL DATA
KS88C0716/P0716
Table 14-7. Main Oscillator Clock Stabilization Time (tST1)
(TA = – 20°C + 85°C, VDD = 4.5 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Crystal
VDD = 4.5 V to 5.5 V
–
–
20
ms
Ceramic
Stabilization occurs when VDD is equal to the minimum
oscillator voltage range.
–
–
10
ms
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is released by a RESET signal.
CPU clock
12 MHz
4 MHz
1 MHz
1
2
2.7 3
4
4.5
Figure 14-5. Frequency vs. Voltage
14-8
5
5.5
6
7
VDD
KS88C0716/P0716
15
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The KS88C0716 microcontroller is available in a 64-pin SDIP package (64-SDIP-750) and a 64-pin QFP package
(64-QFP-1420F).
#33
0−15 °
0.25 +0.1
64-SDIP-75 0
– 0.05
19.05
17.00 ± 0.2
#64
1.00 ± 0.1
1.778
5.08MAX
0.45 ± 0.1
(1.34)
3.30 ± 0.3
57.80 ± 0.2
4.10 ± 0.2
58.20 MAX
0.51MIN
#32
#1
NOTE: Dimensions are in millimeters .
Figure 15-1. 64-SDIP-750 Package Dimensions
15-1
MECHA
MECHANICAL DATA
KS88C0716/P0716
13.20 ± 0.3
0-8°
+0.10
0.15 - 0.05
10.00 ± 0.2
13.20 ± 0.3
0.80 ±0.20
10.00 ± 0.2
44-QFP-1010B
0.10 MAX
#44
0.05 MIN
2.05 ± 0.10
#1
0.35
+0.10
- 0.05
(1.00)
0.80
NOTE: Dimensions are in millimeters.
Figure 15-2. 64-QFP-1420F Package Dimensions
15-2
2.30 MAX
KS88C0716/P0716
16
KS88P0716 OTP
KS88P0716 OTP
OVERVIEW
The KS88P0716 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS88C0716 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by
serial data format.
KS88P0716 is fully compatible with KS88C0716, both in function and in pin configuration. As it has simple
programming requirements, KS88P0716 is ideal for use as an evaluation chip for the KS88C0716.
16-1
KS88P0716 OTP
KS88C0716/P0716
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
SDATA /P4.1/INT5/TDG
SCLK /P4.0/INT4/TCG
VDD /V DD1
VSS/VSS1
XOUT
XIN
VPP/EA
P5.6
P5.7
RESET
/RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
P3.4/TA
P3.3
P3.2
P3.1/TDCK
P3.0/TCCK
P6.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
KS88P0716
64-SDIP
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
VDD2
VSS2
P2.0/ AS
P2.1/ DS
P2.2/R/ W
P2.3/ DM
P2.4/INT0/ WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
Figure 16-1. KS88P0716 Pin Assignments (64-SDIP Package)
16-2
KS88C0716/P0716
KS88P0716 OTP
P1.4/AD4
P1.3/AD3
P1.2/AD2
P1.1/AD1
P1.0/AD0
P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
52
53
54
55
56
57
58
59
60
61
62
63
64
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
SDATA /P4.1/INT5/TDG
SCLK /P4.0/INT4/TCG
VDD /V DD1
VSS/V SS1
XOUT
XIN
VPP/EA
P5.6
P5.7
RESET
/ RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
KS88P0716
64-QFP
(Top View)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
VDD2
VSS2
P2.0/ AS
P2.1/ DS
P2.2/R/ W
P2.3/ DM
P2.4/INT0/ WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
32
31
30
29
28
27
26
25
24
23
22
21
20
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P3.0/TCCK
P3.1/TDCK
P3.2
P3.3
P3.4/TA
Figure 16-2. KS88P0716 Pin Assignments (64-QFP Package)
16-3
KS88P0716 OTP
KS88C0716/P0716
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P4.1
SDAT
14 (7)
I/O
P4.0
SCLK
15 (8)
I
Serial Clock Pin (Input Only Pin)
EA
VPP
20 (13)
I
EPROM Cell Writing Power Supply Pin
(Indicates OTP Mode Entering) When writing
12.5V is applied and when reading 5 V is applied
(Option).
RESET
RESET
23 (9)
I
Chip Initialization
VDD1/VSS1
VDD/VSS
16/17
(9/10)
I
Logic Power Supply Pin. VDD should be tied to
5V during programming.
Serial Data Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned.
NOTE: Parentheses indicate 64-QFP pin number.
Table 16-2. Comparison of KS88P0716 and KS88C0716 Features
Characteristic
KS88P0716
KS88C0716
Program Memory
16 K byte EPROM
16 K bytes mask ROM
Operating Voltage (VDD)
2.7 V to 5.5 V
2.7 V to 5.5V
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5V
Pin Configuration
64 SDIP, 64 QFP
64 SDIP, 64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of KS88P0716, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
5V
VPP
(TEST)
REG/
ADDRESS
(A15-A0)
R/W
MEM
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-4
MODE
KS88C0716/P0716
KS88P0716 OTP
D.C. ELECTRICAL CHARACTERISTICS
Table 16-4. D.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V)
Parameter
Input High
Voltage
Input Low Voltage
Output High
Voltage
Output Low
Voltage
Symbol
Conditions
Min
0.8 VDD
Typ
Max
Unit
VDD
V
0.2 VDD
V
VIH1
All input pins except VIH2
VIH2
XIN
VIL1
All input pins except VIL2
VIL2
XIN
VOH1
VDD = 4.5 V to 5.5 V
IOH = – 4 mA
Port 5, 6
VDD – 1.0
VOH2
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
All output pins except port 5, 6
VDD – 1.0
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Ports 5 and 6
1.0
VOL2
IOL = 2 mA
Ports 0 - 4
0.4
VDD – 0.5
0.4
V
V
16-5
KS88P0716 OTP
KS88C0716/P0716
Table 16-4. D.C. Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ILIH1
VIN = VDD
All input pins except XIN, XOUT
–
–
3
uA
ILIH2
VIN = VDD, XIN, XOUT
ILIL1
VIN = 0 V
All input pins except XIN, XOUT
ILIL2
VIN = 0 V, XIN, XOUT
Output High
Leakage Current
ILOH
VOUT = VDD
All output pins
–
–
5
uA
Output Low
Leakage Current
ILOL
VOUT = 0 V
–
–
–5
uA
Pull-Up Resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 0, 1, 4, 5 and 6
30
47
70
KΩ
RL2
VIN = 0 V; VDD = 5 V
RESET only
110
210
310
–
12
25
4-MHz oscillation
4.5
10
VDD = 3 V ± 10%
12-MHz oscillation
6
15
4-MHz oscillation
2.5
7
Idle mode; VDD = 5 V ± 10%
12-MHz oscillation
2.5
6
4-MHz oscillation
1.5
4
Idle mode; VDD = 3 V ± 10%
12-MHz oscillation
1.2
3
4-MHz oscillation
0.6
1.5
Stop mode:
VDD = 5 V ± 10%
0.1
3
Input High
Leakage Current
Input Low
Leakage Current
Supply Current (1)
IDD1 (2)
IDD2
(2)
IDD3
VDD = 5 V ± 10%
12-MHz oscillation
20
–
–
–3
– 20
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. At supply current, the CPU clock frequency is the same as oscillation frequency (CPU use non divided clock).
16-6
uA
mA
uA
KS88C0716/P0716
KS88P0716 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-3. OTP Programming Algorithm
16-7
KS88P0716 OTP
KS88C0716/P0716
NOTES
16-8