TI SN65LVDT9637AD

SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
D
D
D
D
D
D
D
D
D
D
D
D
Meets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard for Signaling
Rates† Up to 400 Mbps
Operates With a Single 3.3 V Supply
–2 V to 4.4 V Common-Mode Input Voltage
Range
Differential Input Thresholds <50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
Integrated 110Ω Line Termination Resistors
Offered With the LVDT Series
Propagation Delay Times 4 ns (typ)
Open-Circuit and Terminated Fail Safe
Assures a High-Level Output With No Input
Bus-Pin ESD Protection Exceeds 15 kV
HBM
Outputs High-Impedance With VCC < 1.5 V
Power Dissipation <400 mW With Four
Receivers Switching at 200 MHz
Available in Small-Outline Package With
1,27 mm Terminal Pitch
Pin-Compatible With the AM26LS32,
MC3486, or uA9637
description
This family of differential line receivers offer
improved performance and features that implement the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS is defined in
the TIA/EIA-644 standard. This improved performance represents the second generation of
receiver products for this standard providing a
better overall solution for the cabled environment.
The next generation family of products is an
extension to TI’s overall product portfolio and is
not necessarily a replacement for older LVDS
receivers.
Improved features include an input commonmode voltage range 2 V wider than the minimum
required by the standard. This will allow longer
cable lengths by tripling the allowable ground
noise tolerance to 3 V between a driver and
receiver.
SN65LVDS32A
SN65LVDT32A
Logic Diagram
(positive logic)
D PACKAGE
(TOP VIEW)
1B
1A
1Y
G
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
G
G
SN65LVDT32A
ONLY (4 Places)
1A
1Y
1B
2A
2Y
2B
3A
3Y
3B
4A
4Y
4B
SN65LVDS3486A
SN65LVDT3486A
Logic Diagram
(positive logic)
D PACKAGE
(TOP VIEW)
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
SN65LVDT3486A
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
ONLY (4 Places)
1A
4B
4A
1B
1,2EN
4Y
2A
3,4EN
3Y
2B
3A
3A
3B
3B
3,4EN
4A
1Y
2Y
3Y
4Y
4B
SN65LVDS9637A
SN65LVDT9637A
D PACKAGE
(TOP VIEW)
VCC
1Y
2Y
GND
1
8
2
7
3
6
4
5
Logic Diagram
(positive logic)
1A
1B
2A
2B
1A
1Y
1B
SN65LVDT9637A
ONLY
2A
2Y
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
description (continued)
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage
hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more
than ±50 mV over the full input common-mode voltage range. See Application Information for more details on
this feature.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates
this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available
for multidrop or other termination circuits.
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 500 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. This prevents noise from being received as valid data under these fault
conditions. This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A, SN65LVDT3486A, SN65LVDS9637A, and
SN65LVDT9637A are characterized for operation from -40°C to 85°C.
Function Tables
SN65LVDS32A and SN65LVDT32A
DIFFERENTIAL INPUT
ENABLES
OUTPUT
A-B
G
G
Y
VID ≥ -70 mV
H
X
X
L
H
H
-100 mV < VID ≤ -70 mV
H
X
X
L
?
?
VID ≤ -100 mV
H
X
X
L
L
L
X
L
H
Z
Open
H
X
X
L
H
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
SN65LVDS3486A and SN65LVDT3486A
DIFFERENTIAL INPUT
ENABLES
A-B
EN
Y
VID ≥ -70 mV
-100 mV < VID ≤ -70 mV
H
H
H
?
VID ≤ -100 mV
X
H
L
L
Z
Open
H
H
OUTPUT
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
Function Tables (Continued)
SN65LVDS9637A and SN65LVDT9637A
DIFFERENTIAL INPUT
OUTPUT
A-B
Y
VID ≥ -70 mV
-100 mV < VID ≤ -70 mV
H
VID ≤ -100 mV
Open
L
H = high level,
?
H
L = low level,
? = indeterminate
equivalent input and output schematic diagrams
VCC
Attenuation
Network
A Input
18 V
Attenuation
Network
Attenuation
Network
VCC
B Input
7V
7V
18 V
LVDT Only 110 Ω
VCC
VCC
300 kΩ
(G Only)
Enable
Inputs
50 Ω
37 Ω
Y Output
7V
7V
300 kΩ
(EN and G Only)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 3 V
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to 6 V
Electrostatic discharge: A, B, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 15 kV, B: 600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 7 kV, B: 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage Temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR‡
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D8
725 mW
5.8 mW/°C
377 mW
D16
950 mW
7.6 mW/°C
494 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
Enables
Low-level input voltage, VIL
Enables
MIN
NOM
MAX
3
3.3
3.6
2
UNIT
V
V
0.8
V
Magnitude of differential input voltage, VID
0.1
3
V
Common-mode input voltage, VIC
–2
4.4
V
Operating free-air temperature, TA
–40
85
°C
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VITH1
VITH2
Positive-going differential input voltage threshold
VITH3
Differential input fail-safe voltage threshold
VID(HYS)
Differential input voltage hysteresis,
VITH1 - VITH2
VOH
VOL
ICC
Negative-going differential input voltage threshold
IOH = –8 mA
IOL = 8 mA
Low-level output voltage
‘32A or ‘3486A
SN65LVDS
Input current (A or B inputs)
SN65LVDT
IID
II(OFF)
IIH
IIL
Differential in
input
ut current
(IIA - IIB)
MAX
50
–50
–70
–100
G or EN at VCC,
Steady-state
1.1
5
Steady-state
Other input open
±20
Other input open
±20
VI =-2 V,
VI = 4.4 V,
Other input open
±40
Other input open
±40
VI = 0 V,
VI =2.4 V,
Other input open
±40
Other input open
±40
VI =-2 V,
VI = 4.4 V,
Other input open
±80
Other input open
±80
SN65LVDT
VID= 0.4 V,
VID= –0.4 V,
High-level input current (enables)
23
VI = 0 V,
VI =2.4 V,
SN65LVDS
Power off input current (A or B inputs)
Power-off
16
No load,
VID= 100 mV,
See Figure 1
8
VIC= –2 V or 4.4 V,
VIC= –2 V or 4.4 V
VIC= –2 V or 4.4 V
VA or VB =0 or 2.4 V,
VCC= 0 V
IOZ
High-impedance output current
CIN
Input capacitance, A or B input to GND
† All typical values are at 25°C and with a 3.3 V supply.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
mA
A
12
µA
µA
µA
3.1
4.5
mA
–3.1
–4.5
mA
±30
µA
VA or VB =–2 V or 4.4 V,
VCC= 0 V
VI = 0.4 sin (4E6πt) + 0.5 V
mV
±2
±50
VIH = 2 V
VIL = 0.8 V
Low-level input current (enables)
mV
V
0.4
No load,
UNIT
mV
2.4
G or EN at GND
‘9637A
II
See Figure 2 and Table 1
TYP†
50
High-level output voltage
S
Supply
l currentt
2 V or 4
4 V,
V See Figure 1
VIB =
=-2
4.4
MIN
5
10
µA
10
µA
±10
µA
pF
5
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
MIN
TYP†
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output
2.5
4
6
ns
Propagation delay time, high-to-low-level output
2.5
4
td1
td2
Delay time, fail-safe deactivate time
tsk(p)
tsk(o)
Pulse skew (|tPHL1 – tPLH1|)
Output skew§
tsk(pp)
tr
Part-to-part skew‡
Output signal rise time
600
ps
tf
tPHZ
Output signal fall time
600
ps
Propagation delay time, high-level-to-high-impedance output
5.5
9
ns
tPLZ
tPZH
Propagation delay time, low-level-to-high-impedance output
4.4
9
ns
3.8
9
ns
PARAMETER
TEST CONDITIONS
Delay time, fail-safe activate time
0.3
CL = 10 pF,
F
See Figure 3
6
ns
6.1
ns
1
µs
200
ps
150
ps
1
See Figure 4
Propagation delay time, high-impedance -to-high-level output
UNIT
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
7
9
ns
† All typical values are at 25°C and with a 3.3 V supply.
‡ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
§ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven together.
PARAMETER MEASUREMENT INFORMATION
IIA
A
VO
Y
VID
B
VIA
(VIA + VIB)/2
VIC
IIB
VO
VIB
Figure 1. Voltage and Current Definitions
2 µs
1 µs
VID
VIA
VIB
CL < 50 pF
VO
VID
0.2 V
VIT–
VIT+
–0.2 V
VO
Figure 2. VITH3 Input Voltage Threshold Test Circuit and Definitions
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum Fail-Safe
Input Threshold Test Voltages
APPLIED VOLTAGES†
RESULTANT INPUTS
VIA (mV)
–2050
VIB (mV)
–1950
VID (mV)
–100
VIC (mV)
–2000
Output
–2035
–1965
–70
–2000
H
4350
4450
–100
4400
L
4365
4435
–70
4400
H
L
† These voltages are applied for a minimum of 1 µs.
VID
VIA
VO
CL = 10 pF
VIB
VIA
1.4 V
VIB
1V
0.4 V
VID
>1 µs
0V
–0.2 V
–0.4 V
tPHL
tPLH
80%
VO
20%
tf
tD1
tD2
VOH
1.4 V
VOL
80%
20%
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, Pulse Repetition Rate (PRR) = 50 Mpps,
Pulsewidth = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
1.2 V
B
500 Ω
A
10 pF
Inputs
±
VO
G
VTEST
G
1,2,EN, or 3,4, EN
NOTE B: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse
repetition rate (PRR) = 50 Mpps, Pulsewidth = 10 ± 0.2 ns . CL includes instrumentation and fixture
capacitance within 0,06 mm of the D.U.T.
2.5 V
VTEST
A
1V
2V
1.4 V
0.8 V
G, 1,2EN,or 3,4EN
2V
1.4 V
0.8 V
tPLZ
G
tPLZ
tPZL
tPZL
Y
VTEST
2.5 V
1.4 V
VOL +0.5 V
VOL
0
1.4 V
A
G, 1,2EN,or 3,4EN
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
tPHZ
tPHZ
tPZH
tPZH
Y
VOH
VOH –0.5 V
1.4 V
0
Figure 4. Enable/Disable Time Test Circuit and Waveforms
8
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SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
VCC = 3.3 V
TA = 25°C
VOH – High-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
5
4
3
2
1
0
0
20
40
60
80
VCC = 3.3 V
TA = 25°C
3
2
1
0
–100
100
IOL – Low-Level Output Current – mA
–80
–20
0
5
4.5
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
3.5
0
50
TA – Free-Air Temperature – °C
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PHL– High-To-Low Propagation Delay Time – ns
t PLH – Low-To-High Propagation Delay Time – ns
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3
–50
–40
Figure 6
Figure 5
4
–60
IOH – High-Level Output Current – mA
100
5
4.5
VCC = 3 V
VCC = 3.3 V
4
VCC = 3.6 V
3.5
3
–50
Figure 7
0
50
TA – Free-Air Temperature – °C
100
Figure 8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
140
I CC – Supply Current – mA
120
VCC = 3.3 V
100
80
VCC = 3.6 V
60
VCC = 3 V
40
20
0
0
150
100
f – Switching Frequency – MHz
Figure 9
10
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• DALLAS, TEXAS 75265
200
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
APPLICATION INFORMATION
0.01 µF
1
VCC
16
0.1 µF
(see Note A)
1B
100 Ω
2
3
VCC 4
5
6
1A
4B
2Y
4Y
G
2A
100 Ω
7
4A
2B
3Y
3A
5V
1N645
(2 places)
15
1Y
G
≈3.6 V
14
100 Ω
(see Note B)
13
12
11
See Note C
10
100 Ω
8
GND
3B
9
NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 10. Operation with 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com
for more information.
For more application guidelines, please see the following documents:
D
D
D
D
D
D
Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
APPLICATION INFORMATION
abstract terminated failsafe
Differential data line receivers commonly have failsafe circuits to prevent the receiver from switching on input
noise. This can occur when the bus driver is turned off or the interconnecting cable is damaged or left floating.
This is generally solved with an external resistor network that applies a steady state bias voltage to the undriven
input pins. In addition to the cost of external components, this has the effect of lowering the input magnitude
thereby reducing the differential noise margin. Current Integrated solutions will not work in wired-OR or common
mode termininated bus applications. The terminated failsafe circuit works over its entire extended common
mode range and will ensure a known state regardless of the common mode signal present.
Output
Buffer
Main Receiver
A
B
+
_
R
Reset
Failsafe
Timer
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 11. Receiver with Terminated Failsafe
12
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SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
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