TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 D D D D D D D Voltage-Controlled Oscillator (VCO) Section: – Ring Oscillator Using Only One External Bias Resistor (RBIAS) – Lock Frequency: 43 MHz to 100 MHz (VDD = 5 V ±5%, TA = – 20°C to 75°C, ×1 Output) 37 MHz to 55 MHz (VDD = 3 V ±5%, TA = – 20°C to 75°C) Phase-Frequency Detector (PFD) Section Includes a High-Speed Edge-Triggered Detector With Internal Charge Pump Independent VCO, PFD Power-Down Mode Thin Small-Outline Package (14 terminal) CMOS Technology Typical Applications: – Frequency Synthesis – Modulation/Demodulation – Fractional Frequency Division CMOS Input Logic Level PW PACKAGE† (TOP VIEW) LOGIC VDD TEST VCO OUT FIN – A FIN – B PFD OUT LOGIC GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCO VDD BIAS VCO IN VCO GND VCO INHIBIT PFD INHIBIT NC † Available in tape and reel only and ordered as the TLC2933PWLE. NC – No internal connection description The TLC2933 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (RBIAS). The high-speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. With the high-speed and stable VCO characteristics, the TLC2933 is well suited for use in high-performance PLL systems. functional block diagram FIN –A FIN –B PFD INHIBIT 4 5 9 VCO IN Phase Frequency Detector 6 BIAS PFD OUT VCO INHIBIT TEST 12 13 10 2 VoltageControlled Oscillator 3 VCO OUT AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (PW) – 20°C to 75°C TLC2933PWLE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 Terminal Functions TERMINAL I/O DESCRIPTION 13 I Bias supply. An external resistor (RBIAS) between VCO VDD and BIAS supplies bias for adjusting the oscillation frequency range. FIN – A 4 I Input reference frequency f(REF IN) is applied to FIN – A. FIN – B 5 I Input for VCO external counter output frequency f(FIN – B). FIN – B is nominally provided from the external counter. LOGIC GND 7 Ground for the internal logic. LOGIC VDD 1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce cross-coupling between supplies. NC 8 No internal connection. PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD OUT is in the high-impedance state, see Table 2. PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD OUT is in the high-impedance state. TEST 2 I Test terminal. TEST connects to ground for normal operation. NAME BIAS NO. VCO GND 11 VCO IN 12 I Ground for VCO. VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO oscillation frequency. VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 1). VCO OUT 3 O VCO output. When VCO INHIBIT is high, VCO OUT is low. VCO VDD 14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling between supplies. detailed description VCO oscillation frequency The VCO oscillation frequency is determined by an external resistor (RBIAS) connected between the VCO VDD and the BIAS terminals. The oscillation frequency and range depends on this resistor value. While all resistor values within the specified range result in excellent low temperature coefficients, the bias resistor value for the minimum temperature coefficient is nominally 2.2 kΩ with 3-V VDD and nominally 2.4 kΩ with 5-V VDD. For the lock frequency range refer to the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage. VCO Oscillation Frequency (f osc ) VCO Oscillation Frequency Range Bias Resistor (RBIAS) 1/2 VDD VCO Control Voltage (VCO IN) Figure 1. VCO Oscillation Frequency 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 VCO inhibit function The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during the power-down mode as shown in Table 1. Table 1. VCO Inhibit Function VCO INHIBIT VCO OSCILLATOR VCO OUT Low Active Active IDD(VCO) Normal High Stopped Low level Power Down PFD operation The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B. For clock recovery PLL systems, other types of phase detectors should be used. FIN– A FIN– B VOH PFD OUT Hi-Z VOL Figure 2. PFD Function Timing Chart PFD inhibit control A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops phase detection as shown in Table 2. A high level on the PFD INHIBIT terminal can also be used as the power-down mode for the PFD. Table 2. VCO Output Control Function PFD INHIBIT DETECTION PFD OUT Low Active Active IDD(PFD) Normal High Stopped Hi-Z Power Down POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 schematics VCO block schematic RBIAS BIAS VCO IN VCO Output Buffer Bias Control VCO OUT VCO INHIBIT PFD block schematic Charge Pump VDD FIN – A PFD OUT Detector FIN – B PFD INHIBIT absolute maximum ratings† Supply voltage (each supply), VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range (each input), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Input current (each input), II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output current (each output), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Continuous total power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 700 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 75°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 recommended operating conditions VDD = 3 V VDD = 5 V supply see Note 3) Supply voltage voltage, VDD (each supply, MIN NOM MAX 2.85 3 3.15 4.75 5 5.25 Input voltage, VI (inputs except VCO IN) 0 Output current, IO (each output) 0 VCO control voltage at VCO IN 1 VDD ±2 Lock frequency VDD = 3 V VDD = 5 V 37 VDD 55 43 100 Bias resistor resistor, RBIAS VDD = 3 V VDD = 5 V 1.8 2.7 2.2 3 UNIT V V mA V MHz kΩ NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and separated from each other. electrical characteristics over recommended operating free-air temperature range, VDD = 3 V (unless otherwise noted) VCO section PARAMETER TEST CONDITIONS VOH VOL High-level output voltage IOH = – 2 mA IOL = 2 mA VIT + II Positive input threshold voltage at TEST, VCO INHIBIT Zi(VCO IN) IDD(INH) Input impedance at VCO IN VI = VDD or ground VCO IN = 1/2 VDD VCO supply current (inhibit) See Note 4 Low-level output voltage Input current at TEST, VCO INHIBIT MIN TYP MAX 2.4 V 0.3 0.9 UNIT 1.5 V ±1 µA 10 0.01 V 2.1 MΩ 1 µA IDD(VCO) VCO supply current See Note 5 5.1 15 mA NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high. 5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, RBIAS = 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT is high. PFD section PARAMETER VOH VOL TEST CONDITIONS High-level output voltage IOH = – 2 mA IOL = 2 mA Low-level output voltage IOZ High-impedance-state output current VIH VIL High-level input voltage at FIN–A, FIN–B VIT + Ci Positive input threshold voltage at PFD INHIBIT Zi IDD(Z) Input impedance at FIN–A, FIN–B MIN TYP MAX 2.7 V PFD INHIBIT = high, VI = VDD or ground 0.2 V ±1 µA 2.1 V Low-level input voltage at FIN–A, FIN–B 0.9 0.9 Input capacitance at FIN–A, FIN–B 1.5 2.1 5 See Note 6 0.01 V V pF 10 High-impedance-state PFD supply current UNIT MΩ 1 µA IDD(PFD) PFD supply current See Note 7 0.7 4 mA NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited. 7. The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT open, and VCO OUT is inhibited. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 operating characteristics over recommended operating free-air temperature range, VDD = 3 V (unless otherwise noted) VCO section PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 38 48 55 MHz 10 µs 10 ns 2 8 ns 50% 55% fosc ts(fosc) Operating oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ tr tf Rise time, VCO OUT↑ CL = 15 pF, See Figure 3 Fall time, VCO OUT↓ CL = 15 pF, See Figure 3 Duty cycle at VCO OUT RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD α(fosc) Temperature coefficient of oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD, TA = –20°C to 75°C 0.03 %/°C kSVS(fosc) Supply voltage coefficient of oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 1.5 V, VDD = 2.85 V to 3.15 V 0.04 %/mV 3.3 45% Jitter absolute (see Note 9) RBIAS = 2.4 kΩ 100 ps NOTES: 8. The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level. 9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with a carefully designed printed circuit board (PCB) with no device socket. PFD section PARAMETER TEST CONDITIONS fmax tPLZ Maximum operating frequency tPHZ tPZL Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z tPZH tr Enable time, PFD INHIBIT↓ to PFD OUT high tf Fall time, PFD OUT↓ 6 TYP MAX 20 40 18 40 4.1 18 4.8 18 3.1 9 ns 1.5 9 ns 30 Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z Enable time, PFD INHIBIT↓ to PFD OUT low Rise time, PFD OUT↑ MIN See Figures 4 and 5 and Table 3 CL = 15 pF, pF POST OFFICE BOX 655303 See Figure 4 • DALLAS, TEXAS 75265 UNIT MHz ns ns TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V (unless otherwise noted) VCO section PARAMETER TEST CONDITIONS VOH VOL High-level output voltage IOH = – 2 mA IOL = 2 mA VIT + II Positive input threshold voltage at TEST, VCO INHIBIT Zi(VCO IN) IDD(INH) Input impedance at VCO IN VI = VDD or ground VCO IN = 1/2 VDD VCO supply current (inhibit) See Note 4 Low-level output voltage Input current at TEST, VCO INHIBIT MIN TYP MAX 4.5 1.5 UNIT V 2.5 0.5 V 3.5 V ±1 10 0.01 µA MΩ 1 µA IDD(VCO) VCO supply current See Note 5 14 35 mA NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD, and PFD INHIBIT high. 5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, RBIAS = 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT high. PFD section PARAMETER TEST CONDITIONS IOH = 2 mA IOL = 2 mA MIN TYP MAX VOH VOL High-level output voltage IOZ High-impedance-state output current VIH VIL High-level input voltage at FIN–A, FIN–B VIT + Ci Positive input threshold voltage at PFD INHIBIT Input capacitance at FIN–A, FIN–B 7 pF Zi IDD(Z) Input impedance at FIN–A, FIN–B 10 MΩ Low-level output voltage 4.5 UNIT V PFD INHIBIT = high, VI = VDD or ground V ±1 µA 3.5 V Low-level input voltage at FIN–A, FIN–B High-impedance-state PFD supply current 0.2 1.5 See Note 6 2.5 0.01 1.5 V 3.5 V 1 µA IDD(PFD) PFD supply current See Note 10 2.6 8 mA NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited. 10. The current into LOGIC VDD when FIN–A and FIN–B = 50 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = ground, PFD OUT open, and VCO OUT is inhibited. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 operating characteristics over recommended operating free-air temperature range, VDD = 5 V (unless otherwise noted) VCO section PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 64 80 96 MHz 10 µs 5 ns 1.5 4 ns 50% 55% fosc ts(fosc) Operating oscillation frequency RBIAS = 2.4 kΩ,, VCO IN = 1/2 VDD Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ tr tf Rise time, VCO OUT↑ CL = 15 pF, See Figure 3 Fall time, VCO OUT↓ CL = 15 pF, See Figure 3 Duty cycle at VCO OUT RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD α(fosc) Temperature coefficient of oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD, TA = –20°C to 75°C 0.03 %/°C kSVS(fosc) Supply voltage coefficient of oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 2.5 V, VDD = 4.75 V to 5.25 V 0.02 %/mV 2.1 45% Jitter absolute (see Note 9) RBIAS = 2.4 kΩ 100 ps NOTES: 8: The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level. 9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with a carefully designed printed circuit board (PCB) with no device socket. PFD section PARAMETER TEST CONDITIONS fmax tPLZ Maximum operating frequency tPHZ tPZL Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z tPZH tr Enable time, PFD INHIBIT↓ to PFD OUT high tf Fall time, PFD OUT↓ 8 TYP MAX 20 40 17 40 3.7 10 3.4 10 1.7 5 ns 1.3 5 ns 50 Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z Enable time, PFD INHIBIT↓ to PFD OUT low Rise time, PFD OUT↑ MIN See Figures 4 and 5 and Table 3 CL = 15 pF, pF See Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz ns ns TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 PARAMETER MEASUREMENT INFORMATION 90% 90% VCO OUT 10% 10% tr tf Figure 3. VCO Output Voltage Waveform FIN– A† FIN– B† VDD VDD GND GND VDD VDD GND GND VDD PFD INHIBIT 50% VDD 50% 50% 50% GND tr PFD OUT 10% GND tPHZ tf Hi-Z VOH 90% 50% tPLZ 90% 50% 50% 50% 10% Hi-Z VOL tPZL tPZH (a) PFD OUT Hi-Z Timing To and From a High Level (see Figure 5 and Table 3) (b) PFD OUT Hi-Z Timing To and From a Low Level (see Figure 5 and Table 3) † FIN–A and FIN–B are for reference phase only, not for timing. Figure 4. PFD Output Voltage Waveform Table 3. PFD Output Test Conditions PARAMETER RL CL tPZH tPHZ tr tPZL tPLZ tf S1 VDD Test Point S2 S1 RL Open 1 kΩ Closed DUT PFD OUT 15 pF CL Closed S2 Open Figure 5. PFD Output Test Conditions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 TYPICAL CHARACTERISTICS VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE 90 VDD = 3 V RBIAS = 1.8 kΩ 80 f osc – VCO Oscillation Frequency – MHz f osc – VCO Oscillation Frequency – MHz 90 – 20°C 70 75°C 60 50 25°C 40 30 20 10 VDD = 3 V RBIAS = 2.2 kΩ 80 25°C 60 75°C 50 40 30 – 20°C 20 10 0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VCO IN – VCO Control Voltage – V 0 3 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VCO IN – VCO Control Voltage – V Figure 6 VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE 80 80 25°C – 20°C VDD = 3 V RBIAS = 2.4 kΩ 70 f osc – VCO Oscillation Frequency – MHz f osc – VCO Oscillation Frequency – MHz 3 Figure 7 VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE 75°C 60 50 40 30 – 20°C 20 10 VDD = 3 V RBIAS = 2.7 kΩ 70 25°C 60 50 – 20°C 40 75°C 30 20 10 0 0 0 0.8 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 0 0.3 0.6 0.9 1.2 1.5 Figure 8 Figure 9 POST OFFICE BOX 655303 1.8 2.1 2.4 VCO IN – VCO Control Voltage – V VCO IN – VCO Control Voltage – V 10 – 20°C 70 • DALLAS, TEXAS 75265 2.7 3 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 TYPICAL CHARACTERISTICS VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE 160 – 20°C VDD = 5 V RBIAS = 2.2 kΩ 140 120 f osc – VCO Oscillation Frequency – MHz f osc – VCO Oscillation Frequency – MHz 160 25°C 100 75°C 80 60 75°C 40 – 20°C 20 VDD = 5 V RBIAS = 2.4 kΩ 140 120 25°C 100 75°C 80 60 75°C 40 – 20°C 20 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 0.5 1 VCO IN – VCO Control Voltage – V 1.5 2 2.5 3 3.5 4 5 4.5 VCO IN – VCO Control Voltage – V Figure 10 Figure 11 VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE 140 VDD = 5 V RBIAS = 2.7 kΩ 120 f osc – VCO Oscillation Frequency – MHz 140 f osc – VCO Oscillation Frequency – MHz – 20°C – 20°C 25°C 100 75°C 80 60 75°C 40 20 – 20°C VDD = 5 V RBIAS = 3 kΩ 120 – 20°C 25°C 100 75°C 80 60 40 75°C 20 – 20°C 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VCO IN – VCO Control Voltage – V 5 0 0.5 1 1.5 2 2.5 3 3.5 4 VCO IN – VCO Control Voltage – V Figure 12 4.5 5 Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 TYPICAL CHARACTERISTICS RECOMMENDED LOCK FREQUENCY vs BIAS RESISTOR 110 VDD = 3 V ± 5% TA = – 20°C to 75°C Recommended Lock Frequency – MHz Recommended Lock Frequency – MHz 60 RECOMMENDED LOCK FREQUENCY vs BIAS RESISTOR 55 MAX 50 45 40 MIN 35 30 1.8 2.2 2.4 RBIAS – Bias Resistor – kΩ 2.7 100 90 MAX 80 70 60 50 MIN 40 30 2.2 Figure 14 12 VDD = 5 V ± 5% TA = – 20°C to 75°C 2.7 2.4 RBIAS – Bias Resistor – kΩ Figure 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 APPLICATION INFORMATION gain of VCO and PFD Figure 16 is a block diagram of the PLL. The divider N value depends on the input frequency and the desired VCO output frequency according to the system application requirements. The Kp and KV values are obtained from the operating characteristics of the device as shown in Figure 16. Kp is defined from the phase detector VOL and VOH specifications and the equation shown in Figure 16(b). KV is defined from Figures 8, 9, 10, and 11 as shown in Figure 16(c). The parameters for the block diagram with the units are as follows: Divider (KN = 1/N) PFD (Kp) f REF VCO (KV) TLC2933 LPF (Kf) VOH (a) – 2π – π 0 π KV : VCO gain (rad/s/V) Kp : PFD gain (V/rad) Kf : LPF gain (V/V) KN : countdown divider gain (1/N) 2π fMAX VOH VOL fMIN Range of Comparison external counter When a large N counter is required by the application, there is a possibility that the PLL response becomes slow due to the counter response delay time. In the case of a high frequency application, the counter delay time should be accounted for in the overall PLL design. VIN MIN Kp = VOH – VOL 4π (b) KV = VIN MAX 2π(fMAX – fMIN) VIN MAX – VIN MIN (c) Figure 16. Example of a PLL Block Diagram RBIAS The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCO IN terminal. For the most accurate results, a metal-film resistor is the better choice but a carbon-composition resistor can also be used with excellent results. A 0.22 µF capacitor should be connected from the BIAS terminal to ground as close to the device terminals as possible. hold-in range From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter configurations shown in Figure 17 is as follows: DwH ] 0.8 Where ǒ Ǔ ǒ Ǔ ǒ RǓ Kp K V K ( ) f (1) Kf (∞) = the filter transfer function value at ω = ∞ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 APPLICATION INFORMATION low-pass-filter (LPF) configurations Many excellent references are available that include detailed design information about LPFs and should be consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown in Figure 17. When the active filter of Figure 17(c) is used, the reference should be applied to FIN-B because of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO input. The value of C2 should be equal to or less than one tenth the value of C1. C2 R1 R1 VI VO T1 = C1R1 C1 VI VO T1 = C1R1 T2 = C1R2 R2 C1 R2 C2 C1 – VI R1 (a) LAG FILTER A VO T1 = C1R1 T2 = C1R2 (b) LAG-LEAD FILTER (c) ACTIVE FILTER Figure 17. LPF Examples for PLL the passive filter The transfer function for the low-pass filter shown in Figure 17(b) is; V V O IN + 1 )1s)@ s(T1@ T2 ) T2) where T1 (2) + R1 @ C1 and T2 + R2 @ C1 Using this filter makes the closed-loop PLL system a type 1 second-order system. The response curves of this system to a unit step are shown in Figure 18. the active filter When using the active filter shown in Figure 17(c), the phase detector inputs must be reversed since the filter adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A. @ C1 + 1 )s @s @R1R2@ C1 The transfer function for the active filter shown in Figure 17(c) is: F(s) (3) Using this filter makes the closed-loop PLL system a type 2 second-order system. The response curves of this system to a unit step are shown in Figure 19. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 APPLICATION INFORMATION Using the lag-lead filter in Figure 17(b) and divider N value, the transfer function for phase and frequency are shown in equations 4 and 5. Note that the transfer function for phase differs from the transfer function for frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity while the feedback for frequency is 1/N. ȱȧ ȧȧ Ȳ Hence, the transfer function of Figure 17(a) for phase is F2(s) + F1(s) N @ @) K Kp (T1 V T2) ȱȧ ȧȧ Ȳ ƪ ƫ ) s @ T2 K p@K @T2 K p@K V V ) s2 ) s 1 ) N@(T1)T2) N@(T1)T2) 1 and the transfer function for frequency is F OUT(s) F REF(s) Kp @ K V + (T1 ) T2) s2 Ǹ@@ ȳȧ ȧȧ ȴ ƪ )s@ 1) @ @ )@ @ ) ƫ 1 s T2 K p K T2 V N (T1 T2) @) ) N@(T1 Kp K ȳȧ ȧȧ ȴ (4) (5) V T2) The standard 2-pole denominator is D = s2 + 2 ζ ωn s + ωn2 and comparing the coefficients of the denominator of equation (4) and (5) with the standard 2-pole denominator gives the following results. wn + Kp N (T1 K (6) ) V T2) Solving for T1 + T2 T1 ) T2 + KNp@@wKV2 ǒ n Ǔ and by using this value for T1 + T2 in equation (6) the damping factor is z + w2n @ T2 ) Kp @N K (7) V solving for T2 T2 + 2wz – Kp @N K @ @ (8) V then by substituting for T2 in equation (6) Kp K 2 z V N – w T1 2 K n N wn p KV + ) @ POST OFFICE BOX 655303 (9) • DALLAS, TEXAS 75265 15 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 ƪ @ ƫ APPLICATION INFORMATION From the circuit constants and the initial design parameters then R2 R1 + ȱȧ Ȳ + z N wn * Kp K 2 Kp wn @ @ 2 z N * ) w K n p@K N Kv 2 V 1 C1 (10) ȳȧ ȴ 1 C1 V (11) The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and physical capacitor size. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 APPLICATION INFORMATION 1.9 1.8 z = 0.1 1.7 z = 0.2 1.6 z = 0.3 1.5 z = 0.4 1.4 z = 0.6 z = 0.5 1.3 z = 0.7 Normalized Gain Response 1.2 z = 0.8 1.1 1 0.9 z = 1.0 0.8 z = 1.5 0.7 0.6 z = 2.0 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 ωnts = 4.5 6 7 8 9 10 11 12 13 ωnt Figure 18. Type 1 Second-Order Step Response POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 APPLICATION INFORMATION 1.9 ζ = 0.1 1.8 1.7 ζ = 0.2 1.6 ζ = 0.3 1.5 ζ = 0.4 ζ = 0.5 1.4 ζ = 0.6 1.3 ζ = 0.7 Normalized Gain Response 1.2 1.1 1 0.9 ζ = 0.8 0.8 ζ = 1.0 0.7 ζ = 2.0 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 ωnt Figure 19. Type 2 Second-Order Step Response 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 11 12 13 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 APPLICATION INFORMATION AVDD VDD 1 2 VCO LOGIC VDD (Digital) 14 VCO VDD TEST R1† 13 BIAS 0.22 µF REF IN DGND 3 VCO OUT 4 FIN – A 5 FIN – B 6 PFD OUT VCO IN VCO GND R3 12 11 C2 R2 C1 VCO INHIBIT 10 AGND 7 Divide By N Phase Comparator LOGIC GND (Digital) PFD INHIBIT 9 NC 8 DGND S1 S2 R5 R6 DGND DVDD † RBIAS resistor Figure 20. Evaluation and Operation Schematic PCB layout considerations The TLC2933 contains a high frequency oscillator; therefore, very careful breadboarding and PCB layout is required for evaluation. The following design recommendations benefit the TLC2933 user: D D D D D D External analog and digital circuitry should be physically separated and shielded as much as possible to reduce system noise. Radio frequency (RF) breadboarding or RF PCB techniques should be used throughout the evaluation and production process. Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance and resistance. The ground plane is the better choice for noise reduction. LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point available in the system to minimize supply cross-coupling. VCO VDD to ground and LOGIC VDD to ground should be decoupled with a 0.1-µF capacitor placed as close as possible to the appropriate device terminals. The no-connection (NC) terminal on the package should be connected to ground to prevent stray pickup. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP SLAS136A – APRIL 1996 – REVISED JUNE 1997 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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