TI TLC2942PW

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
D
D
D
D
DB PACKAGE
Dual TLC2932 by Multichip Module (MCM)
Technology
Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
– Recommended Lock Frequency Range:
22 MHz to 50 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1 Output)
11 MHz to 25 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1/2 Output)
– Output Frequency . . . ×1 and ×1/2
Selectable
Includes a High-Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump
Independent VCO, PFD Power-Down Mode
(TOP VIEW)
LOGIC VDD1
SELECT1
VCO OUT1
FIN–A1
FIN–B1
PFD OUT1
LOGIC GND1
GND
NC
NC
NC
GND
LOGIC VDD2
SELECT2
VCO OUT2
FIN–A2
FIN–B2
PFD OUT2
LOGIC GND2
description
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
VCO VDD1
BIAS1
VCOIN1
VCO GND1
VCOINHIBIT1
PFD INHIBIT1
NC
GND
NC
NC
NC
GND
VCO VDD2
BIAS2
VCOIN2
VCO GND2
VCOINHIBIT2
PFD INHIBIT2
NC
18
The TLC2942 is a multichip module product that
21
19
uses two TLC2932 chips. The TLC2932 chip is
20
composed of a voltage-controlled oscillator and
an edge-triggered phase frequency detector. The
NC – No internal connection
oscillation frequency range of each VCO is set by
an external bias resistor (RBIAS) and each VCO output can be a ×1 or ×1/2 output frequency. Each high speed
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. The VCO and the PFD have inhibit functions that can be used as a
power-down mode. The high-speed and stable oscillation capability of the TLC2932 makes the TLC2942
suitable for use in dual high-performance phase-locked loop (PLL) systems.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(DB)
–20°C to 75°C
TLC2942IDB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
functional block diagram
VCO
VCO
INHIBIT1 VCO OUT1 VCO OUT2 INHIBIT2
34
VCOIN1
FIN–A1
36
SELECT1
2
3
15
VCO_1
VCO_2
VCOIN2
FIN–A2
PFD_2
17
5
33
6
PFD OUT1
PFD INHIBIT1
2
24
16
4
PFD_1
FIN–B1
SELECT2
14
22
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18
21
PFD OUT2
PFD INHIBIT2
• DALLAS, TEXAS 75265
FIN–B2
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
Terminal Functions
TERMINAL
NO.
I/
O
BIAS1
37
I
VCO1 bias supply. An external resistor (RBIAS1) between VCO VDD1 and BIAS1 supplies bias for adjusting
the oscillation frequency range.
BIAS2
25
I
VCO2 bias supply. An external resistor (RBIAS2) between VCO VDD2 and BIAS2 supplies bias for adjusting
the oscillation frequency range.
FIN–A1
FIN–A2
4
I
Input reference frequency 1. The frequency f(REF IN)1 is applied to FIN-A1.
16
I
Input reference frequency 2. The frequency f(REF IN)2 is applied to FIN-A2.
FIN–B1
5
I
Input for VCO1 external counter output frequency f(FIN-B)1. FIN-B1 is nominally provided from the external
counter (see Figure 28).
FIN–B2
17
I
Input for VCO2 external counter output frequency f(FIN-B)2. FIN-B2 is nominally provided from the external
counter (see Figure 28).
NAME
GND
8, 12,
27,31
DESCRIPTION
Ground
LOGIC VDD1
1
Logic1 supply voltage. LOGIC VDD1 supplies voltage to internal logic 1. LOGIC VDD1 should be separate
from the other supply lines to reduce cross-coupling between power supplies.
LOGIC VDD2
13
Logic2 supply voltage. LOGIC VDD2 supplies voltage to internal logic 2. LOGIC VDD2 should be separate
from the other supply lines to reduce cross-coupling between power supplies.
LOGIC GND1
7
Ground for the internal logic 1
LOGIC GND2
19
Ground for the internal logic 2
NC
9, 10, 11,
20, 28,
29, 30,
32
No internal connection
PFD INHIBIT1
33
I
PFD inhibit 1 control. When PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state (see
Table 4).
PFD INHIBIT2
21
I
PFD inhibit 2 control. When PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state (see
Table 5).
PFD OUT1
6
O
PFD1 output. When the PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state.
PFD OUT2
18
O
PFD2 output. When the PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state.
SELECT1
2
I
VCO1 output frequency select. When SELECT1 is high, the VCO1 output frequency is
SELECT1 is low, the output frequency is 1 (see Table 1).
SELECT2
14
I
VCO2 output frequency select. When SELECT2 is high, the VCO2 output frequency is
SELECT2 is low, the output frequency is 1 (see Table 1).
VCO GND1
35
Ground for VCO1
VCO GND2
23
Ground for VCO2
VCOINHIBIT1
34
I
VCO1 inhibit control. When VCOINHIBIT1 is high, VCO OUT1 is low (see Table 2).
VCOINHIBIT2
22
O
VCO2 inhibit control. When VCOINHIBIT2 is high, VCO OUT2 is low (see Table 3).
VCO OUT1
3
O
VCO1 output. When VCOINHIBIT1 is high, VCO OUT1 is low.
VCO OUT2
15
VCO2 output. When VCOINHIBIT2 is high, VCO OUT2 is low.
VCO VDD1
38
VCO1 supply voltage. VCO VDD1 supplies voltage for VCO1. VCO VDD1 should be separated from LOGIC
VDD1 and LOGIC VDD2 and VCO VDD2 to reduce cross-coupling between power supplies.
VCO VDD2
26
VCO2 supply voltage. VCO VDD2 supplies voltage for VCO2. VCO VDD2 should be separated from LOGIC
VDD1 and LOGIC VDD2 and VCO VDD1 to reduce cross-coupling between power supplies.
VCOIN1
36
I
VCO1 control voltage input. Nominally the external loop filter output1 connects to VCOIN1 to control VCO1
oscillation frequency.
VCOIN2
24
I
VCO2 control voltage input. Nominally the external loop filter output2 connects to VCOIN2 to control VCO2
oscillation frequency.
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1/2 and when
1/2 and when
3
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
detailed description
multichip module
The TLC2942 is a multichip module (MCM) product that uses two TLC2932 chips. A newly developed lead frame
for TLC2942IBD is specially shaped and cut in the package to electrically isolate one chip from another. The
two chips are completely independent from each other to perform the best stable oscillation and locking. If
asynchronous locking operation is required for these two PLL blocks, each TLC2942 VCO and PFD can achieve
the same stability as the single chip TLC2932IPW.
Three NC terminals are on both sides of the package between chip1 and chip2 due to the lead frame shape.
To avoid performance degradation, special attention is needed for each PLL block PCB layout especially for
supply voltage lines and GND patterns.
voltage-controlled oscillator (VCO)
VCO1 and VCO2 have the same typical characteristics. Each VCO oscillation frequency is determined by an
external resistor (RBIAS) connected between each VCO VDD and BIAS terminals. The oscillation frequency and
range depends on this register value. The bias resistor value for the minimum temperature coefficient is
nominally 3.3 kΩ with VDD = 3 V and nominally 2.2 kΩ with VDD = 5 V. For the lock frequency range refer to
the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control
voltage.
VCO Oscillation Frequency (f osc )
VCO Oscillation Frequency Range
Bias Resistor (RBIAS)
1/2 VDD
VCO Control Voltage (VCOIN)
Figure 1. VCO1 and VCO2 Oscillation Frequency
VCO output frequency 1/2 divider
SELECT1 and SELECT2 select between fosc and 1/2 fosc for the VCO output frequencies as shown in Table 1.
Table 1. SELECT1 and SELECT2 Function Table
4
SELECT1
VCO1 OUTPUT
FREQUENCY
Low
fosc1
Low
fosc2
High
1/2 fosc1
High
1/2 fosc2
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SELECT2
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VCO2 OUTPUT
FREQUENCY
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO inhibit function
Each VCO has an externally controlled inhibit function that inhibits the VCO output. The VCO oscillation is
stopped during a high level on VCOINHIBIT, so the high level can also be used as the power-down mode. The
VCO output maintains a low level during the power-down mode (see Table 2 and Table 3).
Table 2. VCO1 Inhibit Function
VCOINHIBIT1
VCO1 OSCILLATOR
VCO OUT1
VCO1 IDD
Low
Active
Active
Normal
High
Stop
Low
Power Down
Table 3. VCO2 Inhibit Function
VCOINHIBIT2
VCO2 OSCILLATOR
VCO OUT2
VCO2 IDD
Low
Active
Active
Normal
High
Stop
Low
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.
FIN– A1,
FIN– A2
FIN– B1,
FIN– B2
VOH
PFD OUT1,
PFD OUT2
Hi-Z
VOL
Figure 2. PFD Function Timing Chart
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5
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
PFD output control
A high level on PFD INHIBIT places the PFD OUT in the high-impedance state and the PFD stops phase
detection as shown in Table 4 and Table 5. A high level on PFD INHIBIT also can be used as the power-down
mode for the PFD.
Table 4. PFD1 Inhibit Function
PFD INHIBIT1
DETECTION
PFD OUT1
PFD1 IDD
Low
Active
Active
Normal
High
Stop
Hi-Z
Power Down
Table 5. PFD2 Inhibit Function Table
PFD INHIBIT2
DETECTION
PFD OUT2
PFD2 IDD
Low
Active
Active
Normal
High
Stop
Hi-Z
Power Down
schematics
VCO block schematic (VCO1, VCO2)
RBIAS
Ring Oscillator
1/2
VCO
Output
Bias
Circuit
VCOIN1,
VCOIN2
(VCO control)
VCOINHIBIT
SELECT1,2
PFD block schematic (PFD1, PFD2)
Charge Pump
VDD
FIN – A
PFD OUT
Detector
FIN – B
PFD INHIBIT
6
M
U
X
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VCO OUT1,
VCO OUT2
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (each supply), VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range (each input), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VDD + 0.5 V
Input current (each input), II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output current (each output), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous total power dissipation, at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . 1160 mW
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 75°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 9.3 mW/°C.
recommended operating conditions
Supply voltage
voltage, VDD (each supply,
supply see Note 3)
VDD = 3 V
VDD = 5 V
MIN
NOM
MAX
2.85
3
3.15
4.75
5
5.25
Input voltage, VI, (all inputs except VCOIN1, VCOIN2)
0
Output current, IO (each output)
0
VCO control voltage at each VCOIN1, VCOIN2
VDD
±2
0.9
Lock frequency,
frequency (each VCO) (×1 output)
VDD = 3 V
VDD = 5 V
frequency (each VCO) (×1/2 output)
Lock frequency,
VDD = 3 V
VDD = 5 V
Bias resistor
resistor, (each BIAS)
BIAS), RBIAS1,
BIAS1 RBIAS2
VDD = 3 V
VDD = 5 V
Operating temperature, TA
14
VDD
21
22
50
7
10.5
11
25
2.2
3.3
4.3
1.5
2.2
3.3
–20
75
UNIT
V
V
mA
V
MHz
MHz
kΩ
°C
NOTE 3: It is recommended that LOGIC VDD1 and VCO VDD1 or LOGIC VDD2 and VCO VDD2 should be at the same voltage and separated from
each other.
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 electrical characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level output voltage
IOH = – 2 mA
IOL = 2 mA
Low-level output voltage
VIT
Input threshold voltage
SELECT1, SELECT2,
VCOINHIBIT2, VCOINHIBIT1
II
Input current
SELECT1, SELECT2,
VCOINHIBIT2, VCOINHIBIT1
VI = VDD or GND
Zi(VCOIN)
IDD(INH)
Input impedance
VCOIN2, VCOIN1
VCOIN = 1/2 VDD
VCO supply current (inhibit) (each chip)
MIN
TYP
MAX
2.4
0.9
V
1.5
0.3
V
2.1
V
±1
µA
10
See Note 4
UNIT
0.01
MΩ
1
µA
IDD(VCO)
VCO supply current (each chip)
See Note 5
5
15
mA
NOTES: 4. The current into VCO VDD and LOGIC VDD when VCOINHIBIT = VDD, and the PFD is inhibited.
5. The current into VCO VDD and LOGIC VDD when VCOIN = 1/2 VDD, RBIAS = 3.3 kΩ, VCOINHIBIT = GND, and the PFD is inhibited.
PFD1, PFD2 electrical characteristic, VDD = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level output voltage
IOH = – 2 mA
IOL = 2 mA
Low-level output voltage
MIN
TYP
MAX
2.7
UNIT
V
PFD INHIBIT = high,
VO = VDD or GND
0.2
V
±1
µA
IOZ
High-impedance output current
VIH
High-level input voltage
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
VIL
Low-level input voltage
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
VIT
Input threshold voltage
PFD INHIBIT2, PFD INHIBIT1
Ci
Input capacitance
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
5
pF
Zi
Input impedance
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
10
MΩ
IDD(Z)
High-impedance state PFD supply current
2.7
0.9
See Note 6
V
1.5
0.1
0.5
V
2.1
V
1
µA
IDD(PFD) PFD supply current
See Note 7
0.1
1.5
mA
NOTES: 6. The current into LOGIC VDD, when FIN–A and FIN–B = GND, PFD INHIBIT= VDD, no load, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FIN–A and FIN–B = 1 MHz with VI(PP) = 3 V rectangular wave, PFD INHIBIT = GND, no load,
and VCO OUT is inhibited.
8
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 operating characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fosc
Operating oscillation frequency
RBIAS1, RBIAS2 = 3.3 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD
ts(fosc)
Time to stable oscillation
See Note 8
tr
Rise time
tf
Fall time
MIN
TYP
MAX
UNIT
15
19
23
MHz
10
µs
CL = 15 pF,
See Figure 3
7
CL = 50 pF,
See Figure 3
14
CL = 15 pF,
See Figure 3
6
CL = 50 pF,
See Figure 3
10
14
12
ns
ns
Duty cycle at VCO OUT
RBIAS1, RBIAS2 = 3.3 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD
α(fosc)
Temperature coefficient of oscillation frequency
RBIAS1, RBIAS2 = 3.3 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD,
TA = –20°C to 75°C
0.04
%/°C
kSVS(fosc)
Supply voltage coefficient of oscillation frequency
RBIAS1, RBIAS2 = 3.3 kΩ,
VCOIN1, VCOIN2 = 1.5 V,
VDD = 2.85 V to 3.15 V
0.02
%/mV
45%
50%
55%
Jitter absolute (see Note 9)
RBIAS1 = 3.3 kΩ
100
ps
NOTES: 8. The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD1, PFD2 operating characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
fmax
tPLZ
Maximum operating frequency
tPHZ
tPZL
PFD output disable time from high level
tPZH
tr
PFD output enable time to high level
tf
Fall time
TEST CONDITIONS
MIN
TYP
MAX
21
50
23
50
20
PFD output disable time from low level
See Figures 4 and 5 and Table 4
PFD output enable time to low level
Rise time
CL = 15 pF,
pF
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• DALLAS, TEXAS 75265
UNIT
MHz
ns
11
30
10
30
2.3
10
ns
2.1
10
ns
ns
9
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 electrical characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage
IOH = – 2 mA
IOL = 2 mA
VIT
Input threshold voltage
SELECT1, SELECT2,
VCOINHIBIT1, VCOINHIBIT2
II
Input current
SELECT1, SELECT2,
VCOINHIBIT1, VCOINHIBIT2
VI = VDD or GND
Zi(VCOIN)
IDD(INH)
Input impedance
VCOIN1, VCOIN2
VCOIN = 1/2 VDD
Low-level output voltage
VCO supply current (inhibit) (each chip)
MIN
TYP
MAX
4
1.5
V
2.5
0.5
V
3.5
V
±1
µA
10
See Note 4
UNIT
0.01
MΩ
1
µA
IDD(VCO)
VCO supply current (each chip)
See Note 10
15
35
mA
NOTES: 4. The current into VCO VDD and LOGIC VDD when VCOINHIBIT = VDD, and the PFD is inhibited.
10. The current into VCO VDD and LOGIC VDD when VCOIN = 1/2 VDD, RBIAS = 2.2 kΩ, VCOINHIBIT = GND, and the PFD is inhibited.
PFD1, PFD2 electrical characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level output voltage
IOH = 2 mA
IOL = 2 mA
Low-level output voltage
MIN
TYP
MAX
4.5
UNIT
V
PFD INHIBIT1, PFD INHIBIT2 = high,
VO = VDD or GND
0.2
V
±1
µA
IOZ
High-impedance output current
VIH
High-level input voltage
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
VIL
Low-level input voltage
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
VIT
Input threshold voltage
PFD INHIBIT2,
PFD INHIBIT1
Ci
Input capacitance
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
5
pF
Zi
Input impedance
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
10
MΩ
IDD(Z)
IDD(PFD)
High-impedance state PFD supply current
See Note 6
0.1
1
µA
PFD supply current (each chip)
See Note 11
0.15
3
mA
4.5
1.5
V
2.5
1
V
3.5
V
NOTES: 6. The current into LOGIC VDD, when FIN–A and FIN–B = GND, PFD INHIBIT= VDD, no load, and VCO OUT is inhibited.
11. The current into LOGIC VDD when FIN–A and FIN–B = 1 MHz with VI(PP) = 5-V rectangular wave, PFD INHIBIT = GND, no load,
and
VCO OUT is inhibited.
10
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fosc
Operating oscillation frequency
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD
ts(fosc)
Time to stable oscillation
See Note 8
tr
Rise time
tf
Fall time
TYP
MAX
UNIT
32
41
50
MHz
10
µs
CL = 15 pF,
See Figure 3
5.5
CL = 50 pF,
See Figure 3
8
CL = 15 pF,
See Figure 3
5
CL = 50 pF,
See Figure 3
6
Duty cycle at VCO OUT
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD
α(fosc)
Temperature coefficient of oscillation frequency
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD,
Tope = –20°C to 75°C
kSVS(fosc)
Supply voltage coefficient of oscillation frequency
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 2.5 V,
VDD = 4.75 V to 5.25 V
NOTES: 8.
9.
MIN
45%
50%
10
10
ns
ns
55%
0.06
%/°C
0.006
%/mV
Jitter absolute (see Note 9)
RBIAS1 = 3.3 kΩ
100
ps
The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.
The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD1, PFD2 operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fmax
tPLZ
Maximum operating frequency
tPHZ
tPZL
PFD output disable time from high level
tPZH
tr
PFD output enable time to high level
tf
Fall time
Rise time
TYP
MAX
21
40
20
40
7.3
20
6.5
20
2.3
10
ns
1.7
10
ns
40
PFD output disable time from low level
PFD output enable time to low level
MIN
See Figures 4 and 5 and Table 4
CL = 15 pF,
pF
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UNIT
MHz
ns
ns
11
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
PARAMETER MEASUREMENT INFORMATION
90%
90%
VCO OUT1,
VCO OUT2
10%
10%
tr
tf
Figure 3. VCO Output Voltage Waveform
FIN– A1,
FIN– A2
FIN– B1,
FIN– B2
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
PFD INHIBIT1,
PFD INHIBIT2
VDD
50%
50%
GND
tr
PFD OUT1,
PFD OUT2
10%
GND
tPHZ
VOH
90%
50%
tPLZ
tf
50%
90%
GND
50%
10%
VDD
50%
VOL
tPZL
tPZH
(a) OUTPUT PULLDOWN
(see Figure 5 and Table 6)
(b) OUTPUT PULLUP
(see Figure 5 and Table 6)
† FIN–A and FIN–B are for reference phase only, not for timing.
Figure 4. PFD Output Voltage Waveform
Table 6. PFD1 and PDF2 Output Test Conditions
PARAMETER
RL
CL
tPZH
tPHZ
tr
tPZL
tPLZ
tf
S1
S2
Open
Close
VDD
Test Point
S1
RL
1 kΩ
15 pF
DUT
Close
PFD OUT
Open
CL
S2
Figure 5. PFD1 and PFD2 Output Test Conditions
12
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
100
VDD = 3 V
RBIAS = 2.2 kΩ
VDD = 5 V
RBIAS = 1.5 kΩ
– 20°C
25°C
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
40
30
75°C
20
10
– 20°C
80
25°C
60
75°C
40
20
0
0
1
2
VI (VCOIN) – VCO Control Voltage – V
3
4
1
2
3
VI (VCOIN) – VCO Control Voltage – V
0
Figure 6
Figure 7
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
80
VDD = 3 V
RBIAS = 3.3 kΩ
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
40
– 20°C
30
75°C
25°C
20
10
0
1
2
VI (VCOIN) – VCO Control Voltage – V
3
VDD = 5 V
RBIAS = 2.2 kΩ
– 20°C
60
75°C
25°C
40
20
0
0
5
0
Figure 8
1
2
3
4
VI (VCOIN) – VCO Control Voltage – V
5
Figure 9
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
80
VDD = 3 V
RBIAS = 4.3 kΩ
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
40
30
75°C
25°C
20
– 20°C
10
0
0
1
2
VI (VCOIN) – VCO Control Voltage – V
VDD = 5 V
RBIAS = 3.3 kΩ
60
40
25°C
20
– 20°C
0
3
75°C
0
1
2
3
4
VI (VCOIN) – VCO Control Voltage – V
Figure 10
Figure 11
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
60
VDD = 3 V
VCOIN = 1/2 VDD
TA = 25°C
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
30
25
20
15
10
2
2.5
3.5
4
3
RBIAS – Bias Resistor – kΩ
4.5
VDD = 5 V
VCOIN = 1/2 VDD
TA = 25°C
50
40
30
20
1.5
Figure 12
14
5
3
2
2.5
RBIAS – Bias Resistor – kΩ
Figure 13
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3.5
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.4
VDD = 3 V
VCOIN = 1/2 VDD
TA = – 20°C to 75°C
α (f osc) – Temperature Coefficient of Oscillation
Frequency – % / °C
α (f osc) – Temperature Coefficient of Oscillation
Frequency – % / °C
0.4
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.3
0.2
0.1
0
2
2.5
3
4
3.3 3.5
RBIAS – Bias Resistor – kΩ
4.5
VDD = 5 V
VCOIN = 1/2 VDD
TA = – 20°C to 75°C
0.3
0.2
0.1
0
1.5
2
2.5
3
2.2
RBIAS – Bias Resistor – kΩ
Figure 15
Figure 14
VCO OSCILLATION FREQUENCY
vs
VCO SUPPLY VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO SUPPLY VOLTAGE
48
24
RBIAS = 3.3 kΩ
VCOIN = 1.5 V
TA = 25°C
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
3.5
22
20
18
16
2.85
3
VDD – VCO Supply Voltage – V
3.15
RBIAS = 2.2 kΩ
VCOIN = 1/2 VDD
TA = 25°C
44
40
36
32
4.75
Figure 16
5
VDD – VCO Supply Voltage – V
5.25
Figure 17
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
VDD = 2.85 V to 3.15 V
VCOIN = 1/2 VDD
TA = 25°C
VDD = 4.75 V to 5.25 V
VCOIN = 1/2 VDD
TA = 25°C
k SVS(fosc) – Supply Voltage Coefficient of
Oscillation Frequency – %/V
k SVS(fosc) – Supply Voltage Coefficient of
Oscillation Frequency – %/V
0.05
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.04
0.03
0.02
0.01
0
2
2.5
3.5
4
3
RBIAS – Bias Resistor – kΩ
0.01
0.005
0
1.5
4.5
Figure 18
2.5
3
2
RBIAS – Bias Resistor – kΩ
3.5
Figure 19
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
BIAS RESISTOR
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
BIAS RESISTOR
60
VDD = 2.85 V to 3.15 V
TA = – 20°C to 75°C
Recommended Lock Frequency – MHz
Recommended Lock Frequency – MHz
30
25
20
15
10
2
2.5
3
3.5
4
RBIAS – Bias Resistor – kΩ
4.5
VDD = 4.75 V to 5.25 V
TA = – 20°C to 75°C
50
40
30
20
10
1.5
Figure 20
16
2
2.5
3
RBIAS – Bias Resistor – kΩ
Figure 21
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3.5
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
BIAS RESISTOR
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
BIAS RESISTOR
30
VDD = 2.85 V to 3.15 V
TA = – 20°C to 75°C
SELECT = VDD
Recommended Lock Frequency – MHz
Recommended Lock Frequency – MHz
15
12.5
10
7.5
5
2
2.5
3.5
4
3
RBIAS – Bias Resistor – kΩ
4.5
25
VDD = 4.75 V to 5.25 V
TA = – 20°C to 75°C
SELECT = VDD
20
15
10
5
1.5
Figure 22
2
2.5
3
RBIAS – Bias Resistor – kΩ
3.5
Figure 23
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The Kp
and KV values are obtained from the operating
characteristics of the device as shown in Figure
24. Kp is defined from the phase detector VOL and
VOH specifications and the equation shown in
Figure 24(b). KV is defined from Figures 8, 9, 10,
and 11 as shown in Figure 24(c).
Divider
(KN = 1/N)
PFD
(Kp)
fREF
VCO
(KV)
TLC2942
LPF
(Kf)
The parameters for the block diagram with the
units are as follows:
KV : VCO gain (rad/s/V)
Kp : PFD gain (V/rad)
Kf : LPF gain (V/V)
KN : countdown divider gain (1/N)
VOH
(a)
– 2π – π
0
π
2π
fMAX
VOH
VOL fMIN
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
Range of
Comparison
VIN MIN
Kp =
VOH – VOL
4π
(b)
KV =
VIN MAX
2π(fMAX – fMIN)
VIN MAX – VIN MIN
(c)
Figure 24. Example of a PLL Block Diagram
RBIAS
The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCOIN terminal. However,
for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply, or a resistor value of
2.5 kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice,
but a carbon-compositiion resistor can be used with excellent results also. A 0.22-µF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
DwH ] 0.8
Where
18
ǒ Ǔ ǒ Ǔ ǒ RǓ
Kp
K
V
K ( )
f
(1)
Kf (∞) = the filter transfer function value at ω = ∞
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and they should
be consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are
shown in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B
because of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at
the VCO input. The value of C2 should be equal to or less than one-tenth the value of C1.
C2
R1
R1
VI
VO
T1 = C1R1
C1
VI
VO
T1 = C1R1
T2 = C1R2
R2
C1
R2
C2
C1
–
VI
R1
(a) LAG FILTER
A
VO
T1 = C1R1
T2 = C1R2
(b) LAG-LEAD FILTER
(c) ACTIVE FILTER
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the low-pass filter shown in Figure 25(b) is:
V
V
O
IN
+ 1 )1s)@ s(T1@ T2
) T2)
Where
T1
(2)
+ R1 @ C1 and T2 + R2 @ C1
Using this filter makes the closed loop PLL system a type 1 second-order system. The response curves of this
system to a unit step are shown in Figure 26.
the active filter
When using the active filter shown in Figure 25(c), the phase detector inputs must be reversed since the filter
adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B terminal
and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
F(s)
+ 1 )s @s @R1R2@ @C1C1
(3)
Using this filter makes the closed loop PLL system a type 2 second-order system. The response curves of this
system to a unit step are shown in Figure 27.
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
1.9
1.8
z = 0.1
1.7
z = 0.2
1.6
z = 0.3
1.5
z = 0.4
1.4
z = 0.6
z = 0.5
1.3
z = 0.7
1.2
φ 2 (t), Normalized Response
z = 0.8
1.1
1
0.9
z = 1.0
0.8
z = 1.5
0.7
0.6
z = 2.0
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
ωnts = 4.5
7
8
9
10
ωnt
Figure 26. Type 1 Second-Order Step Response
20
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12
13
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
1.9
ζ = 0.1
1.8
1.7
ζ = 0.2
1.6
ζ = 0.3
1.5
ζ = 0.4
ζ = 0.5
1.4
ζ = 0.6
1.3
φ 0 (t), Normalized Output Frequency
ζ = 0.7
1.2
1.1
1
0.9
ζ = 0.8
0.8
ζ = 1.0
0.7
ζ = 2.0
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ωnt
Figure 27. Type 2 Second-Order Step Response
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
Assume the loop has to have a 100-µs settling time (ts) with a countdown divider N value = 8. Using the Type
1, second-order response curves of Figure 26, a value of 4.5 radians is selected for ωnts with a damping factor
of 0.7. This selection gives a good combination for settling time, accuracy, and loop gain margin. The initial
parameters are summarized in Table 7. The loop constants, KV and Kp, are calculated from the data sheet
specifications and Table 8 shows these values.
The natural loop frequency is calculated as follows:
Since
wnts + 4.5
Then
(4)
4.5 + 45 k-radiansńsec
wn + 100
ms
Table 7. Design Parameters
PARAMETER
SYMBOL
VALUE
N
8
Divider value
t
100
µs
ωnt
4.5
rad
ζ
0.7
Lockup time
Radian value to selected lockup time
UNITS
Damping factor
Table 8. Device Specifications
PARAMETER
SYMBOL
VCO gain
fMAX
fMIN
KV
VIN MAX
VIN MIN
PFD gain
Kp
VALUE
UNITS
76.6
Mrad/V/s
70
MHz
20
MHz
5
V
0.9
V
0.342357
V/rad
Using the low-pass filter in Figure 25(b) and divider N value, the transfer function for phase and frequency are
shown in equations 5 and 6. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
ȱȧ
ȧȧ
Ȳ
Hence, transfer function of Figure 24 (a) for phase is:
F2(s) +
F1(s) N
22
@
Kp
@)
(T1
K
V
T2)
s2
ƪ
)s 1)
@
@@ )@
)
ƫ
1 s T2
Kp K
T2
V
N (T1 T2)
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ȧȧ
ȴ
V
T2)
(5)
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
ȱȧ
ȧȧ
Ȳ
and the transfer function for frequency is:
F
OUT(s)
F
REF(s)
Kp @ K
V
+ (T1
) T2)
s2
Ǹ@@
ƪ
)s@ 1)
@
@ )@
@
)
ƫ
1 s T2
K p K T2
V
N (T1 T2)
@)
) N@(T1
Kp K
ȳȧ
ȧȧ
ȴ
(6)
V
T2)
The standard two-pole denominator is D = s2 + 2 ζ ωn s + ωn2 and comparing the coefficients of the denominator
of equation 5 and 6 with the standard two-pole denominator gives the following results:
wn +
Kp
N
(T1
K
) T2)
V
(7)
Solving for T1 + T2
T1
) T2 + KNp@@wKV2
ǒ
n
Ǔ
and by using this value for T1 + T2 in equation 7 the damping factor is:
z+
wn
2
@
T2
) Kp @N K
(8)
V
solving for T2:
T2
+ 2wz – Kp @N K
(9)
V
then by substituting for T2 in equation 7 and solving for T1 as given in equation 10:
T1
+ KNV@@wKp2 – 2wnz ) Kp @N K
n
ȱȧ
Ȳ
(10)
V
ȳȧ
ȴ
From the circuit constants and the initial design parameters then:
R1
+
R2
+
Kp
ƪ
@
@
wn2
2 z
N
*
wn ) Kp @ K
N
Kv
z
N
wn * Kp K
2
@
ƫ
V
1
C1
V
(11)
1
C1
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculated
values are listed in Table 9.
Table 9. Calculated Values
PARAMETER
SYMBOL
VALUE
ωn
45000
rad/sec
3.277
Mrad/sec
Natural angular frequency
K = (KV • Kp)/N
24
UNITS
Lag-lead filter
Calculated value
Nearest standard value
R1
15870
16000
Ω
Calculated value
Nearest standard value
R2
308
300
Ω
Selected value
C1
0.1
µF
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
The evaluation and operation schematic for the TLC2942I is shown in Figure 28.
AVDD
VDD
1
2
PLL1
VCO
LOGIC VDD (digital)
38
VCO VDD
SELECT
1/2 fosc
R1†
37
BIAS
0.22 µF
REF IN
DGND
3
VCO OUT
4
FIN – A
5
FIN – B
6
PFD OUT
VCOIN
VCO GND
R3
36
35
C2
R2
C1
VCOINHIBIT 34
AGND
7
Divide
By
N
Phase
Comparator
LOGIC GND (Digital)
PFD INHIBIT 33
GND
8
DGND
S1
PLL2
S2
S3
DGND
R4
R5
R6
DVDD
† RBIAS resistor
Figure 28. Evaluation and Operation Schematic
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
PCB layout considerations
The TLC2942I contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2942I user:
D
D
D
D
D
D
26
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / C 10/95
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
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