DATA SHEET MOS INTEGRATED CIRCUIT µPD16650 120-/128-OUTPUT TFT-LCD GATE DRIVER The µPD16650 is a TFT-LCD gate driver. Provided with a level shift circuit at the logic input, this chip can output a high gate scan voltage for a CMOS-level input. The µPD16650 has an output change-over function for switching from the 120-output mode to the 128-output mode, and vice versa, thereby supporting the VGA, SVGA, and XGA panels. Its output enable function (OE) enables installing the driver on either side. FEATURES • Output with high dielectric strength (on/off range: VDD - VEE1 = 40 VMAX.) • Built-in shift direction change-over function • Shiftable negative supply voltage (VEE1) level (shift range: |VEE1 - VEE2| = 10 V) • Two acceptable CMOS input levels (3.3 and 5 V) • Output enable function • MC-selectable output count (MC = high: 120-output mode) (MC = low : 128-output mode) • Slim TCP ORDERING INFORMATION Part number Package µPD16650N-××× TCP (TAB package) µPD16650N-××× Standard TCP (OL pitch = 220 µm) Remark When ordering, the customer can specify the external form of the TCP. Call one of our sales representatives for more information. Document No. S11041EJ1V0DS00 (1st edition) (Previous No. IP-3677) Date Published December 1995 P Printed in Japan © 1995 µPD16650 BLOCK DIAGRAM VCHA R/L LS φX LS STVR LS MC LS OE LS LS 128-bit shift register STVL VEE1 X1 X2 X127 Remark LS (level shifter): Interfaces the 5 V CMOS level with the VDD-VEE2 level. 2 X128 µPD16650 PIN CONNECTION DIAGRAM (µPD16650N-×××) X128 X127 X126 VDD X70 VCHA X69 VEE2 X68 STVL X67 OE X66 φX R/L X65 (Copper foil side) X64 VCC X63 MC X62 VSS X61 STVR X60 VEE2 X59 These pins are ineffective in the 120-output mode. VEE1 X3 X2 X1 Caution The VCHA pin should be connected to the VDD or VEE2 pin on the TCP. (This method eliminates the necessity to provide the VCHA input pin on the TCP, resulting in a reduction in the number of required input pins.) 3 µPD16650 PIN DESCRIPTION Pin name Pin symbol X1 to X128 Driver output Description of function Output scan signals to drive the TFT-LCD gate electrodes. The output changes when the shift clock φX rises. The amplitude of the driver output is VDD - VEE1. See the timing charts shown later for details of how to switch between the 120output mode and 128-output mode. MC Output count change-over Receives a signal that changes the number of outputs. For the 120-output input mode, this pin must be supplied with a high level (VCC). For the 128-output mode, it must be supplied with a low level (VSS or VEE2). VCHA STVR Logic voltage change-over Must be supplied with the VEE2 level when the logic supply voltage is 3.3 V, and input with the VDD level when the logic supply voltage is 5.0 V. Start pulse input/output Receives an input to the internal shift register. The input data is loaded on the shift register at the positive-going edge of the shift clock φX. The scan signals STVL are output from X1 to X128. The input/output level is the CMOS level. Outputs a start pulse to the next stage if a cascade connection is used. In the 120-output mode, the start pulse is output at the negative-going edge of the 120th shift clock φX pulse, and cleared at the negative-going edge of the 121st pulse. In the 128-output mode, the start pulse is output at the negative-going edge of the 128th shift clock φX pulse, and cleared at the negative-going edge of the 129th pulse. R/L φX Shift direction change-over R/L = high (for shift right): STVR → X1 → X128 → STVL input R/L = low (for shift left) Shift clock input Receives a shift clock pulse for the internal shift register. A shift occurs at the : STVL → X128 → X1 → STVR positive-going edge of the shift clock pulse. OE Output enable input When this pin is at a high level, the driver output is fixed at a low level. The shift register is not cleared, however. The internal logic circuit operates even when the pin is at a high level. The signal supplied to this pin is not synchronized with the clock. VDD Driver positive supply volt- Receives the supply voltage for both the logic circuit and driver. age VCC Reference voltage 5 ±0.5 V/3.3 ±0.3 V Reference voltage for the LS1 and LS2 level shifters. VSS Ground Must be connected to the system ground. VEE1 Driver negative supply volt- VEE1 (for the driver) age VEE2 Driver negative supply voltage 4 VEE2 (for the logic circuit) µPD16650 CAUTIONS FOR USE 1) Power-on sequence To prevent latch-up disruption, the power must be switched on in the order: VCC → VEE1 → VEE2 → VDD → Logic input When witching off, reverse the order. This order must be observed also during transition. 2) Insertion of bypass capacitors The internal logic circuit operates at a high voltage. To make VIH and VIL immune to noise, use capacitors of 0.1 µF or so between supply voltages as shown below. VDD VCC 0.1 µ F 0.1 µ F VSS 0.1 µ F VEE2 3) Negative voltage level shift If it is necessary to shift the level of a negative supply voltage, shift the VEE1 (driver supply voltage) level. The shift should be limited to within: VEE2 ≤ VEE1 ≤ VEE2 + 10 V Note that shifting the VEE1 level results in the ON-state output resistance and output fall time ratings being changed. 4) Handling the VEE1 and VEE2 driver negative supply voltage pins For applications in which a negative supply voltage level is not shifted, connect the VEE1 pin (driver supply voltage) to the VEE2 pin (logic supply voltage) outside the TCP. Fix all unused input pins to the VEE2 level. 5 µPD16650 TIMING CHART (MC = VSS, 128-OUTPUT MODE, AND R/L = VCC) φX 1 2 3 127 128 129 130 STVR (STVL) X1 X2 X3 X127 X128 STVL (STVR) X1 at the next stage X2 at the next stage Caution 6 Do not change all outputs simultaneously, because such a sequence may result in malfunction. µPD16650 TIMING CHART (MC = VCC, 120-OUTPUT MODE, AND R/L = VCC) 1 φX 2 3 119 120 121 122 STVR (STVL) X1 X2 X3 X127 X128 STVL (STVR) X1 at the next stage X2 at the next stage Cautions 1. Do not change all outputs simultaneously, because such a sequence may result in malfunction. 2. The output sequence in the 120-output mode is as follows: STVR (STVL) → X1 → X2 ... X60 → X69 ... X127 → X128 → STVL (STVR) 7 µPD16650 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS = 0 V) Parameter Symbol Conditions Rated value Unit V Supply voltage VDD –0.5 to +28 Supply voltage VCC –0.5 to +7 V Supply voltage VDD-VEE1 –0.5 to +42 V –22 to +0.5 V VDD-VEE2 Supply voltage VEE1, V EE2 Input voltage VI VEE2 – 0.5 to VDD2 + 0.5 V Input current II ±10 mA Output current IO ±10 mA Operating temperature range TA –20 to +85 °C Storage temperature range Tstg. –55 to +125 °C RECOMMENDED OPERATING RANGES (TA = –20 °C to +70 °C, VSS = 0 V) Parameter Symbol Conditions Min. Typ. Max. Unit Supply voltage VDD 16 25 V Supply voltage VEE1 VEE2 VEE2 + 10 V Supply voltage VEE2 –20 0 V Supply voltage VDD-VEE1 20 40 V VDD-VEE2 Supply voltage VCC For the 3.3 V logic input 3.0 3.3 3.6 V Supply voltage VCC For the 5.0 V logic input 4.5 5.0 5.5 V Remark When shifting the level of VEE1 (driver supply voltage), satisfy the condition: VEE2 ≤ VEE1 ≤ VEE2 + 10 V Note that shifting the VEE1 level results in the ON-state output resistance and output fall time ratings being changed. ELECTRICAL CHARACTERISTICS (TA = –20 °C to +70 °C, VDD = 20 V, VEE1 = VEE2 = –20 V, VCC = 3.3 ±0.3 V or 5.0 ±0.5 V, VSS = 0 V) Parameter Symbol Conditions Min. Typ. Max. Unit Input high voltage VIH Other than VCHA 0.7VCC VCC V Input low voltage VIL Other than VCHA VEE2 0.3VCC V Output high voltage VOH STVR(STVL), IOH = –40 µA VCC – 0.4 VCC V Output low voltage VOL STVR(STVL), IOL = 40 µA VSS VSS + 0.4 V Output high current IXOH Xn, VX = VDD – 1 V –1.5 mA Output low current IXOL Xn, VX = VEE1 + 1 V ON-state output resistance RON1 VX = VEE1 + 1 V or VDD – 1 V 660 Ω Input leakage current IIL V1 = 0 V, 5.0 V, or 3.3 V ±1.0 µA Dynamic drain current IDD VDD, fφX = 31.5 kHz 0.5 1.0 mA IEE VEE1/2, fφX = 31.5 kHz –0.5 –1.0 mA ICC VCC, fφX = 31.5 kHz 50 100 µA 8 mA 1.5 µPD16650 SWITCHING CHARACTERISTICS (TA = –20 °C to +70 °C, VDD = 20 V, VEE1 = VEE2 = –20 V, VSS = 0 V, VCC = 3.3 ±0.3 V or 5.0 ±0.5 V) Parameter STVR and STVL output delay Symbol Conditions Min. Typ. Max. Unit tPHL1 CL = 20 pF 600 ns tPLH1 CLK → STVR(STVL) 600 ns tPHL2 CL = 220 pF 700 ns tPLH2 CLK → Xn 700 ns td1 CL = 220 pF, OE: L → H 700 ns td2 CL = 220 pF, OE: H → L 700 ns Output rise time tTHL CL = 220 pF 300 ns Output fall time tTLH CL = 220 pF 300 ns Input capacitance CI TA = 25 °C 15 pF Maximum clock frequency f φX For cascade connection Driver output delay 100 kHz TIMING REQUIREMENTS (TA = –20 °C to +70 °C, VDD = 20 V, VEE1 = VEE2 = –20 V, VSS = 0 V, VCC = 3.3 ±0.3 V or 5.0 ±0.5 V) Parameter Symbol Conditions Min. Typ. Max. Unit Clock pulse high width PWφX(H) Duty = 50 % 500 ns Clock pulse low width PWφX(L) Duty = 50 % 500 ns Data setup time tsetup STVR(STVL) ↑ → CLK ↑ 100 ns Data hold time thold CLK ↑ → STVR(STVL) ↓ 100 ns Remark The logic input rise time (tr) and fall time (tf) must be within 20 ns (between 10 % and 90 % of the peak amplitude of the input). 9 µPD16650 SWITCHING CHARACTERISTIC WAVEFORM (R/L = HIGH) 1/f φ X PW φ X PWφ X VCC 50 % 50 % 50 % 50 % φx VSS thold tsetup VCC VSS tPLH2 tPHL2 90 % 90 % 50 % 50 % Xn 10 % 10 % tTLH tPLH1 tTHL tPHL1 VOH 50 % 50 % STVL (STVR) VOL VCC OE 50 % 50 % VSS td2 td1 Xn Xn 10 50 % 50 % µPD16650 RECOMMENDED MOUNTING CONDITIONS When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel. µPD16650N-××× Mounting Condition Thermocompression Caution Mounting Method Condition Soldering Heating tool 300 to 350 ˚C; heating for 2 to 3 seconds; pressure 100 g (per solder) ACF (Sheet-shape bonding agent) Temporary bonding 70 to 100 ˚C; pressure 3 to 8 kg/cm 2; time 3 to 5 secs. Real bonding 165 to 180 ˚C; pressure 25 to 45 kg/cm 2; time 30 to 40 secs. (when using the anisotropic conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Reference NEC Semiconductor Device Reliability/Quality Control System (IEI-1212) Quality Grades to NEC’s Semiconductor Devices (IEI-1209) 11 µPD16650 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11