LH5164AZ8 CMOS 64K (8K × 8) Static RAM FEATURES DESCRIPTION • 8,192 × 8 bit organization The LH5164AZ8 is a static RAM organized as 8,192 × 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 200 ns (VCC = 3.0 V MAX.) • Power consumption: Operating: 60 mW (MAX.) @ 3 V Standby (to 60°C): 3 µW (MAX.) @ 3 V Data hold 0.6 µA (VCC = 3 V, TA = 60°C) • Operating voltage range: 3.0 V to 3.6 V • Wide operating temperature range: -30 to 60°C • Fully-static operation • TTL compatible I/O • Three-state outputs • Package: 28-pin, 450-mil SOP PIN CONNECTIONS 28-PIN SOP TOP VIEW NC 1 28 VCC A12 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE1 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 5164AZ8-1 Figure 1. Pin Connections for SOP Package 1 CMOS 64K (8K × 8) Static RAM LH5164AZ8 A6 4 A5 5 A4 6 ROW SELECT ROW ADDRESS BUFFERS A9 24 A8 25 A12 2 A7 3 28 VCC MEMORY ARRAY (256 x 256) 14 GND A3 7 I/O1 11 I/O2 12 I/O3 13 I/O4 15 COLUMN I/O CIRCUITS INPUT DATA CONTROL I/O5 16 I/O6 17 I/O7 18 I/O8 19 COLUMN SELECT COLUMN ADDRESS BUFFERS WE 27 OE 22 CE2 26 CE1 20 8 A2 9 A1 10 A0 23 A11 21 A10 5164AZ8-2 Figure 2. LH5164AZ8 Block Diagram PIN DESCRIPTION SIGNAL A0 - A12 2 PIN NAME Address inputs SIGNAL I/O1 - I/O8 PIN NAME Data inputs and outputs CE1 - CE2 Chip Enable input VCC Power supply WE Write Enable input GND Ground OE Output Enable input NC Non connection CMOS 64K (8K × 8) Static RAM LH5164AZ8 TRUTH TABLE CE1 CE2 WE OE MODE I/O 1 - I/O8 SUPPLY CURRENT NOTE H X X L X X X X Standby Standby High-Z High-Z Standby (ISB ) Standby (ISB ) 1 1 L L H H L H X L Write Read DIN DOUT Operating (ICC) Operating (ICC) 1 L H H H Output deselect High-Z Operating (ICC) NOTE: 1. X = H or L ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage VCC -0.3 to +7.0 V 1 Input voltage VIN -0.3 to VCC + 0.3 V 1 Operating temperature Topr -30 to +60 °C Storage temperature Tstg -65 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = -30 to +60°C) PARAMETER Supply voltage Input voltage (VCC = 3.0 to 3.6 V) SYMBOL MIN. VCC VIH VIL TYP. MAX. UNIT 3.0 VCC - 0.5 3.6 VCC + 0.3 V V -0.3 0.2 V DC CHARACTERISTICS (TA = -30 to +60°C, VCC = 3.0 to 3.6 V) ADD TABLE NOTE: 1. CE2 should be ≥ VCC - 0.2 V or ≤ 0.2 V. 3 CMOS 64K (8K × 8) Static RAM LH5164AZ8 AC CHARACTERISTICS (1) READ CYCLE (TA = -30 to +60°C, VCC = 3.0 to 3.6 V) PARAMETER SYMBOL MIN. Read cycle tRC 200 Address access time tAA 200 ns (CE1) tACE1 200 ns (CE2) tACE2 200 ns tOE 150 ns Chip enable access time Output enable access time Output hold time Chip enable to output in Low-Z UNIT ns tOH 10 ns (CE1) tLZ1 20 ns (CE2) tLZ2 20 ns tOLZ 10 tHZ1 0 60 ns tHZ2 0 60 ns tOHZ 0 40 ns Output enable to output in Low-Z Chip enable to output in High-Z MAX. (CE1) (CE2) Output disable to output in High-Z ns (2) WRITE CYCLE (TA = -30 to +60°C, VCC = 3.0 to 3.6 V) PARAMETER SYMBOL MIN. MAX. UNIT Write cycle time tWC 200 ns Chip enable to end of write tCW 180 ns Address valid to end of write tAW 180 ns Address setup time tAS 0 ns Write pulse width tWP 150 ns Write recovery time tWR 0 ns Data valid to end of write tDW 100 ns Data hold time tDH 0 ns Output active from end of write tOW 20 ns WE to output in High-Z tWZ 0 60 ns OE to output in High-Z tOHZ 0 40 ns AC TEST CONDITIONS PARAMETER Input voltage amplitude Input rise/fall time MODE 0 to VCC 10 ns Timing reference level 1.5 V Output load conditions No load CAPACITANCE (TA = 25°C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS TYP. MAX. UNIT Input capacitance CIN VIN = 0 V 7 pF Input/output capacitance CI/O VI/O = 0 V 10 pF NOTE: This parameter is sampled and not production tested. 4 MIN. CMOS 64K (8K × 8) Static RAM LH5164AZ8 DATA RETENTION CHARACTERISTICS (TA = -30 to +60°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Data retention supply voltage VCCDR CE2 ≤ 0.2 V or CE1 ≥ VCCDR – 0.2 V 2.0 5.5 V 1 Data retention supply current ICCDR Chip disable to data retention Recovery time VCCDR = 3.0 V, CE2 ≤ 0.2 V or CE1 ≥ VCCDR – 0.2 V TA = 25°C 0.2 TA = 60°C 0.6 µA tCDR 0 ns tR tRC ns 1 2 NOTES: 1. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V. 2. t RC = Read cycle time tRC ADDRESS tAA tACE1 CE1 tLZ1 tHZ1 tACE2 CE2 tHZ2 tLZ2 tOE tOLZ OE tOHZ tOH DOUT DATA VALID NOTE: WE is "HIGH" level during the read cycle. 5164AZ8-3 Figure 3. Read Cycle 5 CMOS 64K (8K × 8) Static RAM LH5164AZ8 tWC ADDRESS OE tAW tWR tCW (NOTE 2) (NOTE 4) CE1 tWR tCW CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE tOHZ DOUT tDW DIN (NOTE 5) tDH DATA VALID NOTES: 1. The writing occurs during an overlapping period of CE1 = "LOW," CE2 = "HIGH," and WE = "LOW" (tWP). 2. tCW is defined as the time from the last occuring transit, either CE1 LOW transit or CE2 HIGH transit, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. The input signals of opposite phase to the outputs must not be applied while I/O pins are in the output state. Figure 4. Write Cycle 6 5164AZ8-4 CMOS 64K (8K × 8) Static RAM LH5164AZ8 tWC ADDRESS tAW tWR tCW (NOTE 4) (NOTE 2) CE1 tWR tCW CE2 tAS tWP (NOTE 3) (NOTE 1) tWR WE tWZ tOW (NOTE 7) (NOTE 6) DOUT tDW tDH (NOTE 5) DIN DATA VALID NOTES: 1. The writing occurs during an overlapping period of CE1 = "LOW," CE2 = "HIGH," and WE = "LOW" (tWP). 2. tCW is defined as the time from the last occuring transit, either CE1 LOW transit or CE2 HIGH transit, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. The input signals of opposite phase to the outputs must not be applied while I/O pins are in the output state. 6. If CE1 LOW transit or CE2 HIGH transit occurs at the same time or after WE LOW transit, the output will remain high-impedance. 7. If CE1 HIGH transit or CE2 LOW transit occurs at the same time or before WE HIGH transit, the output will remain high-impedance. 5164AZ8-5 Figure 5. OE Low Fixed 7 CMOS 64K (8K × 8) Static RAM LH5164AZ8 DATA HOLD MODE CE1 CONTROL (NOTE) VCC 2.5 V tCDR tRDR VCC - 0.2 V VCCDR CE1 ≥ VCCDR - 0.2 V CE1 0V CE2 CONTROL DATA HOLD MODE VCC 2.5 V tCDR CE2 tRDR VCCDR 0.2 V 0V CE2 ≥ 0.2 V NOTE: To control the data hold mode at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V during the data hold mode. Figure 6. Low Voltage Data Retention 8 5164AZ8-6 CMOS 64K (8K × 8) Static RAM LH5164AZ8 PACKAGE DIAGRAM 28SOP (SOP028-P-0450) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 1.70 [0.067] 28 15 8.80 [0.346] 8.40 [0.331] 1 12.40 [0.488] 11.60 [0.457] 10.60 [0.417] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP ORDERING INFORMATION LH5164AZ8 Device Type CMOS 64K (8K x 8) Static RAM Example: LH5164AZ8 (CMOS 64K (8K x 8) Static RAM, 200 ns, 28-pin, 450-mil SOP) 5164AZ8-7 9