LH5268A CMOS 64K (8K × 8) Static RAM FEATURES DESCRIPTION • 8,192 × 8 bit organization The LH5268A is a static RAM organized as 8,192 × 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 100 ns (MAX.) • Power consumption: Operating: 220 mW (MAX.) 55 mW (MAX.) (tRC, tWC = 1 µs) Standby: 220 µW (MAX.) Data retention: 3.0 µW (VCC = 3 V, TA = 25°C) • Fully-static operation PIN CONNECTIONS 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP TOP VIEW NC 1 28 VCC A12 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 • Three-state outputs A3 7 22 OE A2 8 21 A10 • Single +5 V power supply A1 9 20 CE1 A0 10 19 I/O8 • TTL compatible I/O • Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 5268A-1 Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages 1 CMOS 64K (8K × 8) Static RAM ROW ADDRESS BUFFER A12 2 A8 25 A7 3 A6 4 A5 5 A4 6 A3 7 I/O1 I/O2 I/O3 I/O4 ROW DECODERS LH5268A 28 VCC MEMORY ARRAY (128 x 512) 14 GND 11 12 13 15 I/O CIRCUITS DATA CONTROL I/O5 16 I/O6 17 I/O7 18 I/O8 19 COLUMN DECODER COLUMN ADDRESS BUFFER WE 27 OE 22 CE2 26 CE1 20 23 24 21 8 10 9 A11A9 A10 A2 A0 A1 5268A-2 Figure 2. LH5268A Block Diagram PIN DESCRIPTION SIGNAL A0 - A12 2 PIN NAME Address inputs SIGNAL I/O1 - I/O8 PIN NAME Data inputs and outputs CE1 - CE2 Chip Enable input VCC Power supply WE Write Enable input GND Ground OE Output Enable input NC No connection CMOS 64K (8K × 8) Static RAM LH5268A TRUTH TABLE CE1 CE2 WE OE MODE I/O 1 - I/O 8 SUPPLY CURRENT NOTE H X X X Deselect High-Z Standby (ISB) 1 X L X X Deselect High-Z Standby (ISB) 1 1 L H L X Write DIN Operating (ICC) L H H L Read DOUT Operating (ICC) L H H H Output disable High-Z Operating (ICC) NOTE: 1. X = H or L ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage VCC -0.3 to +7.0 V 1 Input voltage VIN -0.3 to V CC + 0.3 V 1,2 Operating temperature Topr 0 to +70 °C Storage temperature Tstg -65 to +150 °C NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER Supply voltage SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Input voltage VIH 2.2 VCC + 0.3 V VIL -0.3 0.8 V NOTE 1 NOTE: 1. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5 V ±10%) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT Input leakage current ILI VIN = 0 to VCC -1 1 µA Output leakage current ILO CE 1 = VIH or CE2 = VIL or OE = VIH or WE = V IL VI/O = 0 V to VCC -1 1 µA Operating current Standby current Output voltage ICC CE1 = VIL, VIN = VIL or VIH CE2 = VIH, II/O = 0 mA tCYCLE = 100 ns CE1 = 0.2 V, VIN = 0.2 V or VCC - 0.2 V CE2 = VCC - 0.2 V, II/O = 0 mA tCYCLE = 1.0 µs 40 mA 10 ISB1 CE1 = VIH or CE2 = VIL 3 mA ISB CE2 ≤ 0.2 V or CE1 ≥ VCC - 0.2 V 40 µA VOL VOH IOL = 2.1 mA IOH = -1.0 mA NOTE 0.4 2.4 1 V V NOTE: 1. CE2 should be ≥ VCC - 0.2 V or ≤ 0.2 V when CE1 ≥ VCC - 0.2 V. 3 CMOS 64K (8K × 8) Static RAM LH5268A AC CHARACTERISTICS (1) READ CYCLE (TA = 0 to +70°C, VCC = 5 V ±10%) PARAMETER SYMBOL MIN. tRC 100 Read cycle time Address access time Chip enable access time MAX. UNIT NOTE ns tAA 100 ns (CE1) tACE1 100 ns (CE2) tACE2 100 ns Output enable access time tOE 40 ns Output hold time tOH 10 ns (CE1) tLZ1 10 ns 1 (CE2) tLZ2 10 ns 1 tOLZ 5 ns 1 (CE1) tHZ1 0 30 ns 1 (CE2) tHZ2 0 30 ns 1 tOHZ 0 20 ns 1 Chip enable to output in Low-Z Output enable to output in Low-Z Chip enable to output in High-Z Output disable to output in High-Z NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. (2) WRITE CYCLE (TA = 0 to +70°C, VCC = 5 V ±10%) PARAMETER SYMBOL MIN. MAX. UNIT Write cycle time tWC 100 ns Chip enable to end of write tCW 80 ns Address valid to end of write tAW 80 ns Address setup time tAS 0 ns Write pulse width tWP 60 ns Write recovery time tWR 0 ns Data valid to end of write tDW 40 ns NOTE Data hold time tDH 0 ns Output active from end of write tOW 10 ns 1 WE to output in High-Z tWZ 0 30 ns 1 OE to output in High-Z tOHZ 0 20 ns 1 NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER MODE Input voltage amplitude 0.6 to 2.4 V Input rise/fall time 10 ns Timing reference level 1.5 V Output load conditions 1TTL + CL (100 pF) NOTE: 1. Includes scope and jig capacitance. 4 NOTE 1 CMOS 64K (8K × 8) Static RAM LH5268A CAPACITANCE 1 (TA = 25°C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS Input capacitance CIN Input/output capacitance CI/O MIN. TYP. MAX. UNIT VIN = 0 V 7 pF VI/O = 0 V 10 pF NOTE: 1. This parameter is sampled and not production tested. DATA RETENTION CHARACTERISTICS (TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Data retention voltage VCCDR CE2 ≤ 0.2 V or CE1 ≥ VCCDR - 0.2 V 2.0 5.5 V 1 Data retention current ICCDR 1 µA 20 µA VCCDR = 3 V, CE2 ≤ 0.2 V or CE1 ≥ VCCDR - 0.2 V TA = 25°C Chip disable to data retention tCDR 0 ns Recovery time tR tRC ns 1 2 NOTES: 1. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR - 0.2 V 2. t RC = Read cycle time DATA RETENTION MODE CE1 CONTROL (NOTE) VCC 4.5 V tCDR tR 2.2 V VCCDR CE1 ≥ VCCDR - 0.2 V CE1 0V CE2 CONTROL DATA RETENTION MODE VCC 4.5 V tCDR CE2 tR VCCDR 0.8 V 0V CE2 ≥ 0.2 V NOTE: To control the data retention mode at CE1, fix the input level of CE2 between VCCDR and VCCDR - 0.2 V or 0 V to 0.2 V during the data retention mode. 5268A-6 Figure 3. Low Voltage Data Retention 5 CMOS 64K (8K × 8) Static RAM LH5268A tRC A0 - A12 tAA tACE1 CE1 tLZ1 tHZ1 tACE2 CE2 tHZ2 tLZ2 tOE tOLZ OE tOHZ tOH DOUT DATA VALID NOTE: WE = 'HIGH.' 5268A-3 Figure 4. Read Cycle 6 CMOS 64K (8K × 8) Static RAM LH5268A tWC A0 - A12 OE tAW tWR tCW (NOTE 2) (NOTE 4) CE1 tWR tCW CE2 tAS tWR tWP (NOTE 1) (NOTE 3) WE tOHZ DOUT tDW tDH DATA VALID DIN NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5268A-4 Figure 5. Write Cycle 1 7 CMOS 64K (8K × 8) Static RAM LH5268A tWC A0 - A12 tAW tWR (NOTE 4) tCW (NOTE 2) CE1 tWR tCW CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE (NOTE 6) tWZ tOW (NOTE 7) DOUT tDW DIN tDH DATA VALID (NOTE 5) NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. When I/O pins are in the output state, input signals with the opposite logic level must not be applied. 6. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 7. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the outputs will remain high-impedance. 5268A-5 Figure 6. Write Cycle 2 8 CMOS 64K (8K × 8) Static RAM LH5268A PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 14 0.30 [0.012] 0.20 [0.008] 36.30 [1.429] 35.70 [1.406] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.60 [0.024] 0.40 [0.016] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.51 [0.020] MIN. MAXIMUM LIMIT MINIMUM LIMIT 28DIP-2 28-pin, 600-mil DIP 28DIP (DIP028-P-0300) DETAIL 28 15 7.05 [0.278] 6.65 [0.262] 1 0° TO 15° 14 0.35 [0.014] 0.15 [0.006] 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] TYP. 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.51 [0.02] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 28DIP-6 28-pin, 300-mil DIP 9 CMOS 64K (8K × 8) Static RAM LH5268A 28SOP (SOP028-P-0450) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.70 [0.067] 28 15 8.80 [0.346] 8.40 [0.331] 1 12.40 [0.488] 11.60 [0.457] 10.60 [0.417] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP ORDERING INFORMATION LH5268A Device Type X Package - ## Speed LL Power Low-Low-power standby 10 100 Access Time (ns) Blank 28 pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil DIP (DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) CMOS 64K (8K x 8) Static RAM Example: LH5268AD-10LL (CMOS 64K (8K x 8) Static RAM, Low-Low-power standby, 100 ns, 28-pin, 300-mil DIP)) 5268A-7 10