LH534B00 FEATURES CMOS 4M (512K × 8) MROM PIN CONNECTIONS • 524,288 words × 8 bit organization • Access time: 120 ns (MAX.) • Power consumption: Operating: 330 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Package: 40-pin, 10 × 20 mm2 TSOP (Type I) 40-PIN TSOP (Type I) TOP VIEW A16 1 40 A17 A15 2 39 GND A14 3 38 NC A13 4 37 NC A12 5 36 A10 A11 6 35 D7 A9 7 34 D6 A8 8 33 D5 NC 9 32 D4 NC 10 31 VCC NC 11 30 VCC NC 12 29 NC A18 13 28 D3 A7 14 27 D2 DESCRIPTION A6 15 26 D1 The LH534B00 is a 4M-bit mask-programmable ROM organized as 524,288 × 8 bits. It is fabricated using silicon-gate CMOS process technology. A5 16 25 D0 A4 17 24 OE A3 18 23 GND A2 19 22 CE A1 20 21 A0 534B00-1 Figure 1. Pin Connections for TSOP Package 1 LH534B00 CMOS 4M MROM A18 13 A17 40 1 2 3 4 ADDRESS BUFFER A12 5 A11 6 A10 36 A9 A8 A7 A6 7 8 14 15 MEMORY MATRIX (524,288 x 8) ADDRESS DECODER A16 A15 A14 A13 A5 16 A4 17 A3 18 A2 19 A1 20 COLUMN SELECTOR A0 21 SENSE AMPLIFIER CE BUFFER CE 22 TIMING GENERATOR OUTPUT BUFFER OE BUFFER OE 24 30 31 VCC 23 39 GND 25 D0 26 D1 27 D2 28 D3 32 D4 33 D5 34 D6 35 D7 534B00-2 Figure 2. LH534B00 Block Diagram PIN DESCRIPTION SIGNAL 2 PIN NAME SIGNAL PIN NAME A0 – A18 Address input VCC Power supply (+5 V) D0 – D7 Data output GND Ground CE Chip enable input OE Output enable input NC No connection CMOS 4M MROM LH534B00 TRUTH TABLE CE OE DATA OUTPUT SUPPLY CURRENT H X High-Z Standby H High-Z Operating L Output Operating L NOTE: X = H or L, High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC – 0.3 to +7.0 V Input voltage VIN – 0.3 to V CC + 0.3 V Output voltage VOUT – 0.3 to V CC + 0.3 V Operating temperature Topr –20 to +70 °C Storage temperature Tstg –65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = –20°C to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V ±10%, TA = –20°C to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage VIH 2.2 VCC + 0.3 V Input ‘Low’ voltage VIL – 0.3 0.8 V Output ‘High’ voltage VOH IOH = – 400 µA Output ‘Low’ voltage VOL IOL = 2.0 mA 0.4 V Input leakage current | ILl | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 tRC = 120 ns 60 mA 2 ICC2 tRC = 1 µs 50 mA 2 ICC3 tRC = 120 ns 55 mA 3 ICC4 tRC = 1 µs 45 mA 3 ISB1 CE = V IH 3 mA ISB2 CE = V CC – 0.2 V 100 µA CIN f = 1 MHz TA = 25°C 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance COUT 2.4 V NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open 3 LH534B00 CMOS 4M MROM AC CHARACTERISTICS (VCC = 5 V ±10%, TA = –20°C to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT Read cycle time tRC 120 Address access time tAA 120 ns Chip enable access time tACE 120 ns Output enable delay time tOE 60 ns Output hold time tOH CE to output in High-Z tCHZ OE to output in High-Z tOHZ NOTE ns 0 ns 60 ns 1 NOTE: 1. This is the time required for the outputs to become high-impedance. AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude 0.4 to 2.6 V Input rise/fall time 10 ns Input/output reference level 1.5 V Output load condition 1 TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. tRC A0 - A18 tAA (NOTE) CE tACE tCHZ (NOTE) OE tOHZ tOE (NOTE) D 0 - D7 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. Figure 3. Timing Diagram 4 534B00-3 CMOS 4M MROM LH534B00 PACKAGE DIAGRAM 40TSOP (TSOP040-P-1020) 40 1 0.50 [0.020] TYP. 10.20 [0.402] 9.80 [0.386] 0.25 [0.010] 0.15 [0.006] 20 21 1.10 [0.043] 0.90 [0.035] SEE DETAIL 1.19 [0.047] MAX. 0.49 [0.019] 0.39 [0.015] DETAIL 0.125 [0.005] 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] DIMENSIONS IN MM [INCHES] 0 - 10° 0.49 [0.019] 0.39 [0.015] 20.30 [0.799] 19.70 [0.776] 0.22 [0.009] 0.02 [0.001] MAXIMUM LIMIT MINIMUM LIMIT 0.18 [0.007] 0.08 [0.003] 40TSOP 40-pin, 10 × 20 mm2 TSOP (Type I) ORDERING INFORMATION LH534B00 Device Type T Package 40-pin, 10 x 12 mm2 TSOP (Type I) (TSOP040-P-1020) CMOS 4M (512K x 8) Mask-Programmable ROM Example: LH534B00T (CMOS 4M (512K x 8) Mask-Programmable ROM, 40-pin, 10 x 12 mm2 TSOP (Type I)) 534B00-4 5