SHARP LH28F040SUTD-Z4

LH28F040SUTD-Z4
FEATURES
• 512K × 8 Bit Configuration
• 5 V Write/Erase Operation (5 V VPP, 3.3 VCC)
– VCC for Write/Erase at as low as 2.9 V
• Min. 2.7 V Read Capability
– 190 ns Maximum Access Time
(VCC = 2.7 V)
• 2 Banks Enable the Simultaneous
Read/Write/Erase Operation
• 32 Independently Lockable Blocks (16K)
• 100,000 Erase Cycles per Block
• Automated Byte Write/Block Erase
– Command User Interface
– Status Register
• System Performance Enhancement
– Erase Suspend for Read
– Two-Byte Write
– Bank Erase
4M (512K × 8) Flash Memory
40-PIN TSOP
TOP VIEW
NC1
1
40
NC
NC1
2
39
OE
A11
3
38
NC
A9
4
37
A10
A8
5
36
BE1
A13
6
35
BE0
A14
7
34
DQ7
8
33
DQ6
WE
9
32
DQ5
VCC
10
31
DQ4
VPP
11
30
DQ3
A16
12
29
GND
A15
13
28
DQ2
A12
14
27
DQ1
A7
15
26
DQ0
A6
16
25
A0
A17
A5
17
24
A1
A4
18
23
A2
NC2
19
22
A3
NC2
20
21
NC
• Data Protection
– Hardware Erase/Write Lockout during
Power Transitions
– Software Erase/Write Lockout
28F040SUZ4-1
Figure 1. TSOP Configuration
• Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
• 20 µA (Maximum) ICC in CMOS Standby
• State-of-the-Art 0.55 µm ETOX™
Flash Technology
• 40-Pin, 1.2 mm × 10 mm × 20 mm TSOP
(Type I) Package
1
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
Bank1
Bank0
DQ0 - DQ7
OUTPUT
BUFFER
INPUT
BUFFER
DATA
QUEUE
REGISTER
ID
REGISTER
I/O
LOGIC
CSR
OUTPUT
MULTIPLEXER
REGISTER
BE1
BE0
OE
CUI
WE
DATA
COMPARATOR
ADDRESS
COUNTER
16KB BLOCK 15
...
16KB BLOCK 14
X-DECODER
16KB BLOCK 1
ADDRESS
QUEUE
LATCH
Y GATING/SENSING
Y-DECODER
16KB BLOCK 0
INPUT
BUFFER
...
A0 - A17
...
WSM
PROGRAM/
ERASE
VOLTAGE
SWITCH
VPP
VCC
GND
28F040SUZ4-2
Figure 2. LH28F040SUTD-Z4 Block Diagram
2
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A0 - A13
INPUT
BYTE-SELECT ADDRESSES: Select a byte within one 16K block. These addresses
are latched during Data Writes.
A14 - A17
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 16K Erase blocks. These addresses
are latched during Data Writes, Erase and Lock-Block operations.
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.
BE »0, BE »1
INPUT
BANK ENABLE INPUTS: Activate the device's control logic, input buffers, decoders
and sense amplifiers. CE » must be low to select the device. When BE »0 is low,
bank0 is active. When BE »1 is low, bank1 is active. Both BE »0 and BE »1 must not be
low at the same time.
OE »
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE » is high.
WE
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
VPP
SUPPLY
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks
or writing bytes into the flash array.
VCC
SUPPLY
DEVICE POWER SUPPLY (3.3 V ±0.3 V): Do not leave any power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
DQ0 - DQ7
NC
NC1, NC2
NO CONNECTION
OPEN PIN: But NC1 (between pin1 and pin2) and also NC2 (pin19 and pin20) are
connected inside package.
INTRODUCTION
Sharp’s LH28F040SUTD-Z4 4M Flash Memory is a
revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and
communication products. With innovative capabilities,
3.3 V low power operation and very high read/write performance, the LH28040SU-Z4 is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F040SUTD-Z4 is a very high density, highest performance non-volatile read/write solution for solidstate storage applications. Its independently lockable
32 symmetrical blocked architecture (16K each)
extended cycling, low power operation, very fast write
and read performance and selective block locking provide a highly flexible memory component suitable for
high density memory cards, Resident Flash Arrays and
PCMCIA-ATA Flash Drives. The LH28F040SUTD-Z4’s
5.0 V/3.3 V power supply operation enables the design
of memory cards which can be read in 3.3 V system
and written in 5.0 V/3.3 V systems. Its x8 architecture
allows the optimization of memory to processor interface. The flexible block locking option enables bundling
of executable application software in a Resident Flash
Array or memory card. Manufactured on Sharp’s 0.55
µm ETOX™ process technology, the LH28F040SUTDZ4 is the most cost-effective, high-density 3.3 V flash
memory.
LH28F040SUTD-Z4 divides 4M into two areas. Each
area can read/write/erase independently. For example,
while you write and erase on one area, you can simultaneously read the data from the other area. This
enables users to reduce the number of components in
their system.
3
LH28F040SUTD-Z4
DESCRIPTION
The LH28F040SUTD-Z4 is a high performance 4M
(4,194,304 bit) block erasable non-volatile random
access memory organized as 256K × 8 × 2 banks. The
LH28F040SUTD-Z4 includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 3.
The two banks, the one selected by BE 0» (bank0) and
the other selected by BE »1 (bank1) can be controlled
independently. For example, while erase the data in
bank0, the data in bank1 can be read out.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F040SUTD-Z4:
• 3 V Read, 5 V Write/Erase Operation
(5 V VPP, 3 V VCC)
• Low Power Capability (2.7 V VCC Read)
• Improved Write/Erase Performance
(Two-Byte Serial Write, Bank Erase)
• Dedicated Block Write/Erase Protection
• Command-Controlled Memory Protection
Set/Reset Capability
The LH28F040SUTD-Z4 will be available in a 40-pin,
1.2 mm thick × 10 mm × 20 mm TSOP (Type I) package. This form factor and pinout allow for very high board
layout densities.
A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a TwoWrite command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
•
•
•
•
Software Locking of Memory Blocks
Memory Protection Set/Reset Capability
Two-Byte Serial Writes in 8-bit Systems
Bank Erase All Unlocked Blocks
Writing of memory data is performed typically within
20 µs. A Block Erase operation erases one of the 32
blocks in typically 1.5 seconds, independent of the other
blocks.
4
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4 allows to erase all unlocked
blocks for each bank selected by BE »0 or BE »1. It is desirable in case of which you have to implement Erase
operation maximum 32 times.
LH28F040SUTD-Z4 enables Two-Byte serial Write
which is operated by three times command input. This
feature can improve system write performance by up to
typically 17 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) provide information on the progress of the
requested operation.
Same as the LH28F008SA, LH28F040SUTD-Z4
requires an operation to complete before the next operation can be requested, also it allows to suspend block
erase to read data from any other block, and allow to
resume erase operation.
The LH28F040SUTD-Z4 provides user-selectable
block locking to protect code or data such as Device
Drivers, PCMCIA card information, ROM-Executable OS
or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the
block. In addition, the LH28F040SUTD-Z4 has a software controlled master Write Protect circuit which prevents any modifications to memory blocks whose lockbits are set.
When the device power-up, Write Protect Set/
Confirm command must be written both in bank0 and
bank1. Otherwise, all lock bits in the device remain
being locked, can’t perform the Write to each block and
single Block Erase. Write Protect Set/Confirm command
must be written to reflect the actual lock status. However, when the device power-on, Erase All Unlocked
Blocks can be used. If used, Erase is performed with
reflecting actual lock status, and after that Write and
Block Erase can be used.
The LH28F040SUTD-Z4 contains Status Register to
accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capability to the LH28F040SUTD-Z4 from a LH28F008SA
based design.
The LH28F040SUTD-Z4 is specified for a maximum
access time of 150 ns (tACC) at 3.3 V operation (3.0 to
3.6 V) over the commercial temperature range (-20 to
+70°C). A corresponding maximum access time of
190 ns (tACC) at 2.7 V (-20 to +70°C) is achieved for
reduced power consumption applications.
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
The LH28F040SUTD-Z4 incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
A CMOS Standby mode of operation is enabled when
BE X
» transitions high with all input control pins at CMOS
levels. In this mode, the device draws an ICC standby
current of 20 µA.
In APS mode, the typical ICC current is 2 mA at 3.3 V.
Please do not execute reprogramming 0 for the bit
which has already been programmed 0. Overwrite operation may generate unerasable bit. In case of reprogramming 0 to the data which has been programmed 1.
A bank reset mode of operation is enabled when
whole BE »0 (or BE »1), WE » and OE » hold low more than 5
µs. In this mode, all operations are aborted, the internal
control circuit is reset and CSR register is cleared. When
the device power up, this bank reset operation must be
executed for each bank to initialize the control circuit. If
BE »X (either BE »0 or BE »1 which is in low state) and or
WE » and or OE » and or goes high, chip reset mode will
be finished. It needs more than 750 ns from one of the
BE »X, WE » or OE » goes high until output data are valid. It
is impossible to reset the whole chip at once, the bank
reset must be executed separately for bank0 and bank1.
• Program 0 for the bit in which you want to change
data from 1 to 0.
• Program 1 for the bit which has already been programmed 0.
For example, changing data from 10111101 to
10111100 requires 11111110 programming.
MEMORY MAP
Bank0 (BE0 = Low)
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
Bank1 (BE1 = Low)
16KB BLOCK
15
16KB BLOCK
14
16KB BLOCK
13
16KB BLOCK
12
16KB BLOCK
11
16KB BLOCK
10
16KB BLOCK
9
16KB BLOCK
8
16KB BLOCK
7
16KB BLOCK
6
16KB BLOCK
5
16KB BLOCK
4
16KB BLOCK
3
16KB BLOCK
2
16KB BLOCK
1
16KB BLOCK
0
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
16KB BLOCK
15
16KB BLOCK
14
16KB BLOCK
13
16KB BLOCK
12
16KB BLOCK
11
16KB BLOCK
10
16KB BLOCK
9
16KB BLOCK
8
16KB BLOCK
7
16KB BLOCK
6
16KB BLOCK
5
16KB BLOCK
4
16KB BLOCK
3
16KB BLOCK
2
16KB BLOCK
1
16KB BLOCK
0
28F040SUZ4-3
Figure 3. Memory Map
5
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations
OE »
WE
A0
DQ0 - DQ7
NOTE
VIL
VIH
X
DOUT
1
X
VIH
VIH
X
High-Z
1
VIH
VIH
X
X
X
High-Z
1
Bank 0
VI L
VIH
VIL
VIH
VIL
2
VIH
VIL
B0H
Bank 1
Bank 0
VI L
VIH
VIL
VIH
VIH
2
VIH
VIL
31H
Bank 1
Bank 0
VI L
VIH
VIL
VIL
DIN
1, 3
VIH
VIH
X
Bank1
BE »0
BE »1
Bank 0
VI L
VIH
Bank 1
VIH
VIL
X
MODE
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
NOTES:
1. X can be VIH or VIL for address or control pins, which is either VOL or VOH.
2. A0 at VIL provide manufacturer ID codes. A0 at VIH provide device ID codes.
All other addresses are set to zero.
3. Commands for different Erase operations, Data Write operations, and Lock-Block operations can only
be successfully completed when VPP = VPPH.
4. Both BE »0 and BE »1 must not be low at the same time.
6
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
LH28F008SA-Compatible Mode Command Bus Definitions
Following is the commands to be applied to each bank.
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
NOTE
OPER.
ADDRESS
DATA
OPER.
ADDRESS
DATA
Read Array
Write
X
FFH
Read
AA
AD
Intelligent Identifier
Write
X
90H
Read
IA
ID
1
Read Compatible Status Register
Write
X
70H
Read
X
CSRD
2
Clear Status Register
Write
X
50H
Byte Write
Write
X
40H
Write
WA
WD
Alternate Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
4
Erase Suspend/Resume
Write
X
B0H
Write
X
D0H
4
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
3
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions.
4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase complete.
7
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4 Performance Enhancement Command Bus Definitions
Following is the commands to be applied to each bank.
FIRST BUS CYCLE
COMMAND
SECOND BUS CYCLE
OPER. ADD. DATA OPER. ADD.
THIRD BUS CYCLE
DATA
OPER. ADD.
NOTE
DATA
Protect Set/Confirm
Write
X
57H
Write
0FFH
D0H
1, 2, 6
Protect Reset/Confirm
Write
X
47H
Write
0FFH
D0H
3, 6
Lock Block/Confirm
Write
X
77H
Write
BA
D0H
1, 2, 4
Bank Erase All Unlocked Blocks Write
X
A7H
Write
X
D0H
1, 2
Two-Byte Write
X
FBH
Write
A10
WD (L, H)
Write
ADDRESS
BA = Block Address
WA = Write Address
X = Don’t Care
Write
WA
WD (H, L) 1, 2, 5
DATA
AD = Array Data
WD (L, H) = Write Data (Low, High)
WD (H, L) = Write Data (High, Low)
NOTES:
1. After initial device power-up, or reset is completed, the block lock status bit default to the locked state independent of the data in the
corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.
2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.
3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.
4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.
5. A0 is automatically complemented to load second byte of data A0 value determines which WD is supplied first: A0 = 0 looks at the
WDL, A0 = 1 looks at the WDH.
6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A9 - A8 = 0, A7 - A0 = 1,
others are don’t care.
Compatible Status Register
Following is the commands to be applied to each bank.
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
2 = Busy
CSR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
CSR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
CSR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
8
NOTES:
1. RY »/BY » output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPL and VPPH.
4. CSR.2 - CSR.0 = Reserved for further enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
4M (512K × 8) Flash Memory
4M DUAL WORK FLASH MEMORY
SOFTWARE ALGORITHMS
Overview
With the advanced Command User Interface, its Performance Enhancement commands and Status Registers, the software code required to perform a given
operation may become more intensive but it will result
in much higher write/erase performance compared with
current flash memory architectures.
The software flowcharts describing how a given
operation proceeds are shown here. Figures 4 through
6 depict flowcharts using the 2nd generation flash
device in the LH28F008SA-compatible mode. Figures
7 through 12 depict flowcharts using the 2nd generation flash device’s performance enhancement commands mode.
LH28F040SUTD-Z4
lock status, also the unlocked block data is erased. When
the device power-up or reset is completed, Set Write
Protect command must be written to reflect actual block
lock status.
Reset Write Protect command must be written before Write Block Lock command. To reflect actual block
lock status, Set Write Protect command is succeeded.
The Compatible Status Register (CSR) used to
determine which blocks are locked. In order to see Lock
Status of certain block, a Byte Write command (WA =
Block Address, WD = FHH) is written to the CUI, after
issuing Set Write Protect command. If CSR.7, CSR.5
and CSR.4 (WSMS, ES and DWS) are set to ‘1’s, the
block is locked. If CSR.7 is set to ‘1’, the block is not
locked.
Reset Write Protect command enables Write/Erase
operation to each block.
When the device power-up or reset is completed, Set
Write Protect command must be written to both the bank
selected by BE 0» and BE 1» in order to reflect actual block
lock status.
In the case of Block Erase is performed, the block
lock information is also erased. Block Lock command
and Set Write Protect command must be written to prohibit Write/Erase operation to each block.
When the device power-up or reset is completed, all
blocks come up locked. Therefore, Byte Write, Two Byte
Serial Write and Block Erase can not be performed in
each block. However, at that time, Erase All Unlocked
Block is performed normally, if used, and reflect actual
There are unassigned commands. It is not recommended that the customer use any command other than
the valid commands specified in “Command Bus Definitions”. Sharp reserved the right to redefine these codes
for future functions.
9
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
START
WRITE 40H or 10H
BUS
OPERATION
COMMAND
Write
Byte Write
D = 40H or 10H
A=X
Write
D = WD
A = WA
Read
Q = CSRD
Toggle BE0, BE1 or OE
to update CSRD.
A=X
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Standby
CSR.7 =
COMMENTS
0
Repeat for subsequent Byte Writes.
CSR Full Status Check can be done after each Byte Write,
or after a sequence of Byte Writes.
Write FFH after the last operation to reset device
to read array mode.
See Command Bus Cycle notes for description of codes.
1
CSR FULL STATUS
CHECK IF DESIRED
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
DATA WRITE
SUCCESSFUL
1
CSR.3 =
1
VPP LOW
DETECT
COMMENTS
COMMAND
Standby
Check CSR.4, 5
1 = Data Write Unsuccessful
0 = Data Write Successful
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F040SUZ4-4
Figure 4. Byte Writes with Compatible Status Register
10
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
START
WRITE 20H
BUS
OPERATION
COMMAND
Write
Block Erase
D = 20H
A=X
Write
Confirm
D = D0H
A = BA
WRITE D0H AND
BLOCK ADDRESS
Q = CSRD
Toggle BE0, BE1 or OE
to update CSRD.
A=X
Read
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
CSR.7 =
0
SUSPEND YES
ERASE
1
CSR FULL STATUS
CHECK IF DESIRED
COMMENTS
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent Block Erasures.
CSR Full Status Check can be done after each Block Erase,
or after a sequence of Block Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
CSR.3 =
1
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
(NOTE)
VPP LOW
DETECT
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
ERASE
SUCCESSFUL
1
COMMAND
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command.
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Single Block Erase command.
Where power off or chip reset during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command,
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
28F040SUZ4-5
Figure 5. Block Erase with Compatible Status Register
11
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
START
WRITE B0H
BUS
OPERATION
COMMAND
Write
Erase
Suspend
Read
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check CSR.6
1 = Erase Suspended
0 = Erase Completed
0
1
0
CSR.6 =
Write
ERASE COMPLETED
Read
Array
Read
1
Write
D = FFH
A=X
Q = AD
Read must be from
block other than the
one suspended.
WRITE FFH
READ ARRAY DATA
D = B0H
A=X
Q = CSRD
Toggle BE0, BE1 or OE
to update CSRD.
A=X
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
COMMENTS
Erase
Resume
D = D0H
A=X
See Command Bus Cycle notes for description of codes.
DONE
READING
NO
YES
WRITE D0H
WRITE FFH
ERASE RESUMED
READ ARRAY DATA
28F040SUZ4-6
Figure 6. Erase Suspend to Read Array with Compatible Status Register
12
4M (512K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
LH28F040SUTD-Z4
Q = CSRD
Toggle BE0, BE1 or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
0
Write
Reset
Write Protect
After Write D = 47H A = X,
Write D = D0H A = 0FFH
Q = CSRD
Read
1
Toggle BE0, BE1 or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
RESET WP
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
COMMENTS
Write
Lock Block
D = 77H
A=X
Write
Confirm
D = D0H
A = BA
0
Read
Q = CSRD
Toggle BE0, BE1, or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
1
WRITE 77H
Write
WRITE D0H AND
BLOCK ADDRESS
After Write D = 57H A = X,
Write D = D0H A = 0FFH
NOTE:
See CSR Full Status Check for Data-Write operation.
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Definitions for description of codes.
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
Set
Write Protect
0
1
CSR.4, 5 =
1
(NOTE)
0
LOCK
YES
ANOTHER
BLOCK
NO
SET WP
OPERATION COMPLETE
28F040SUZ4-7
Figure 7. Block Locking Scheme
13
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
START
START
RESET WP
(NOTE 1)
RESET WP
(NOTE 1)
ERASE BLOCK
(NOTE 2)
WRITE MORE
DATA TO BLOCK
(NOTE 4)
SET WP
(NOTE 3)
WRITE NEW DATA
TO BLOCK
(NOTE 4)
SET WP
(NOTE 3)
OPERATION
COMPLETE
FLOW TO ADD DATA
RELOCK BLOCK
(NOTE 5)
OPERATION
COMPLETE
FLOW TO REWRITE DATA
NOTES:
1. Use Reset-Write-Protect flowchart. Enable Write/Erase operation to all blocks.
2. Use Block-Erase flowchart. Erasing a block clears any previously established lockout for that block.
3. Use Set-Write-Protect flowchart. This step re-implements protection to locked blocks.
4. Use Byte-Write or 2-Byte-Write flowchart sequences to write data.
5. Use Block-Lock flowchart to write lock bit if desired.
Figure 8. Updating Data in a Locked Block
14
28F040SUZ4-8
4M (512K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
LH28F040SUTD-Z4
COMMENTS
Q = CSRD
Toggle BE0, BE1 or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
0
Write
1
2-Byte
Write
D = FBH
A=X
Write
D = WD
A0 = 0 loads low byte
of Data Register.
A0 = 1 loads high byte
of Data Register.
Other Addresses = X
Write
D = WD
A = WA
Internally, A0 is automatically
complemented to load the
alternate byte location of the
Data Register.
Read
Q = CSRD
WRITE FBH
WRITE DATA/A0
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
Toggle BE0, BE1 or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
0
1
CSR.4, 5 =
1
(NOTE)
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Cycle notes for description of codes.
0
ANOTHER
2-BYTE
WRITE
YES
NO
OPERATION COMPLETE
28F040SUZ4-9
Figure 9. Two-Byte Serial Writes with Compatible Status Registers
15
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
START
(NOTE)
BUS
OPERATION
COMMAND
Write
Erase All
Unlocked
Blocks
D = A7H
A=X
Write
Confirm
D = D0H
A=X
WRITE A7H
WRITE D0H
Q = CSRD
Toggle BE0, BE1 or OE
to update CSRD.
A=X
Read
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
CSR.7 =
0
SUSPEND
ERASE
COMMENTS
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Standby
YES
1
CSR FULL STATUS
CHECK IF DESIRED
CSR Full Status Check can be done after Erase All Unlocked
Block, or after a sequence of Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
NOTE:
Where power off or reset during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command,
2. Retry Erase All Unlocked Block Erase command to
erase all blocks, or issue Single Block Erase to
erase all of the unlocked blocks in sequence.
3. Set WP command is issued, if necessary.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
CSR.3 =
1
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
(NOTE)
VPP LOW
DETECT
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
ERASE
SUCCESSFUL
1
COMMAND
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command,
2. Retry Erase All Unlocked Block Erase command to erase
all blocks, or issue Single Block Erase to erase all of the
unlocked blocks in sequence.
3. Set WP command is issued, if necessary.
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Erase All Unlocked Block Erase command.
28F040SUZ4-10
Figure 10. Bank Erase All Unlocked Blocks with Compatible Status Registers
16
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
BUS
COMMAND
OPERATION
START
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
COMMENTS
Write
Set
Write Protect
D = 57H
A=X
Write
Set Confirm
D = D0H
A = 0FFH
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Read
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE 57H
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Upon device power-up or reset is complete, Set Write
Protect command must be written to reflect the actual
lock-bit status.
Write FFH after the last operation to reset device to
Read Array Mode.
See Command Bus Cycle notes for description of codes.
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
0
OPERATION
COMPLETE
28F040SUZ4-11
Figure 11. Set Write Protect
17
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
COMMENTS
Write
Reset
Write Protect
Write
Reset
Confirm
D = 47H
A=X
D = D0H
A = 0FFH
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Read
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE 47H
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Reset Write Protect command enables Write/Erase
operation to all blocks.
Write FFH after the last operation to reset device to
Read Array Mode.
See Command Bus Cycle notes for description of codes.
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
0
OPERATION
COMPLETE
28F040SUZ4-12
Figure 12. Reset Write Protect
18
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
*WARNING: Stressing the device beyond
ELECTRICAL SPECIFICATIONS
the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
Absolute Maximum Ratings*
Temperature under bias ...................... -20°C to +80°C
Storage temperature ......................... -65°C to +125°C
SYMBOL
TA
PARAMETER
Operating Temperature, Commercial
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
0
70.0
°C
Ambient Temperature
1
VCC
VCC with Respect to GND
-0.2
7.0
V
2
VPP
VPP Supply Voltage with Respect to GND
-0.2
7.0
V
2
V
Voltage on any Pin (Except VCC, VPP)
with Respect to GND
-0.5
VCC + 0.5
V
2
I
Current into any Non-Supply Pin
±30
mA
100.0
mA
IOUT
Output Short Circuit Current
3
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum
DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
Capacitance
SYMBOL
TYP.
MAX.
UNITS
Capacitance Looking into an
Address/Control Pin
14
20
pF
TA = 25°C, f = 1.0 MHz
1, 2
COUT
Capacitance Looking into an Output Pin
18
24
pF
TA = 25°C, f = 1.0 MHz
1
CLOAD
Load Capacitance Driven by Outputs for
Timing Specifications
50
pF
For VCC = 3.3 V ±0.3 V
1
Equivalent Testing Load Circuit VCC ± 10%
2.5
ns
50 Ω transmission line delay
CIN
PARAMETER
TEST CONDITIONS
NOTE
NOTE:
1. Sampled, not 100% tested.
2. BE »0 and BE »1 have half the value of this.
19
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
Timing Nomenclature
For 3.3 V systems use 1.5 V cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tELQV
time (t) from BE » (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV
time (t) from OE » (G) going low (L) to the outputs (Q) becoming valid (V)
tACC tAVQV
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS
tAVWH time (t) from address (A) valid (V) to WE » (W) going high (H)
tDH
tWHDX time (t) from WE » (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
PIN STATES
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
BE » (Byte Enable)1
X
Driven, but not necessarily valid
G
OE » (Output Enable)
Z
High Impedance
W
WE (Write Enable)
V
Any Voltage Level
3V
VCC at 3.0 V Min.
NOTE:
1. BE »X means either BE »0 or BE »1.
2.5 ns OF 50 Ω TRANSMISSION LINE
3.0
INPUT 1.5
0.0
TEST POINTS
1.5 OUTPUT
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1'
and 0.0 V for a Logic '0'. Input timing begins
and output timing ends at 1.5 V. Input rise
and fall times (10% to 90%) < 10 ns.
FROM OUTPUT
UNDER TEST
TEST
POINT
TOTAL CAPACITANCE = 50 pF
28F040SUZ4-14
28F040SUZ4-13
Figure 13. Transient Input/Output
Reference Waveform (VCC = 3.3 V)
20
Figure 14. Transient Equivalent Testing
Load Circuit (VCC = 3.3 V)
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
DC Characteristics
VCC = 3.3 V ± 0.3 V, TA = -20°C to +70°C
Following is the current consumption of one bank. For the current consumption of one device total, please refer to
Note 5.
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IIL
Input Load Current
±2
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage
Current
±20
µA
VCC = VCC MAX., VIN = VCC or GND
1
10
µA
VCC = VCC MAX.,
BE »0, BE »1 = VCC ±0.2 V
mA
VCC = VCC MAX.,
BE »0, BE »1 = VIH
mA
VCC = VCC MAX.,
CMOS: BE »0, BE »1 = GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V,
TTL: BE »0, BE »1 = VIL,
Inputs = VIL or VIH,
f = 10 MHz, IOUT = 0 mA
1, 3,
4, 5
1, 3,
4, 5
5
ICCS
VCC Standby Current
0.3
ICCR1
VCC Read Current
(10 MHz Operation)
4
35
1, 4, 5
ICCR2
VCC Read Current
(5 MHz Operation)
10
20
mA
VCC = VCC MAX.,
CMOS: BE »0, BE »1 = GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V,
TTL: BE »0, BE »1 = VIL,
Inputs = VIL or VIH,
f = 5 MHz, IOUT = 0 mA
ICCW
VCC Write Current
8
12
mA
Byte/Two-Byte Serial Write
in Progress
1, 5
ICCE
VCC Block Erase
Current
6
12
mA
Block Erase in Progress
1, 5
ICCES
VCC Erase Suspend
Current
3
6
mA
BE »0, BE »1 = VIH
Block Erase Suspended
1, 2, 5
IPPS
VPP Standby Current
±1
±10
µA
VPP ≤ VCC
1, 5
21
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
DC Characteristics (Continued)
VCC = 3.3 V ± 0.3 V, TA = -20°C to +70°C
SYMBOL
PARAMETER
TYPE
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IPPR
VPP Read Current
65
200
µA
VPP > VCC
1, 5
IPPW
VPP Write Current
15
35
mA
VPP = VPPH, Byte/Two-Byte
Serial Write in Progress
1, 5
IPPE
VPP Erase Current
20
40
mA
VPP = VPPH,
Block Erase in Progress
1, 5
IPPES
VPP Erase Suspend
Current
65
200
µA
VPP = VPPH,
Block Erase Suspended
1, 5
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.3
V
VOL
Output Low Voltage
0.4
V
VCC = VCC MIN. and
IOL = 4 mA
2.4
V
IOH = -2 mA
VCC = VCC MIN.
VCC - 0.2
V
IOH = 100 µA
VCC = VCC MIN.
VOH1
Output High Voltage
VOH
2
VPPL
VPP during Normal
Operations
VPPH
VPP during Write/Erase
Operations
VLKO
VCC Erase/Write
Lock Voltage
5.0
0.0
5.5
V
4.5
5.5
V
1.4
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3 V, VPP = 5.0 V, T = 25°C.
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation.
4. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.
5. These are the values of the current which is consumed within one bank area. The value for the bank0 and bank1 should be added in
order to calculate the value for the whole chip. If the bank0 is in write state and bank1 is in read state, the I CC = ICCW + ICCR. If both
banks are in standby mode, the value for the device is 2 times the value in the above table.
22
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
AC Characteristics - Read Only Operations1
VCC = 3.3 V ± 0.3 V, TA = -20°C to +70°C
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
tAVAV
Read Cycle Time
tAVGL
Address Setup to OE » Going Low
tAVQV
Address to Output Delay
150
ns
tELQV
BE »0, BE »1 to Output Delay
150
ns
2
tGLQV
OE » to Output Delay
50
ns
2
tELQX
BE »0, BE »1 to Output in Low Z
ns
3
tEHQZ
BE »0, BE »1 to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
UNITS
NOTE
tOH
Output Hold from Address, BE »0, BE »1 or
OE » change, whichever occurs first
150
ns
0
ns
NOTE
0
55
0
40
0
3
AC Characteristics - Read Only Operations1 (Continuted)
VCC = 2.85 V ± 0.15 V, TA = -20°C to +70°C
SYMBOL
PARAMETER
MIN.
MAX.
tAVAV
Read Cycle Time
tAVGL
Address Setup to OE » Going Low
tAVQV
Address to Output Delay
190
ns
tELQV
BE »0, BE »1 to Output Delay
190
ns
2
tGLQV
OE » to Output Delay
65
ns
2
tELQX
BE »0, BE »1 to Output in Low Z
ns
3
tEHQZ
BE »0, BE »1 to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
tOH
Output Hold from Address, BE »0, BE »1
or OE » change, whichever occurs first
190
ns
0
ns
0
70
0
55
0
3
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figure 4.
2. OE » may be delayed up to tELQV - tGLQV after the falling edge of BE 0» , BE »1 without impact on tELQV.
3. Sampled, not 100% tested.
23
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
VCC
POWER-UP
ADDRESSES (A)
STANDBY
DEVICE AND
ADDRESS
SELECTION
VIH
OUTPUTS ENABLED
DATA VALID
ADDRESSES STABLE
VIL
...
...
VCC
STANDBY POWER-DOWN
tAVAV
BEX (E)
(NOTE)
VIH
...
VIL
tEHQZ
OE (G)
VIH
...
VIL
tAVGL
WE (W)
tGHQZ
...
VIH
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
DATA (D/Q)
VOH
...
HIGH-Z
VALID OUTPUT
HIGH-Z
...
VOL
tAVQV
3.3 V
VCC
GND
NOTE: BEX means either BE0 or BE1
28F040SUZ4-15
Figure 15. Read Timing Waveforms
24
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
POWER-UP AND RESET TIMINGS
VCC POWER UP
tEHRS
tELRS
BEX (E)
(NOTE)
OE (G)
tGLRS
tGHRS
WE (W)
3.3 V
3.3 V
3.0 V
VCC (3.5 V)
0V
tWLPL
ADDRESS (A)
VALID
tAVQV
VALID
3.3 V OUTPUTS
DATA (Q)
tPHQV
NOTE: BEX means either BE0 or BE1
28F040SUZ4-16
Figure 16. VCC Power-Up and RP » Reset Waveforms
SYMBOL
PARAMETER
MIN.
MAX.
5
UNITS
NOTE
µs
1
tWLPL
WE Low to VCC at 3.0 V MIN.
tAVQV
Address Valid to Data Valid for VCC = 3.3 V ± 0.3 V
150
ns
2
tPHQV
WE High to Data Valid for VCC = 3.3 V ± 0.3 V
500
ns
2
tELRS
BE »0 and BE »1 Setup to WE Going Low
100
ns
tGLRS
OE » Setup to WE Going Low
100
ns
tEHRS
BE »0 and BE »1 Hold from WE Going High
100
ns
tGHRS
OE » Hold from WE Going High
100
ns
NOTES:
BE »0, BE »1 and OE » must be set high once after power-up. BE »0 and BE »1 must not be set low at the same time.
1. Chip reset is enabled when the low state of all BE »0 (or BE »1), OE » and WE » exceeds 5 µs. Especially when you will
power on the chip, execute an above chip reset sequence for a protection from noise. All BE »0 (or BE »1), OE » and WE »
must not be low, except for the purpose of chip reset.
2. These values are shown for 3.3 V VCC operation. Refer to the AC Characteristics Read Only Operations also.
25
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
AC Characteristics for WE » - Controlled Command Write Operations1
VCC = 3.25 V ± 0.35 V, TA = -20°C to +70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
tAVAV
Write Cycle Time
150
ns
tVPWH
VPP Set up to WE Going High
100
ns
tELWL
BE »0 and BE »1 Setup to WE Going Low
0
ns
tAVWH
Address Setup to WE Going High
110
ns
2, 6
tDVWH
Data Setup to WE Going High
110
ns
2, 6
tWLWH
WE Pulse Width
110
ns
tWHDX
Data Hold from WE High
10
ns
2
tWHAX
Address Hold from WE High
10
ns
2
tWHEH
BE »0 and BE »1 Hold from WE High
10
ns
tWHWL
WE Pulse Width High
75
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
120
ns
tQVVL
VPP Hold from Valid Status Register Data
0
µs
tWHQV1
Duration of Byte Write Operation
tWHQV2
Duration of Block Erase Operation
20
8
0.3
250
3
µs
4, 5, 7
s
4
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE » for all Command Write operations.
7. The maximum value of byte write time is the maximum write time inside the chip. It is not the time until the whole
writing procedure is completed properly. It is necessary to check CSR to see if the writing procedure is properly
completed.
26
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
WRITE
DATA-WRITE
OR ERASE
SETUP COMMAND
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
AIN
READ
COMPATIBLE
STATUS
REGISTER DATA
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
(NOTE 2)
tAVWH tWHAX
tAVAV
BEX (E) VIH
(NOTE 3) VIL
tWHEH
tWHGL
tELWL
OE (G)
VIH
VIL
tWHWL
WE (W)
tWHQV 1, 2
tGHWL
VIH
VIL
tWLWH
tWHDX
tDVWH
DATA (D/Q)
VIH
VIL
HIGH-Z
DIN
DIN
DIN
tVPWH
DOUT
DIN
tQVVL
VPPH
VPP (V) V
PPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
2. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
3. BEX means either BE0 or BE1
28F040SUZ4-17
Figure 17. Waveforms for Command Write Operations
27
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
AC Characteristics for BE » - Controlled Command Write Operations2
VCC = 3.25 V ± 0.35 V, TA = -20°C to +70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
tAVAV
Write Cycle Time
150
ns
tVPEH
VPP Set up to BE »0 or BE »1 Going High
100
ns
tWLEL
WE Setup to BE »0 or BE »1 Going Low
0
ns
tAVEH
Address Setup to BE »0 or BE »1 Going High
110
ns
2, 6
tDVEH
Data Setup to BE »0 or BE »1 Going High
110
ns
2, 6
tELEH
BE »0 or BE »1 Pulse Width
110
ns
tEHDX
Data Hold from BE »0 or BE »1 High
10
ns
2
tEHAX
Address Hold from BE »0 or BE »1 High
10
ns
2
tEHWH
WE Hold from BE »0 or BE »1 High
10
ns
tEHEL
BE »0 or BE »1 Pulse Width High
75
ns
tGHEL
Read Recovery before Write
0
ns
tEHGL
Write Recovery before Read
120
ns
tQVVL
VPP Hold from Valid Status Register Data
0
µs
tEHQV1
Duration of Byte Write Operation
tEHQV2
Duration of Block Erase Operation
20
8
0.3
250
3
µs
4, 5, 7
s
4
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of BE »0 or BE 1» for all Command Write operations.
7. The MAX. value of byte write time is the maximum wrtie time inside the chip. It is not the time until the whole writing
procedure is completed properly. It is necessary to check CSR to see if the writing procedure is properly completed.
28
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
WRITE
DATA-WRITE
OR ERASE
SETUP COMMAND
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
(NOTE 2)
AIN
tAVAV
tAVEH
READ
COMPATIBLE
STATUS
REGISTER DATA
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
tEHAX
VIH
WE (W)
VIL
tEHWH
tEHGL
tWLEL
OE (E)
VIH
VIL
tEHEL
tEHQV 1, 2
tGHEL
BEX (E) VIH
(NOTE 3) VIL
tELEH
tEHDX
tDVEH
DATA (D/Q)
VIH
VIL
HIGH-Z
DIN
DIN
DIN
tVPEH
DOUT
DIN
tQVVL
VPPH
VPP (V)
VPPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
2. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
3. BEX means either BE0 or BE1
28F040SUZ4-18
Figure 18. Alternate AC Waveforms for Command Write Operations
29
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
Erase and Byte Write Performance
VCC = 3.25 V ± 0.35 V, TA = -20°C to +70°C
SYMBOL
PARAMETER
TYP.(1)
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
250
µs
2, 3
µs
2
tWHRH1
Byte Write Time
20
tWHRH2
Two-Byte Serial Write Time
34
tWHRH3
16KB Block Write Time
0.33
1.0
s
Byte Write Mode
2
tWHRH4
16KB Block Write Time
0.28
1.0
s
Two-Byte Serial Write Mode
2
Block Erase Time (16KB)
0.8
10
s
2
2M Bit Bank Erase Time
9 - 15
s
2, 4
NOTES:
1. 25°C, VPP = 5.0 V
2. Excludes System-Level Overhead. It actually indicates the time from input write/erase command until bit7 of status register becomes
ready (WSMS = 0).
3. The MAX. value of byte write time is the maximum write time inside the chip. It is not the time until the whole writing procedure is completed properly. It is necessary to check CSR to see if the writing procedure is properly completed.
4. Depends on the number of protected blocks.
30
4M (512K × 8) Flash Memory
LH28F040SUTD-Z4
40TSOP (TSOP040-P-1020)
40
1
0.50 [0.020]
TYP.
10.20 [0.402]
9.80 [0.386]
0.25 [0.010]
0.15 [0.006]
20
21
1.10 [0.043]
0.90 [0.035]
SEE DETAIL
1.19
[0.047]
MAX.
0.49 [0.019]
0.39 [0.015]
DETAIL
0.125 [0.005]
18.60 [0.732]
18.20 [0.717]
19.30 [0.760]
18.70 [0.736]
0.49 [0.019]
0.39 [0.015]
20.30 [0.799]
19.70 [0.776]
DIMENSIONS IN MM [INCHES]
0.22 [0.009]
0.02 [0.001]
MAXIMUM LIMIT
MINIMUM LIMIT
0 - 10°
0.18 [0.007]
0.08 [0.003]
40TSOP
ORDERING INFORMATION
LH28F040SU
T
Device Type Package
D
-Z4
Speed
190 Access Time (ns)
Dual Works
40-pin, 1.2 mm x 10 mm x 20 mm TSOP (Type I) (TSOP040-P-1020)
4M (512K x 8) Flash Memory
Example: LH28F040SUT-Z4 (4M (512K x 8) Flash Memory, 190 ns, 40-pin TSOP)
28F040SUZ4-19
31
LH28F040SUTD-Z4
4M (512K × 8) Flash Memory
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
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SHARP Electronics Corporation
Microelectronics Group
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Phone: (360) 834-2500
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SHARP Corporation
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Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
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Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Issued July 1996
Reference Code SMT96117