ETC W28J800

W28J800B/T
8M(512K × 16/1M × 8)
BOOT BLOCK FLASH MEMORY
Table of Contents1. GENERAL DESCRIPTION.................................................................................................................. 3
2. FEATURES ......................................................................................................................................... 3
3. PRODUCT OVERVIEW ...................................................................................................................... 4
4. BLOCK DIAGRAM .............................................................................................................................. 5
Block Organization ........................................................................................................................... 6
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. PRINCIPLES OF OPERATION........................................................................................................... 8
Data Protection ................................................................................................................................ 8
8. BUS OPERATION ............................................................................................................................. 10
Read............................................................................................................................................... 10
Output Disable ............................................................................................................................... 10
Standby .......................................................................................................................................... 10
Reset .............................................................................................................................................. 10
Read Identifier Codes .................................................................................................................... 11
OTP (One Time Program) Block.................................................................................................... 12
Write ............................................................................................................................................... 13
9. COMMAND DEFINITIONS................................................................................................................ 14
Read Array Command ................................................................................................................... 16
Read Identifier Codes Command................................................................................................... 16
Read Status Register Command ................................................................................................... 16
Clear Status Register Command ................................................................................................... 17
Block Erase Command .................................................................................................................. 17
Full Chip Erase Command ............................................................................................................. 17
Word/Byte Write Command ........................................................................................................... 18
Block Erase Suspend Command ................................................................................................... 18
Word/Byte Write Suspend Command ............................................................................................ 19
Set Block and Permanent Lock-bit Commands ............................................................................. 19
Clear Block Lock-bits Command.................................................................................................... 20
OTP Program Command ............................................................................................................... 21
Block Locking by the #WP ............................................................................................................. 21
-1-
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
10. DESIGN CONSIDERATIONS ......................................................................................................... 33
Three-line Output Control............................................................................................................... 33
RY/#BY and WSM Polling.............................................................................................................. 33
Power Supply Decoupling .............................................................................................................. 33
VPP Trace on Printed Circuit Boards .............................................................................................. 33
VDD, VPP, #RESET Transitions ....................................................................................................... 33
Power-up/Down Protection ............................................................................................................ 34
Power Dissipation .......................................................................................................................... 34
Data Protection Method ................................................................................................................. 34
11. ELECTRICAL SPECIFICATIONS ................................................................................................... 35
Absolute Maximum Ratings* .......................................................................................................... 35
Operating Conditions ..................................................................................................................... 35
Capacitance(1)............................................................................................................................... 36
AC Input/Output Test Conditions ................................................................................................... 36
DC Characteristics ......................................................................................................................... 37
AC Characteristics - Read-only Operations(1) .............................................................................. 39
AC Characteristics - Write Operations(1) ...................................................................................... 42
Reset Operations ........................................................................................................................... 46
Block Erase, Full Chip Erase, Word/Byte Write And Lock-Bit Configuration Performance(3) ...... 47
12. ADDITIONAL INFORMATION......................................................................................................... 48
Recommended Operating Conditions............................................................................................ 48
13. ORDERING INFORMATION........................................................................................................... 50
14. PACKAGE DIMENSION.................................................................................................................. 50
15. VERSION HISTORY ....................................................................................................................... 51
-2-
W28J800B/T
1. GENERAL DESCRIPTION
The W28J800B/T Flash memory chip is a high-density, cost-effective, nonvolatile, read/write storage
device suited for a wide range of applications. It operates off of VDD = 2.7V to 3.6V, with VPP of 2.7V to
3.6V or 11.7V to 12.3V. This low voltage operation capability enbales use in low power applications.
The IC features a boot, parameter and main-blocked architecture, as well as low voltage and
extended cycling. These features provide a highly flexible device suitable for portable terminals and
personal computers. Additionally, the enhanced suspend capabilities provide an ideal solution for both
code and data storage applications. For secure code storage applications, such as networking where
code is either directly executed out of flash or downloaded to DRAM, the device offers four levels of
protection. These are: absolute protection, enabled when VPP ≤ VPPLK; selective hardware blocking;
flexible software blocking; or write protection. These alternatives give designers comprehensive
control over their code security needs. The device is manufactured using 0.25µm process technology.
It comes in industry-standard packaging, a 48-lead TSOP, which makes it ideal for small real estate
applications.
2. FEATURES
•
Low Voltage Operation
− VDD = VPP = 2.7V to 3.6V Single Voltage
•
OTP (One Time Program) Block
− 3963 word + 4 word Program only array
• Enhanced Automated Suspend Options
− Word/Byte Write Suspend to Read
− Block Erase Suspend to Word/Byte Write
− Block Erase Suspend to Read
•
User-Configurable x 8 or x 16 Operation
•
•
High-Performance Read Access Time
− 90 nS (VDD = 2.7V to 3.6V)
•
Operating Temperature
− 0° C to +70° C (W28J800BT/TT90C)
− -40° C to +85° C (W28J800BT/TT90L)
Enhanced Data Protection Features
− Absolute Protection with VPP ≤ VPPLK
− Block Erase, Full Chip Erase, Word/Byte
Write and Lock-Bit Configuration Lockout
during Power Transitions
− Block Locking with Command and #WP
− Permanent Locking
•
Low Power Management
•
Automated Block Erase, Full Chip Erase, Low
Power Management Word/Byte Write and
Lock-Bit Configuration
− Command User Interface (CUI)
− Status Register (SR)
− 2 µA Typical Standby Current
− Automatic Power Savings Mode Decreases
ICCR in Static Mode
− 120 µA Typical Read Current
Optimized Array Blocking Architecture
− Two 4k-word (8k-byte) Boot Blocks
− Six 4k-word (8k-byte) Parameter Blocks
− Fifteen 32k-word (64k-byte) Main Blocks
− Top or Bottom Boot Location
• Extended Cycling Capability
− Minimum 100,000 Block Erase Cycles
•
• Low power consumption
− Active current: 20 mA (typ.)
− Standby current: 15 µA (typ.)
• SRAM-Compatible Write Interface
• Industry-Standard Packaging
− 48-Lead TSOP
-3-
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
3. PRODUCT OVERVIEW
The product is a high-performance 8M-bit Boot Block Flash memory organized as 512k-word of 16
bits or 1M-byte of 8 bits. The 512k-word/1M-byte of data is arranged in two 4k-word/8k-byte boot
blocks, six 4k-word/8k-byte parameter blocks and fifteen 32k-word/64k-byte main blocks which are
individually erasable, lockable and unlockable in-system. The memory map is shown in Figure 3.
The dedicated VPP pin gives complete data protection when VPP ≤ VPPLK.
A Command User Interface (CUI) serves as the interface between the system processor and internal
operation of the device. A valid command sequence written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for
block erase, full chip erase, word/byte write and lock-bit configuration operations.
A block erase operation erases one of the device’s 32k-word/64k-byte blocks typically within 1.2S (3V
VDD, 3V VPP), 4k-word/8k-byte blocks typically within 0.6s (3V VDD, 3V VPP) independent of other
blocks. Each block can be independently erased minimum 100,000 times. Block erase suspend mode
allows system software to suspend block erase to read or write data from any other block.
Writing memory data is performed in word/byte increments of the device’s 32k-word blocks typically
within 33 µS (3V VDD, 3V VPP), 64k-byte blocks typically within 31 µS (3V VDD, 3V VPP), 4k-word
blocks typically within 36 µS (3V VDD, 3V VPP), 8k-byte blocks typically within 32 µS (3V VDD, 3V VPP).
Word/byte write suspend mode enables the system to read data or execute code from any other flash
memory array location.
Individual block locking uses a combination of bits, thirty-nine block lock-bits, a permanent lock-bit and
#WP pin, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word/byte
write operations, while the permanent lock-bit gates block lock-bit modification and locked block
alternation. Lock-bit configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear
Block Lock-Bits commands) set and cleared lock-bits.
The status register indicates when the WSM’s block erase, full chip erase, word/byte write or lock-bit
configuration operation is finished.
The RY/#BY output gives an additional indicator of WSM activity by providing both a hardware signal
of status (versus software polling) and status masking (interrupt masking for background block erase,
for example). Status polling using RY/#BY minimizes both CPU overhead and system power
consumption. When low, RY/#BY indicates that the WSM is performing a block erase, full chip erase,
word/byte write or lock-bit configuration. RY/#BY-high Z indicates that the WSM is ready for a new
command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended,
or the device is in reset mode.
The access time is 90 nS (tAVQV) over the operating temperature range and VDD supply voltage range
of 2.7V to 3.6V.
The Automatic Power Savings (APS) feature substantially reduces active current when the device is in
static mode (addresses not switching). In APS mode, the typical ICCR current is 2 µA (CMOS) at 3.0V
VDD.
When #CE and #RESET pins are at VDD, the ICC CMOS standby mode is enabled. When the #RESET
pin is at VSS, reset mode is enabled which minimizes power consumption and provides write
protection. A reset time (tPHQV) is required from #RESET switching high until outputs are valid.
Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the CUI are recognized.
With #RESET at VSS, the WSM is reset and the status register is cleared.
-4-
W28J800B/T
Overwriting a "0" to a bit already holding a data "0" may render this bit un-erasable. In order to avoid
this potential "stuck bit" failure, when re-programming (changing data from "1" to "0") the following
should be followed:
•
Program "0" for the bit in which you want to change data from "1" to "0".
•
Program "1" for the bit which is already holding a data "0". (Note: Since only an erase process
can change the data from "0" to "1", programming "1" to a bit holding a data "0" will not
change the data).
For example, changing data from "10111101" to "10111100" requires "11111110" programming.
4. BLOCK DIAGRAM
DQ0 -DQ15
Input Buffer
Output Buffer
I/O Logic
Identifier
Register
VDD
#BYTE
#CE
Output
Multiplexer
Command
User
Interface
Data
Register
Status
Register
#WE
#OE
#RESET
#WP
Data
Comparator
OTP Block
32K-Word
(64K-Byte)
Main Blocks
x 15
Main Block 13
Write
State
Machine
Main Block 14
Main Block 0
Main Block 1
Parameter Block 5
Parameter Block 3
Parameter Block 4
Parameter Block 1
Parameter Block 2
X
Decoder
Y-Gating
Boot Block 1
Address
Latch
Y
Decoder
Parameter Block 0
Input
Buffer
Boot Block 0
A1-A18
RY/#BY
Program/Erase
Voltage Switch
VPP
VDD
VSS
Address
Counter
Figure 1. Block Diagram
-5-
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Block Organization
This product features an asymmetrically-blocked architecture providing system memory integration.
Each erase block can be erased independently of the others up to 100,000 times. For the address
locations of the blocks, see the memory map in Figure 3.
Boot Blocks: The boot block is intended to replace a dedicated boot PROM in a microprocessor or
microcontroller-based system. This boot block 4k words (4,096 words) features hardware controllable
write protection to protect the crucial microprocessor boot code from accidental modification. The
protection of the boot block is controlled using a combination of the VPP, #RESET, #WP pins and
block lock-bit.
Parameter Blocks: The boot block architecture includes parameter blocks to facilitate storage of
frequently update small parameters that would normally require an EEPROM. By using software
techniques, the word-rewrite functionality of EEPROMs can be emulated. Each boot block component
contains six parameter blocks of 4k words (4,096 words) each. The protection of the parameter block
is controlled using a combination of the VPP, #RESET and block lock-bit.
Main Blocks: The reminder is divided into main blocks for data or code storage. Each 8M-bit device
contains fifteen 32k words (32,768 words) blocks. The protection of the main block is controlled using
a combination of the VPP, #RESET and block lock-bit.
5. PIN CONFIGURATION
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
#WE
#RESET
Vpp
#WP
RY/#BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
2
47
7
46
3
4
45
44
5
6
43
7
8
42
41
9
10
11
12
13
14
15
16
40
48-pin TSOP
Standard Pinout
12mm X 20mm
Top View
17
18
39
38
37
36
35
34
33
32
31
30
19
20
29
28
21
27
22
23
26
25
24
Figure 2. TSOP 48-Lead Pinout
-6-
A16
#BYTE
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
#OE
Vss
#CE
A0
W28J800B/T
6. PIN DESCRIPTION
SYM.
A-1
A0 − A18
DQ0 −
DQ15
TYPE
NAME AND FUNCTION
INPUT
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A -1: Lower address input while #BYTE is VIL. A-1 pin changes DQ15 pin while #BYTE is VIH.
A15 − A18: Main Block Address.
A12 − A18: Boot and Parameter Block Address.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins float to
INPUT/
high-impedance when the chip is deselected or outputs are disabled. Data is internally
OUTPUT
latched during a pin write cycle. DQ8 − DQ15 pins are not used while byte mode (#BYTE =
VIL). Then, DQ15 changes A-1address input.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers.
#CE-high deselects the device and reduces power consumption to standby levels.
#RESET
INPUT
RESET: Resets the device internal automation. #RESET-high enables normal operation.
When driven low, #RESET inhibits write operations which provides data protection during
power transitions. Exit from reset mode sets the device to read array mode. #RESET must
be VIL during power-up.
#OE
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
#WE
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the #WE pulse.
#WP
INPUT
WRITE PROTECT: When #WP is VIL, boot blocks cannot be written or erased. When #WP is
VIH, locked boot blocks can not be written or erased. #WP is not affected parameter and main
places device in byte mode (x 8). All data is then input or output on blocks.
#BYTE
INPUT
BYTE ENABLE: #BYTE VIL places the device in byte mode (x 8), All data is then input or
output on DQ0 − 7, and DQ8 − 15 float. #BYTE VIH places the device in word mode (×16),
and turns off the A-1 input buffer.
#CE
READY/#BUSY: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, full chip erase, word/byte write or lock-bit
OPEN
configuration).
RY/#BY DRAIN
RY/#BY-high Z indicates that the WSM is ready for new commands, block erase is
OUTPUT
suspended, and word/byte write is inactive, word/byte write is suspended, or the device is
in reset mode.
VPP
BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE OR LOCK-BIT
CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words/bytes or
configuring lock-bits. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase,
SUPPLY full chip erase, word/byte write and lock-bit configuration with an invalid VPP (see DC
Characteristics) produce spurious results and should not be attempted. Applying 12V
±0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each
block. VPP may be connected to 12V ±0.3V for a total of 80 hours maximum.
VDD
DEVICE POWER SUPPLY: Do not float any power pins. With VDD ≤ VLKO, all write
SUPPLY attempts to the flash memory are inhibited. Device operations at invalid VDD voltage (see
DC Characteristics) produce spurious results and should not be attempted.
VSS
SUPPLY GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Table 1.
-7-
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
7. PRINCIPLES OF OPERATION
The product includes an on-chip WSM to manage block erase, full chip erase, word/byte write and
lock-bit configuration functions. It allows for one hundred percent TTL-level control inputs, fixed power
supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from reset mode (see Bus Operations section), the device
defaults to read array mode. Manipulation of external memory control pins allow array read, standby
and output disable operations.
Status register and identifier codes can be accessed through the CUI independent of the VPP voltage.
High voltage on VPP enables successful block erase, full chip erase, word/byte write and lock-bit
configurations. All functions associated with altering memory contents (block erase, full chip erase,
word/byte write, lock-bit configuration, status and identifier codes) are accessed via the CUI and
verified through the status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as input
to the WSM, which controls the block erase, full chip erase, word/byte write and lock-bit configuration.
The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and
margining of data. Addresses and data are internally latched during write cycles. Writing the
appropriate command outputs array data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block erase, full chip erase, word/byte write and
lock-bit configuration can be stored in any block. This code is copied to and executed from system
RAM during flash memory updates. After successful completion, reads are again possible via the
Read Array command. Block erase suspend allows system software to suspend a block erase to
read/write data from/to blocks other than that which is suspend. Word/byte write suspend allows
system software to suspend a word/byte write to read data from any other flash memory array
location.
Data Protection
When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command sequences, provides protection from
unwanted operations even when high voltage is applied to VPP. All write functions are disabled when
VDD is below the write lockout voltage VLKO or when #RESET is at VIL. The device’s block locking
capability provides additional protection from inadvertent code or data alteration by gating block erase,
full chip erase and word/byte write operations.
Reference Table 5 for write protection alternatives.
-8-
W28J800B/T
[A18-A0]
7FFFF
7F000
7EFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
Top Boot
4KW/8KB Boot Block 0
4KW/8KB Boot Block 1
4KW/8KB Parameter Block 0
4KW/8KB Parameter Block 1
4KW/8KB Parameter Block 2
4KW/8KB Parameter Block 3
4KW/8KB Parameter Block 4
4KW/8KB Parameter Block 5
32KW/64KB Main Block 0
32KW/64KB Main Block 1
32KW/64KB Main Block 2
32KW/64KB Main Block 3
32KW/64KB Main Block 4
32KW/64KB Main Block 5
32KW/64KB Main Block 6
32KW/64KB Main Block 7
32KW/64KB Main Block 8
32KW/64KB Main Block 9
32KW/64KB Main Block 10
32KW/64KB Main Block 11
32KW/64KB Main Block 12
32KW/64KB Main Block 13
32KW/64KB Main Block 14
[A18-A0]
[A18-A1]
FFFFF
FE000
FDFFF
FC000
FBFFF
FA000
F9FFF
F8000
F7FFF
F6000
F5FFF
F4000
F3FFF
F2000
F1FFF
F0000
EFFFF
E0000
DEFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
Bottom Boot
32KW/64KB Main Block 14
32KW/64KB Main Block 13
32KW/64KB Main Block 12
32KW/64KB Main Block 11
32KW/64KB Main Block 10
32KW/64KB Main Block 9
32KW/64KB Main Block 8
32KW/64KB Main Block 7
32KW/64KB Main Block 6
32KW/64KB Main Block 5
32KW/64KB Main Block 4
32KW/64KB Main Block 3
32KW/64KB Main Block 2
32KW/64KB Main Block 1
32KW/64KB Main Block 0
4KW/8KB Parameter Block 5
4KW/8KB Parameter Block 4
4KW/8KB Parameter Block 3
4KW/8KB Parameter Block 2
4KW/8KB Parameter Block 1
4KW/8KB Parameter Block 0
4KW/8KB Boot Block 1
4KW/8KB Boot Block 0
[A18-A1]
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
00E000
00DFFF
00C000
00BFFF
00A000
009FFF
008000
007000
006000
005FFF
004000
003FFF
002000
001FFF
000000
Figure 3. Memory Map
-9-
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
8. BUS OPERATION
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Read
Information can be read from any block, identifier codes or status register independent of the VPP
voltage. #RESET can be at VIH.
The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial device power-up or after exit from reset mode, the
device automatically resets to read array mode. Six control pins dictate the data flow in and out of the
component: #CE, #OE, #BYTE, #WE, #RESET and #WP. #CE and #OE must be driven active to
obtain data at the outputs. #CE is the device selection control, and when active enables the selected
memory device. #OE is the data output (DQ0 − DQ15) control and when active drives the selected
memory data onto the I/O bus. #BYTE is the device I/O interface mode control. #WE must be at VIH,
#RESET must be at VIH, and #BYTE and #WP must be at VIL or VIH. Figure 16, 17 illustrates read
cycle.
Output Disable
With #OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0 − DQ15) are
placed in a high-impedance state.
Standby
Setting #CE to a logic-high level (VIH) deselects the device and places it in standby mode, which
substantially reduces device power consumption. DQ0 − DQ15 outputs are placed in a high
impedance state independent of #OE. If deselected during block erase, full chip erase, word/byte write
or lock-bit configuration, the device continues functioning, and it continues to consume active power
until the operation is completed.
Reset
Setting #RESET to VIL initiates the reset mode.
In read modes, setting #RESET at VIL deselects the memory, places output drivers in a highimpedance state and turns off all internal circuits. #RESET must be held low for a minimum of 100 nS.
A delay (tPHQV) is required after return from reset until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The CUI is reset to read array mode status register
is set to 80H, and all blocks are locked.
During block erase, full chip erase, word/byte write or lock-bit configuration modes, #RESET at VIL will
abort the operation. RY/#BY remains low until the reset operation is complete. Memory contents at the
aborted location are no longer valid since the data may be partially erased or written. A delay (tPHWL) is
required after #RESET goes to logic-high (VIH) before another command can be written.
As with any automated device, it is important to assert #RESET during system reset. When the
system comes out of reset, it expects to read from the flash memory. Automated flash memories
provide status information when accessed during block erase, full chip erase, word/byte write or lockbit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization
may not occur because the flash memory may be providing status information instead of array data.
Winbond’s flash memories allow proper CPU initialization following a system reset through the use of
- 10 -
W28J800B/T
the #RESET input. In this application, #RESET is controlled by the same #RESET signal that resets
the system CPU.
Read Identifier Codes
The read identifier codes operation outputs the manufacturer code, device code, block lock
configuration codes for each block and the permanent lock configuration code (see Figure 4). Using
the manufacturer and device codes, the system CPU can automatically match the device with its
proper algorithms. The block lock and permanent lock configuration codes identify locked and
unlocked blocks and permanent lock-bit setting.
- 11 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
[A18-A0]
7FFFF
7F003
7F002
7F001
7F000
7EFFF
7E003
7E002
7E001
7E000
7DFFF
7D003
7D002
7D001
7D000
7CFFF
79000
78FFF
78003
78002
78001
78000
77FFF
70003
7002
7001
7000
6FFF
08000
07FFF
01000
00FFF
00080
0007F
Top Boot
Reserved for Future Implementation
Boot Block 0 Lock Configuration Code
Reserved for Future Implementation
Boot Block0
Reserved for Future Implementation
Boot Block 1 Lock Configuration Code
Reserved for Future Implementation
Boot Block1
Reserved for Future Implementation
Parameter Block 0 Lock Configuration Code
Reserved for Future Implementation
Parameter Block0
(Parameter Blocks 1 through 4)
Reserved for Future Implementation
Parameter Block 5 Lock Configuration Code
Reserved for Future Implementation
Parameter Block5
Reserved for Future Implementation
Main Block 6 Lock Configuration Code
Reserved for Future Implementation
Mani Block0
Reserved for Future Implementation
OTP Block
Reserved for Future Implementation
Permanent Lock Configuration Code
00002
Main Block 14 Lock Configuration Code
00000
[A18-A0]
FFFFF
7FFFF
FE006
FE005
FE004
FE003
FE000
FDFFF
78003
78002
78001
FC006
FC005
FC004
FC003
FC000
FBFFF
10000
0FFFF
78000
77FFF
0C003
0C002
0C001
FA006
FA005
FA004
FA003
FA000
F9FFF
0C000
07FFF
F2000
F1FFF
07000
06FFF
F0006
F0005
F0004
F0003
03000
02FFF
07003
07002
07001
02003
02002
02001
F0000
EFFFF
E0006
E0005
E0004
E0003
E0000
DFFFF
02000
01FFF
01003
01002
01001
(Main Blocks 1 through 13)
00004
00003
00001
[A18-A1]
Device Code
Manufacturer Code
Mani Block 14
10000
0FFFF
01000
02000
01FFF
00080
0007F
Bottom Boot
Reserved for Future Implementation
Main Block 14 Lock Configuration Code
Reserved for Future Implementation
Main Block14
(Main Blocks 1 through 13)
Reserved for Future Implementation
Main Block 0 Lock Configuration Code
Reserved for Future Implementation
Mani Block0
Reserved for Future Implementation
Parameter Block 5 Lock Configuration Code
Reserved for Future Implementation
Parameter Block5
(Parameter Blocks 1 through 4)
Reserved for Future Implementation
Parameter Block 0 Lock Configuration Code
Reserved for Future Implementation
Parameter Block0
Reserved for Future Implementation
Boot Block 1 Lock Configuration Code
Reserved for Future Implementation
Boot Block1
00FFF
00100
000FF
00008
00007
00006
00005
00004
00003
00002
00001
00000
00004
OTP Block
00003
Permanent Lock Configuration Code
00002
Boot Block 0 Lock Configuration Code
00000
Device Code
Manufacturer Code
F0006
F0005
F0004
F0003
F0000
EFFFF
20000
1FFFF
01006
10005
10004
10003
10000
0FFFF
0E006
0E005
0E004
0E003
0E000
0DFFF
06000
05FFF
04006
04005
04004
04003
04000
03FFF
02006
02005
02004
02003
02000
01FFF
00100
000FF
Reserved for Future Implementation
00001
[A18-A1]
FFFFF
Boot Block 0
00008
00007
00006
00005
00004
00003
00002
00001
00000
Figure 4. Device Identifier Code Memory Map
OTP (One Time Program) Block
The OTP block is a special block that can not be erased. The block is divided into two parts. One is a
factory program area where a unique number can be written according to customer requirements in
Winbond factory. This factory program area is "READ ONLY" (Already locked). The other is a
customer program area that can be used by customers. This customer program area can be locked.
After locking, this customer program area is protected permanently.
- 12 -
W28J800B/T
The OTP block is read in Configuration Read Mode by writing Read Identifier Codes command(90H).
To return to Read Array Mode, write Read Array command(FFH).
The OTP block is programmed by writing OTP Program command(C0H). First write OTP Program
command and then write data with address to the device (See Figure 5). If OTP program is failed,
SR.4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is
locked, SR.1(DEVICE PROTECT STATUS) bit is set to "1" too.
The OTP block is also locked by writing OTP Program command(C0H). First write OTP Program
command and then write data "FFFDH" with address "80H" to the device. Address "80H" of OTP block
is OTP lock information. Bit 0 of address "80H" means factory program area lock status("1" is "NOT
LOCKED", "0" is "LOCKED"). Bit 1 of address "80H" means customer program area lock status. The
OTP lock information can not be cleared, after once it is set.
[A18-A0]
[A18-A1]
01FFF
00FFF
Customer Program Area
0010A
00109
00085
00084
Factory Program Area
00102
00081
00080
00100
OTP Lock
Customer Program Area Lock(Bit 1)
Factory Program Area Lock(Bit 1)
Figure 5. OTP Block Address Map
Write
Writing commands to the CUI enable reading of device data and identifier codes. They also control
inspection and clearing of the status register. When VDD = 2.7V to 3.6V and VPP = VPPH1/2, the CUI
additionally controls block erase, full chip erase, word/byte write and lock-bit configuration.
The Block Erase command requires appropriate command data and an address within the block to be
erased. The Full Chip Erase command requires appropriate command data and an address within the
device. The Word/Byte Write command requires the command and address of the location to be
written. Set Permanent and Block Lock-Bit commands require the command and address within the
device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block LockBits command requires the command and address within the device.
The CUI does not occupy an addressable memory location. A write occurs when #WE and #CE are
active (low). The address and data needed to execute a command are latched on the rising edge of
#WE or #CE, whichever occurs first. Standard microprocessor write timings are used.
Figures 18 and 19 illustrate #WE and #CE controlled write operations.
- 13 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
9. COMMAND DEFINITIONS
When VPP ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled.
Setting VPPH1/2 = VPP enables successful block erase, full chip erase, word/byte write and lock-bit
configuration operations.
Device operations are selected by writing specific commands into the CUI. Table 3 defines these
commands.
Table 2.1. Bus Operations (#BYTE = VIH) (Note 1, 2)
MODE
ADDRESS
VPP
VIH
X
X
DOUT
X
VIH
X
X
High Z
X
X
X
X
X
High Z
X
X
X
X
X
X
High Z
High Z
VIH
VIL
VIL
VIH
See
Figure 4, 5
X
Note 5
High Z
VIH
VIL
VIH
VIL
X
X
DIN
X
#RESET
#CE
#OE
#WE
Read (Note 8)
VIH
Output Disable
VIH
VIL
VIL
VIL
VIH
Standby
VIH
VIH
Reset (note 4)
VIL
Read Identifier
Codes (Note 8)
Write (Note 6, 7, 8)
DQ0-15
RY/#BY(3)
Table 2.2. Bus Operations (#BYTE = VIL) (Note 1, 2)
MODE
Read (Note 8)
#RESET
#CE
#OE
#WE
ADDRESS
VPP
DQ0-15
RY/#BY(3)
VIH
VIL
VIL
VIH
X
X
DOUT
X
Output Disable
VIH
VIL
VIH
VIH
X
X
High Z
X
Standby
VIH
VIH
X
X
X
X
High Z
X
Reset (note 4)
VIL
X
X
X
X
X
High Z
High Z
Read Identifier
Codes (Note 8)
VIH
VIL
VIL
VIH
See
Figure 4, 5
X
Note 5
High Z
Write (Note 6, 7, 8)
VIH
VIL
VIH
VIL
X
X
DIN
X
Notes:
1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK voltages.
3. RY/#BY is VOL when the WSM is executing internal block erase, full chip erase, word/byte write or lock-bit configuration
algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive),
word/byte write suspend mode or reset mode.
4. #RESET at VSS ±0.2V ensures the lowest power consumption.
5. See Read Identifier Codes Command section for details.
6. Command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed when
VPP = VPPH1/2 and VDD = 2.7V to 3.6V.
7. Refer to Table 3 for valid DIN during a write operation.
8. Never hold #OE low and #WE low at the same timing.
- 14 -
W28J800B/T
Table 3. Command Definitions(10)
COMMAND
Read Array/Reset
BUS CYCLES FIRST BUS CYCLE
REQ’D.
Oper(1) Addr(2)
SECOND BUS CYCLE
Data(3)
Oper(1)
Addr(2)
Data(3)
1
Write
X
FFH
Read Identifier Codes
≥2 (Note 4)
Write
X
90H
Read
IA
ID
Read Status Register
2
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
2 (Note 5)
Write
X
20H
Write
BA
D0H
Full Chip Erase
2
Write
X
30H
Write
X
D0H
Word/Byte Write
2 (Note 5, 6)
Write
X
40H or
10H
Write
WA
WD
Block Erase and Word/Byte
Write Suspend
1 (Note 5)
Write
X
B0H
Block Erase and Word/Byte
Write Resume
1 (Note 5)
Write
X
D0H
Set Block Lock-Bit
2 (Note 8)
Write
X
60H
Write
BA
01H
2 (Note 7, 8)
Write
X
60H
Write
X
D0H
2 (Note 9)
Write
X
60H
Write
X
F1H
2
Write
X
C0H
Write
OA
OD
Block Erase
Clear Block Lock-Bits
Set Permanent Lock-Bit
OTP Program
Notes:
1. BUS operations are defined in Table 2.1 and Table 2.2.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 4.
BA = Address within the block being erased.
WA = Address of memory location to be written.
OA = Address of OTP block to be written: see Figure 5.
3. ID = Data read from identifier codes.
SRD = Data read from status register. See Table 6 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first).
OD = Data to be written at location OA. Data is latched on the rising edge of #WE or #CE (whichever goes high first).
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and
permanent lock configuration codes. See Read Identifier Codes Command section for details.
5. If #WP is VIL, boot blocks are locked without block lock-bits state. If #WP is VIH, boot blocks are locked by block lockbits. The
parameter and main blocks are locked by block lock-bits without #WP state.
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
9. Once the permanent lock-bit is set, permanent lock-bit reset is unable.
10. Commands other than those shown above are reserved by Winbond for future device implementations and should not be
used.
- 15 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Read Array Command
Upon initial device power-up and after exit from reset mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array command. The device remains enabled for
reads until another command is written. Once the internal WSM has started a block erase, full chip
erase, word/byte write or lock-bit configuration the device will not recognize the Read Array command
until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or
Word/Byte Write Suspend command. The Read Array command functions independently of the VPP
voltage and #RESET can be VIH.
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the
command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device,
block lock configuration and permanent lock configuration codes (see Table 4 for identifier code
values). To terminate the operation, write another valid command. Like the Read Array command, the
Read Identifier Codes command functions independently of the VPP voltage and #RESET can be VIH.
Following the Read Identifier Codes command, the following information can be read:
Table 4. Identifier Codes
CODE
Manufacture Code
Device Code
ADDRESS(2)
[A18 − A0]
00000H
Top Boot
Bottom Boot
00001H
DATA(3)
[DQ7 − DQ0]
B0H
ECH
EDH
Block Lock Configuration
• Block is Unlocked
• Block is Locked
• Reserved for Future Use
BA(1)+2
DQ0 = 0
DQ0 = 1
DQ1 − 7
Permanent Lock Configuration
• Device is Unlocked
• Device is Locked ed
• Reserved for Future Use
00003H
DQ0 = 0
DQ0 = 1
DQ1 − 7
Notes:
1. BA selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map.
2. A-1 don’t care in byte mode.
3. DQ15 − DQ8 outputs 00H in word mode.
Read Status Register Command
The status register may be read to determine when a block erase, full chip erase, word/byte write or
lock-bit configuration is complete and whether the operation completed successfully. It may be read at
any time by writing the Read Status Register command. After writing this command, all subsequent
read operations output data from the status register until another valid command is written. The status
register contents are latched on the falling edge of #OE or #CE, whichever occurs last. #OE or #CE
must toggle to VIH before further reads to update the status register latch. The Read Status Register
command functions independently of the VPP voltage. #RESET can be VIH.
- 16 -
W28J800B/T
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate various failure conditions (see Table 6). By
allowing system software to reset these bits, several operations (such as cumulatively erasing multiple
blocks or writing several words/bytes in sequence) may be performed. The status register may be
polled to determine if an error occurred during the sequence.
To clear the status register, the Clear Status Register command (50H) is written. It functions
independently of the applied VPP voltage. #RESET can be VIH. This command is not functional during
block erase or word/byte write suspend modes.
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm. This command sequence requires appropriate
sequencing and an address within the block to be erased (all bits within the block being set to "1").
Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the device automatically outputs status register
data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output
data of the RY/#BY pin or status register bit SR.7.
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued.
This two-step command sequence for set-up, followed by execution, ensures that block contents are
not accidentally erased. An invalid Block Erase command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Additionally, reliable block erasure can only occur when VDD =
2.7V to 3.6V and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected
against erasure. If block erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1".
Successful block erase for boot blocks requires that #WP = VIH and the corresponding block lock-bit
be cleared. In parameter and main blocks cases, it must be cleared via the corresponding block
lock-bit. If block erase is attempted when the excepting above conditions, SR.1 and SR.5 will be set to
"1".
Full Chip Erase Command
This command followed by a confirm command erases all of the unlocked blocks. A full chip erase
setup (30H) is first written, followed by a full chip erase confirm (D0H). After a confirm command is
written, device erases the all unlocked blocks block by block. This command sequence requires
appropriate sequencing. Block preconditioning, erase and verify are handled internally by the WSM
(invisible to the system). After the two-cycle full chip erase sequence is written, the device
automatically outputs status register data when can be read (see Figure 7). The CPU can detect full
chip erase completion by analyzing the output data of the RY/#BY pin or status register bit SR.7.
When the full chip erase is complete, status register bit SR.5 should be checked. If erase error is
detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued. If error is detected on a
block during full chip erase operation, WSM stops erasing. Full chip erase operation start from lower
address block, finish the higher address block. Full chip erase can not be suspended.
- 17 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
This two-step command sequence of set-up followed by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when VDD = 2.7V to
3.6V and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against
erasure. If full chip erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". Successful
full chip erase requires for boot blocks that #WP is VIH and the corresponding block lock-bit be
cleared. In parameter and main blocks case, it must clear the corresponding block lock-bit. If all blocks
are locked, SR.1 and SR.5 will be set to "1".
Word/Byte Write Command
Word/Byte write is executed by a two-cycle command sequence. Word/Byte write setup (standard
40H or alternate 10H) is written, followed by a second write that specifies the address and data
(latched on the rising edge of #WE). The WSM then takes over, controlling the word/byte write and
write verify algorithms internally. After the word/byte write sequence is written, the device
automatically outputs status register data when read (see Figure 7). The CPU can detect the
completion of the word/byte write event by analyzing the RY/#BY pin or status register bit SR.7.
When word/byte write is complete, status register bit SR.4 should be checked. If a word/byte write
error is detected, the status register should be cleared. The internal WSM verify only detects errors for
"1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it
receives another command.
Reliable word/byte writes can only occur when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the absence of
this high voltage, memory contents are protected against word/byte writes. If word/byte write is
attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte
write for boot blocks requires that #WP = VIH and the corresponding block lock-bit be cleared. In
parameter and main blocks case, the corresponding block lock-bit must be cleared. If word/byte write
is attempted under these conditions, SR.1 and SR.4 will be set to "1".
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data that must be read after the Block Erase Suspend
command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1"). RY/#BY will also transition to High Z. The
period tWHRZ2 defines the block erase suspend latency.
When Block Erase Suspend command writes to the CUI, if block erase is finished, the device is
placed in read array mode. Therefore, after Block Erase Suspend command writes to the CUI, Read
Status Register command (70H) has to write to CUI, and then status register bit SR.6 should be
checked to confirm that the device is in suspend mode. At this point, a Read Array command can be
written to read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued during erase suspend to program data in
other blocks. Using the Word/Byte Write Suspend command (see Word/Byte Write Suspend
Command section), a word/byte write operation can also be suspended. During a word/byte write
operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/#BY output
will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status.
The only other valid commands while block erase is suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will
- 18 -
W28J800B/T
continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and
RY/#BY will return to VOL. After the Erase Resume command is written, the device automatically
outputs status register data when read (see Figure 9). VPP must remain at VPPH1/2 (the same VPP level
used for block erase) while block erase is suspended. #RESET must also remain at VIH. #WP must
also remain at VIL or VIH (the same #WP level used for block erase). Block erase cannot resume until
word/byte write operations initiated during block erase suspend have completed.
If the time from Block Erase Resume command write to the CUI till Block Erase Suspend command
write to the CUI is short, it can be repeated. In addition, erase time be prolonged.
Word/Byte Write Suspend Command
The Word/Byte Write Suspend command allows word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process starts, sending the Word/Byte Write Suspend
command causes the WSM to suspend the Word/Byte write sequence at a predetermined point in the
algorithm. The device continues to output status register data when read after the Word/Byte Write
Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the
word/byte write operation has been suspended (both will be set to "1"). RY/#BY will also transition to
High Z. The period tWHRZ1 defines the word/byte write suspend latency parameters.
When Word/Byte Write Suspend command writes to the CUI, the device is placed in read array mode
if word/byte write is finished. Therefore, after Word/Byte Write Suspend command writes to the CUI,
the Read Status Register command (70H) has to write to CUI, then status register bit SR.2 should be
checked to confirm the device is in suspend mode.
At this point, a Read Array command can be written to read data from locations other than that which
is suspended. The only other valid commands while word/byte write is suspended are Read Status
Register and Word/Byte Write Resume. After Word/Byte Write Resume command is written to the
flash memory, the WSM will continue the word/byte write process. Status register bits SR.2 and SR.7
will automatically clear and RY/#BY will return to VOL. After the Word/Byte Write Resume command is
written, the device automatically outputs status register data when read (reference Figure 9). VPP must
remain at VPPH1/2 (the same VPP level used for word/byte write) while in word/byte write suspend mode.
#RESET must also remain at VIH. #WP must also remain at VIH or VOL (the same #WP level used for
word/byte write).
If the period from Word/Byte Write Resume command write to Word/Byte Write Suspend command
write is too short, it can be repeated, and the write time will be prolonged.
Set Block and Permanent Lock-bit Commands
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a
permanent lock-bit and #WP pin. The block lock-bits and #WP pin gates program and erase
operations while the permanent lock-bit gates block-lock bit modification. With the permanent lock-bit
not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set
Permanent Lock-Bit command sets, sets the permanent lock-bit. After the permanent lock-bit is set,
block lock-bits and locked block contents cannot altered. See Table 5 for a summary of hardware and
software write protection options.
Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The set
block or permanent lock-bit setup along with appropriate block or device address is written followed by
either the set block lock-bit confirm (and an address within the block to be locked) or the set
permanent lock-bit confirm (and any device address). The WSM then executes the set lock-bit
algorithm. After the sequence is written, the device automatically outputs status register data when
- 19 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
read (see Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing the
RY/#BY pin output or status register bit SR.7.
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The CUI will remain in read status register mode until
a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set.
An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5
being set to "1". Also, reliable operations occur only when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the
absence of this high voltage, lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the permanent lock-bit be cleared. If it is
attempted with the permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail.
Clear Block Lock-bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. If the permanent
lock-bit is not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the
permanent lock-bit is set, block lock-bits cannot be cleared. Refer to Table 5 for a summary of
hardware and software write protection options.
Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the device automatically outputs status register
data when read (refer to Figure 11). The CPU can detect completion of the clear block lock-bits event
by reading the RY/#BY Pin output or status register bit SR.7.
When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur
when VDD = 2.7V to 3.6V and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block lock-bits operation requires that the
permanent lock-bit is not set. If it is attempted with the permanent lock-bit set, SR.1 and SR.5 will be
set to "1" and the operation will fail.
If a clear block lock-bits operation is aborted due to VPP or VDD transitioning out of valid range or
#RESET is toggled, block lock-bit values are left in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit
is set, it cannot be cleared.
- 20 -
W28J800B/T
OTP Program Command
OTP program is executed by a two-cycle command sequence. OTP program command(C0H) is
written, followed by a second write cycle that specifies the address and data (latched on the rising
edge of #WE). The WSM then takes over, controlling the OTP program and program verify algorithms
internally. After the OTP program command sequence is completed, the device automatically outputs
status register data when read (see Figure 13). The CPU can detect the completion of the OTP
program by analyzing the output data of the RY/#BY pin or status register bit SR.7.
When OTP program is completed, status register bit SR.4 should be checked. If OTP program error is
detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s
that do not successfully program to "0"s. The CUI remains in read status register mode until it receives
other commands.
Reliable OTP program can be executed only when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the
absence of this voltage, memory contents are protected against OTP programs. If OTP program is
attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 is set to "1". If OTP write is attempted
when the OTP Lock-bit is set, SR.1 and SR.4 is set to "1".
Block Locking by the #WP
This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure while other blocks are programmed or erased as
necessary.
The lockable two boot blocks are locked when #WP = VIL; any program or erase operation to a locked
block will result in an error, which will be reflected in the status register. For top configuration, the top
two boot blocks are lockable. For the bottom configuration, the bottom two boot blocks are lockable. If
#WP is VIH and block lock-bit is not set, boot block can be programmed or erased normally (Unless
VPP is below VPPLK). #WP is valid only two boot blocks, other blocks are not affected.
- 21 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Table 5. Write Protection Alternatives(1)
OPERATION
VPP
≤ VPPLK
Block Erase
or Word/Byte
Write
> VPPLK
#RESET
PERMANENT BLOCK
LOCK-BIT LOCK-BIT
X
X
X
VIL
X
X
X
0
VIH
X
1
≤ VPPLK
Full Chip
Erase
> VPPLK
≤ VPPLK
Set Block LockBit
> VPPLK
≤ VPPLK
Clear Block
Lock-Bits
> VPPLK
≤ VPPLK
Set Permanent
Lock-Bit
> VPPLK
#WP
EFFECT
All Blocks Locked.
X
All Blocks Locked.
VIL
2 Boot Blocks Locked.
VIH
Block Erase and Word/Byte Write Enabled.
VIL
Block Erase and Word/Byte Write Disabled.
VIH
Block Erase and Word/Byte Write Disabled.
X
X
X
X
VIL
X
X
X
All Blocks Locked.
VIL
All Unlocked Blocks are Erased.
2 Boot Blocks and Locked Blocks are NOT
Erased.
VIH
All Unlocked Blocks are Erased.
Locked Blocks are NOT Erased.
VIH
X
X
All Blocks Locked.
X
X
X
X
Set Block Lock-Bit Disabled.
VIL
X
X
X
Set Block Lock-Bit Disabled.
0
X
X
Set Block Lock-Bit Disabled.
VIH
1
X
X
Set Block Lock-Bit Disabled.
X
X
X
X
Clear Block Lock-Bits Disabled.
VIL
X
X
X
Clear Block Lock-Bits Disabled.
VIH
X
0
X
X
Clear Block Lock-Bits Enabled.
1
X
X
Clear Block Lock-Bits Disabled.
X
X
X
Set Permanent Lock-Bit Disabled.
VIL
X
X
X
Set Permanent Lock-Bit Disabled.
VIH
X
X
X
Set Permanent Lock-Bit Enabled.
Note: X can be VIL or VIH for #RESET and #WP, and "0" or "1" for permanent lock-bit and block lock-bit. See DC Characteristics
for VPPLK voltage.
- 22 -
W28J800B/T
Table 6. Status Register Definition
WSMS
BESS
ECBLBS
WBWSLBS
VPPS
WBWSS
DPS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check RY/#BY or SR.7 to determine block erase, full chip
erase, word/byte write or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 = "0".
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS
(ECBLBS)
1 = Error in Block Erase, Full Chip Erase or Clear Block
Lock-bits
0 = Successful Block Erase, Full Chip Erase or Clear
Block Lock-bits
SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT STATUS
(WBWSLBS)
1 = Error in Word/Byte Write or Set Block/Permanent
Lock-bit
0 = Successful Word/Byte Write or Set Block/Permanent
Lock-bit
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-bit, Permanent Lock-Bit and/or #WP Lock
Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase or lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. SR.3 is not guaranteed
to reports accurate feedback only when VPP ≠ VPPH1/2.
SR.1 does not provide a continuous indication of permanent
and block lock-bit and #WP values. The WSM interrogates
the permanent lock-bit, block lock-bit and #WP only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
set, permanent lock-bit is set and/or #WP is VIL. Reading the
block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
- 23 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Bus Operation Command
Read Status
Write
Register
Read
Start
Write 70H
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Read Status
Register
0
SR.7=
1
Write
Erase Setup
Write
Erase
Confirm
Write 20H
Read
Write D0H,
Block Address
Standby
Suspend Block
Erase Loop
Suspend
Block Erase
0
SR.7=
Data = 20H
Addr = X
Data = D0H
Addr = Within Block to
be Erased
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures. Full status
check can be done after each block erase or after a
sequence of block erasures. Write FFH after the last
operation to place device in read array mode.
Read Status
Register
No
Comments
Data = 70H
Addr = X
Status Register Data
Yes
1
Full Status
Check if Desired
Block Erase
Complete
Full STATUS CHECK PROCEDURE
Bus Operation Command
Read Status Register
Data(See Above)
Standby
1
SR.3=
Vpp Range Error
Standby
Device Protect Error
Standby
0
SR.1=
1
0
SR.4,5=
1
Command Sequence
Error
Standby
0
SR.5=
1
Comments
Check SR.3
1= VPP Error Detect
Check SR.1
1 = Device Protect
Detect
Check SR.4, 5
Both 1 = Command
Sequence Error
Check SR.5
1 = Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the
Clear Status Register Command in cases where
multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Block Erase Error
0
Block Erase
Sucessfully
Figure 6. Automated Block Erase Flowchart
- 24 -
W28J800B/T
Bus Operation
Start
Write
Read
Write 70H
Write
0
1
Write
Write 30H
Full Chip
Erase
Setup
Full Chip
Erase
Confirm
SR.7=
Data = 30H
Addr = X
Data = D0H
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write D0H
Read Status
Register
Comments
Data = 70H
Addr = X
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Read Status
Register
SR.7=
Command
Read Status
Register
Full status check can be done after each full chip erase.
Write FFH after the last operation to place device in read
array mode.
0
1
Full Status
Check if Desired
Full Chip Erase
Complete
Full STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus Operation
1
SR.3=
Standby
Vpp Range Error
0
SR.1=
Standby
1
Device Protect Error
0
SR.4,5=
1
SR.5=
1
Full Chip Erase Error
Comments
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
(All Blocks are locked)
Standby
Check SR.4, 5
Both 1 = Command
Sequence Error
Standby
Check SR.5
1 = Full Chip Erase Error
Command Sequence
Error
0
Command
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register Command in cases where multiple
blocks are erased before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
0
Full Chip Erase
Successfully
- 25 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Figure 7. Automated Full Chip Erase Flowchart
Start
Bus Operation
Command
Comments
Write
Read Status
Register
Data = 70H
Write 70H
Read Status
Register
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
SR.7=
Write
1
Setup
Word/Byte
Write
Write 40H or 10H
Write
Write Word/Byte
Data and Adddress
Read Status
Register
Suspend Word/Byte
Write Loop
No
0
SR.7=
Suspend
Word/Byte
Write
1
Yes
Word/Byte
Write
Data = 40H or 10H
Addr = X
Data = Data to Be Written
Addr = Location to Be
written
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent word/byte writes.
SR full status check can be done after each word/byte
write, or after a sequence of word/byte writes.
Full Status
Check if Desired
Write FFH after the last word/byte write operation to place
device in read array mode.
Word/Byte Write
Complete
Full STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus Operation
Command
Standby
SR.3=
1
Vpp Range Error
Standby
0
SR.1=
1
Device Protect Error
Standby
0
1
SR.4=
0
Word/Byte Write
Successfully
Word/Byte Write Error
Comments
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
Check SR.4
1 = Data Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 8. Automated Word/Byte Write Flowchart
- 26 -
W28J800B/T
Start
Bus Operation Command
Write
Write B0H
Read
Read Status
Register
SR.7=
Erase
Suspend
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
0
1
SR.6=
0
Block Erase
Complete
Standby
1
Read
Read Array Data
Read or
Word/Byte
Write?
No
Word/Byte write
Write
Wore/Byte Write Loop
Comments
Data = B0H
Addr = X
Status Register Data
Addr = X
Erase
Resume
Check SR.6
1 = Block Erase
Suspended
0 = Block Erase
Completed
Data = D0H
Addr = X
Done?
Yes
Write D0H
Block Erase
Resumed
Write FFH
Read Array Data
Figure 9. Block Erase Suspend/Resume Flowchart
- 27 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Start
Bus Operation
Write
Write B0H
Read
Read Status
Register
SR.7=
0
0
Word/Byte Write
Completed
Standby
1
Write FFH
Write
Read Array Data
Read
Write
Done
Reading
Check SR.2
1 = Word/Byte Write
Suspended
0 = Word/Byte Write
Completed
Data = FFH
Read Array
Addr = X
Read Array locations other
than that being written.
Word/Byte Write
Data = D0H
Resume
Addr = X
Yes
Write D0H
Word/Byte Write
Resumed
Write FFH
Read Array Data
Figure 10. Word/Byte Write Suspend/Resume Flowchart
- 28 -
Comments
Data = B0H
Addr = X
Status Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
1
SR.2=
Command
Word/Byte Write
Suspend
W28J800B/T
Bus Operation
Start
Write
Read
Write 70H
0
Write
Set
Block/Permanent
Lock-bit Setup
Write
Set Block or
Permanent
Lock-bit Confirm
1
Write 60H
Write 01H/F1H
Block/Device Address
Read
SR.7=
Data = 60H
Addr = X
Data = 01H(Block),
F1H(Permanent)
Addr = Block
Address(Block),
Device Address(Permanent)
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Read Status
Register
Comments
Data = 70H
Addr = X
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Read Status
Register
SR.7=
Command
Read Status
Register
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
0
1
Full Status
Check if Desired
Set Lock-Bit
Complete
Full STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Vpp Range Error
0
SR.1=
1
Standby
1
Command Sequence
Error
0
SR.4=
0
Set Lock-Bit
Successfully
Standby
Device Protect Error
0
SR.4,5=
Command
Standby
1
SR.3=
Bus Operation
Standby
1
Set Lock-Bit Error
Comments
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
Permanent Lock-bit is Set
(Set Block Lock-Bit
Operation)
Check SR.4, 5
Both 1 = Command
Sequence Error
Check SR.4
1 = Set Lock-bit Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple lock-bits
are set before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 11. Set Block and Permanent Lock-bit Flowchart
- 29 -
W28J800B/T
Bus Operation
Start
Write
Read
Write 70H
Write
0
1
Write
Write 60H
Comments
Data = 70H
Addr = X
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Read Status
Register
SR.7=
Command
Read Status
Register
Clear Block
Lock-Bits
Setup
Clear Block
Lock-Bits
Confirm
Data = 60H
Addr = X
Data = D0H
Addr = X
Read
Status Register Data
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Write FFH after the Clear Block Lock-Bits operation to
place device in read array mode.
Write D0H
Read Status
Register
SR.7=
0
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
Full STATUS CHECK PROCEDURE
Bus Operation
Read Status Register
Data(See Above)
Standby
1
SR.3=
Vpp Range Error
Standby
0
SR.1=
1
Device Protect Error
Standby
0
SR.4,5=
1
Command Sequence
Error
Standby
0
SR.5=
1
Command
Comments
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
Permanent Lock-Bit is Set
Check SR.4, 5
Both 1 = Command
Sequence Error
Check SR.5
1 = Clear Block Lock-Bits
Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command. If error is detected, clear the
Status Register before attempting retry or other error
recovery.
Clear Block Lock-Bits
Error
0
Clear Block Lock-Bits
Successfully
Figure 12. Clear Block Lock-Bits Flowchart
- 30 -
W28J800B/T
Start
Bus Operation
Write
Write 70H
Command
Read Status
Register
Read
Read Status
Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Data = C0H
Addr = X
Data = Data to Be Written
Write
OTP Program Addr = Location to Be
Written
Read
Status Register Data
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent OTP programs.
SR full status check can be done after each OTP program,
or after a sequence of OTP programs.
Write FFH after the last OTP program operation to place
device in read array mode.
0
SR.7=
Setup OTP
Program
Write
1
Write C0H
Write Data
and Address
Read Status
Register
0
SR.7=
Comments
Data = 70H
Addr = X
Status Register Data
1
Full Status
Check if Desired
OTP Program
Complete
Full STATUS CHECK PROCEDURE
Bus Operation
Read Status Register
Data(See Above)
SR.3=
Command
Standby
1
Vpp Range Error
Standby
Device Protect Error
Standby
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
Permanent Lock-Bit is Set
0
SR.1=
1
Check SR.4
1 = Data Write Error
0
SR.4=
0
OTP Program
Sucessfully
1
OTP Program
Sucessfully
Comments
Check SR.3
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated OTP Program Flowchart
- 31 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
- 32 -
W28J800B/T
10. DESIGN CONSIDERATIONS
Three-line Output Control
This device will often be used in large memory arrays. Winbond provides three control inputs to
accommodate multiple memory connections. Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable #CE while #OE should be
connected to all memory devices and the system’s READ control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in standby mode. #RESET
should be connected to the system POWERGOOD signal to prevent unintended writes during system
power transitions. POWERGOOD should also toggle during system reset.
RY/#BY and WSM Polling
RY/#BY is an open drain output that should be connected to VDD by a pull up resistor to provides a
hardware method of detecting block erase, full chip erase, word/byte write and lock-bit configuration
completion. It transitions low after block erase, full chip erase, word/byte write or lock-bit configuration
commands and returns to VOH (while RY/#BY is pull up) when the WSM has finished executing the
internal algorithm.
RY/#BY can be connected to an interrupt input of the system CPU or controller. It is active at all times.
RY/#BY is also high impedance when the device is in block erase suspend (with word/byte write
inactive), word/byte write suspend or reset modes.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers
are interested in three supply current issues; standby current levels, active current levels and transient
peaks produced by falling and rising edges of #CE and #OE. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 µF ceramic capacitor connected between VDD and VSS and between
VPP and VSS. These high frequency, low inductance capacitors should be placed as close as possible
to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed
at the array’s power supply connection between VDD and VSS. The bulk capacitor will overcome
voltage drops caused by PC board trace inductance.
VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target system requires that the printed circuit board
designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for
word/byte writing and block erasing. Use similar trace widths and layout considerations given to the
VDD power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and
overshoots.
VDD, VPP, #RESET Transitions
Block erase, full chip erase, word/byte write and lock-bit configuration are not guaranteed if VPP falls
outside of a valid VPPH1/2 range, VDD falls outside of a valid 2.7V to 3.6V range, or #RESET ≠ VIH. If VPP
error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the
- 33 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
attempted operation. If #RESET transitions to VIL during block erase, full chip erase, word/byte write or
lock-bit configuration, RY/#BY will remain low until the reset operation is complete. Then, the
operation will abort and the device will enter reset mode. The aborted operation may leave data
partially altered. Therefore, the command sequence must be repeated after normal operation is
restored. Device power-off or #RESET transitions to VIL clear the status register.
The CUI latches commands issued by system software and is not altered by VPP or #CE transitions or
WSM actions. Its state is read array mode upon power-up, after exit from reset mode or after VDD
transitions below VLKO.
Power-up/Down Protection
The device is designed to offer protection against accidental block erase, full chip erase, word/byte
write or lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to
which power supply (VPP or VDD) powers-up first. Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious writes for VDD voltages above VLKO when VPP is active.
Since both #WE and #CE must be low for a command write, driving either to VIH will inhibit writes. The
CUI’s two step command sequence architecture provides added level of protection against data
alteration.
In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled
while #RESET = VIL regardless of its control inputs state.
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only
during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed.
Data Protection Method
On some systems, noise having a level exceeding the limit dictated in the specification may be
generated under specific operating conditions. Such noise, when induced onto #WE signal or power
supply, may be interpreted as false commands, causing undesired memory updating. To protect the
data stored in the flash memory against undesired overwriting, systems operating with the flash
memory should have the following write protect designs, as appropriate:
1) Protecting data in specific block
When a lock bit is set, the corresponding block (includes the 2 boot blocks) is protected against
overwriting. By setting a #WP low, only the 2 boot blocks can be protected against overwriting. By
using this feature, the flash memory space can be divided into the program section (locked section)
and data section (unlocked section). The permanent lock bit can be used to prevent false block bit
setting. For further information on setting/resetting lock-bit, refer to the specification.
2) Data protection through VPP
When the level of VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is
disabled. All blocks are locked and the data in the blocks are completely write protected. For the
lockout voltage, refer to the specification.
- 34 -
W28J800B/T
3) Data protection through #RESET
When the #RESET is kept low during read mode, the flash memory will be in reset mode, write
protecting all blocks. When the #RESET is kept low during power up and power down sequence
such as voltage transition, write operation on the flash memory is disabled, write protecting all
blocks. For the details of #RESET control, refer to the specification.
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase, Full Chip Erase, Word/Byte Write
and Lock-Bit Configuration ........................................................................................... -40° C to +85° C (1)
......................................................................................................................................... 0° C to +70° C (1)
Storage Temperature
During under Bias .............................. ............................................................................... -10° C to +80° C
During non Bias .............................. ................................................................................... -65° C to +125° C
Voltage On Any Pin
(except VDD and VPP) ......... ...................................................................................... .. -0.5V to VDD +0.5V (2)
VDD Supply Voltage......................... .............................................................................. ....... -0.2V to +4.6V (2)
VPP Supply Voltage..................................................................................................... .... -0.2V to +13.0V (2, 3)
Output Short Circuit Current............. ................................................................................................100 mA (4)
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress
ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond
the "Operating Conditions" may affect device reliability.
Notes:
1. -40° C to +85° C operating temperature is for extended temperature product defined by this specification.
(for W28J800BT/TT90L)
0° C to +70° C operating temperature is for commercial temperature product defined by this specification.
(for W28J800BT/TT90C)
2. All specified voltages are with respect to VSS. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VDD and VPP
pins. During transitions, this level may undershoot to -2.0V for periods <20 nS. Maximum DC voltage on input/output pins are
VDD +0.5V which, during transitions, may overshoot to VDD +2.0V for periods <20 nS.
3. Maximum DC voltage on VPP may overshoot to +13.0V for periods <20 nS. Applying 12V ±0.3V to VPP during erase/write can
only be done for a maximum of 1000 cycles on each block. VPP may be connected to 12V ±0.3V for a total of 80 hours
maximum.
4. Output shorted for no more than one second. No more than one output shorted at a time.
Operating Conditions
Temperature and VDD Operating Conditions
SYMBOL
PARAMETER
MIN.
MAX.
W28J800BT/TT90C
0
+70
W28J800BT/TT90L
-40
+85
2.7
3.6
TA
Operating Temperature
VDD
VDD Supply Voltage (2.7V to 3.6V)
- 35 -
UNIT
TEST CONDITION
°C
Ambient
Temperature
V
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Capacitance(1)
TA = +25° C, f = 1 MHz
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
CONDITION
CIN
7
10
pF
VIN = 0.0V
COUT
9
12
pF
VOUT = 0.0V
Input Capacitance
Output Capacitance
Note: Sampled, not 100% tested.
AC Input/Output Test Conditions
2.7
INPUT
TEST POINTS
1.35
1.35 OUTPUT
0.0
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 nS.
Figure 14. Transient Input/Output Reference Waveform for VDD = 2.7V to 3.6V
1.3V
(IN914)
R L =3.3K ohm
DEVICE
UNDER
TEST
OUT
C L Includes Jig Capacitance
CL
Figure 15. Transient Equivalent Testing Load Circuit
Test Configuration Capacitance Loading Value
Test Configuration
CL (pF)
VDD = 2.7V to 3.6V
50
- 36 -
W28J800B/T
DC Characteristics
PARAMETER
TEST
SYM.
CONDITIONS
VDD = 2.7V − 3.6V
Typ.
Max.
UNIT
Input Load Current
(Note 1)
ILI
VDD = VDD Max.
VIN = VDD or VSS
±0.5
µA
Output Leakage Current
(Note 1)
ILO
VDD = VDD Max.
VOUT = VDD or VSS
±0.5
µA
ICCS
CMOS Level Inputs VDD = VDD Max.
#CE = #RESET = VDD ±0.2V
2
15
µA
0.2
2
mA
VDD Standby Current
(Note 1, 3, 6)
TTL Level Inputs VDD = VDD Max.
#CE = #RESET = VIH
VDD Auto Power-save Current
(Note 1, 5, 6)
ICCAS
CMOS Level Inputs VDD = VDD Max.
#CE = VSS ±0.2V
2
15
µA
VDD Reset Power-down Current
(Note 1)
ICCD
#RESET = VSS ±0.2V IOUT(RY/#BY)
= 0 mA CMOS Level Inputs
2
15
µA
ICCR
VDD = VDD Max., #CE = VSS,
f = 5 MHz, IOUT = 0 mA
15
25
mA
30
mA
VDD Read Current (Note 1, 6)
TTL Level Inputs VDD = VDD Max.,
#CE = VSS, f = 5 MHz, IOUT = 0 mA
VPP = 2.7V − 3.6V
5
17
mA
VPP = 11.7V − 12.3V
5
12
mA
VPP = 2.7V − 3.6V
4
17
mA
VPP = 11.7V − 12.3V
4
12
mA
#CE = VIH
1
6
mA
VPP ≤ VDD
±2
±15
µA
VPP > VDD
10
200
µA
ICCWAS
CMOS Level Inputs VDD = VDD Max.
#CE = VSS ±0.2V
0.1
5
µA
VPP Reset Power-down Current
(Note 1)
ICCWD
#RESET = VSS ±0.2V
0.1
5
µA
VPP Word/Byte Write or Set Lock-bit
Current (Note 1, 7)
ICCWW
VPP = 2.7V − 3.6V
12
40
mA
30
mA
VPP Block Erase, Full Chip Erase
or Clear Block Lock-bits Current
(Note 1, 7)
ICCWE
25
mA
20
mA
200
µA
VDD Word/Byte Write or Set Lock-bit
Current (Note 1, 7)
ICCW
VDD Block Erase, Full Chip Erase or
Clear Block Lock-bits Current
(Note 1, 7)
ICCE
VDD Word/Byte Write or Block Erase
Suspend Current (Note 1, 2)
ICCWS
ICCES
VPP Standby or Read Current
(Note 1)
ICCWS
ICCWR
VPP Auto Power-save Current
(Note 1, 5, 6)
VPP Word/Byte Write or Block Erase
Suspend Current (Note 1)
ICCWWS
ICCWES
VPP = 11.7V − 12.3V
VPP = 2.7V − 3.6V
8
VPP = 11.7V − 12.3V
VPP = VPPH1/2
- 37 -
10
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
DC Characteristics (Continued)
PARAMETER
Input Low Voltage (Note 7)
SYM.
TEST
CONDITIONS
VDD = 2.7V − 3.6V
MIN.
MAX.
UNIT
VIL
-0.5
0.8
V
Input High Voltage (Note 7)
VIH
2.0
VDD +0.5
V
Output Low Voltage (Note 3, 7)
VOL
0.4
V
Output High Voltage
(TTL) (Note 7)
Output High Voltage
(CMOS) (Note 7)
VOH1
VOH2
VDD = VDD Min.
IOL = 2.0 mA
VDD = VDD Min.
V
IOH = -2.0 mA
2.4
VDD = VDD Min.
0.85 VDD
V
IOH = -2.5 mA
VDD -0.4
V
VDD = VDD Min.
VPP Lockout during Normal Operations
(Note 4, 7)
VPPLK
VPP during Block Erase, Full ChipErase,
Word/Byte Write or Lock-bit Configuration
Operations
VPPH1
2.7
VPP during Block Erase, Full Chip Erase,
Word/Byte Write or Lock-bit Configuration
Operations (Note 8)
VPPH2
11.7
VDD Lockout Voltage
VLKO
2.0
IOH = -100 µA
1.0
3.6
12.3
V
V
V
V
Notes:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VDD voltage and TA = +25° C.
2. ICCWS and ICCES are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the
device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW , respectively.
3. Includes RY/#BY.
4. Block erases, full chip erase, word/byte writes and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed
in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.).
5. The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more
than 300ns while read mode.
6. About all of pin except describe Test Conditions, CMOS level inputs are either VDD ±0.2V or VSS ±0.2V, TTL level inputs are
either VIL or VIH.
7. Sampled, not 100% tested.
8. Applying 12V ±0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each block. VPP may be
connected to 12V ±0.3V for a total of 80 hours maximum.
- 38 -
W28J800B/T
AC Characteristics - Read-only Operations(1)
VDD = 2.7V to 3.6V, TA = 0° C to +70° C for W28J800BT/TT90C; TA = -40° C to +85° C for W28J800BT/TT90L
PARAMETER
SYM.
Read Cycle Time
tAVAV
Address to Output Delay
tAVQV
TA = 0 to +70° C
MIN.
TA =-40 to +85° C
MAX.
90
MIN.
MAX.
90
90
UNIT
nS
90
nS
#CE to Output Delay (Note 2)
tELQV
90
90
nS
#RESET High to Output Delay
tPHQV
600
600
nS
#OE to Output Delay (Note 2)
tGLQV
40
50
nS
#CE to Output in Low Z (Note 3)
tELQX
#CE High to Output in High Z (Note 3)
tEHQZ
#OE to Output in Low Z (Note 3)
tGLQX
#OE High to Output in High Z (Note 3)
tGHQZ
Output Hold from Address, #CE or #OE Change,
Whichever Occurs First (Note 3)
tOH
0
0
40
0
nS
55
0
15
0
nS
nS
20
0
nS
nS
#BYTE to Output Delay (Note 3)
tFVQV
90
90
nS
#BYTE Low to Output in High Z (Note 3)
tFLQZ
25
30
nS
#CE to #BYTE High or Low (Note3, 4)
tELFV
5
5
nS
Notes:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. #OE may be delayed up to tELQV to tGLQV after the falling edge of #CE without impact on tELQV.
3. Sampled, not 100% tested.
4. If #BYTE transfer during reading cycle, exist the regulations separately.
- 39 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Address(A)
#CE(E)
VIH
Standby
#WE(W)
t AVAV
t EHQZ
VIL
VIH
tGHQZ
VIL
VIH
t GLQV
t ELQV
tELQX
VIL
DATA(D/Q) VOH
(DQ0-DQ15)
VOL
VDD
#RESET(P)
Data Valid
Address Stable
VIL
VIH
#OE(G)
Device
Address Selection
tOH
tGLQX
HIGH Z
Valid Output
t AVQV
t PHQV
VIH
VIL
Figure 16. AC Waveform for Read Operations
- 40 -
HIGH Z
W28J800B/T
Address(A)
#CE(E)
VIH
Standby
Device
Address Selection
Address Stable
VIL
VIH
t AVAV
t ELQV
VIL
t EHQZ
t AVQV
VIH
#OE(G) V
IL
#BYTE(F)
Data Valid
t GLQV
tGHQZ
t FVQV
VIH
tOH
VIL
DATA(D/Q) VOH
(DQ0-DQ7)
VOL
t ELFV
HIGH Z
tGLQX
HIGH Z
Data Output
tELQX
Valid
Output
t FLQZ
DATA(D/Q) VOH
(DQ0-DQ7)
VOL
HIGH Z
HIGH Z
Data Output
Figure 17. #BYTE Timing Waveform
- 41 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
AC Characteristics - Write Operations(1)
VDD = 2.7V to 3.6V, TA = 0° C to +70° C for W28J800BT/TT90C; TA = -40° C to +85° C for W28J800BT/TT90L
PARAMETER
SYMBOL
MIN.
MAX.
Write Cycle Time
tAVAV
90
nS
#RESET High Recovery to #WE Going Low (Note 2)
tPHWL
1
µS
#CE Setup to #WE Going Low
tELWL
10
nS
#WE Pulse Width
tWLWH
50
nS
#WP VIH Setup to #WE Going High (Note 2)
tSHWH
100
nS
VPP Setup to #WE Going High (Note 2)
tVPWH
100
nS
Address Setup to #WE Going High (Note 3)
tAVWH
50
nS
Data Setup to #WE Going High (Note 3)
tDVWH
50
nS
Data Hold from #WE High
tWHDX
0
nS
Address Hold from #WE High
tWHAX
0
nS
#CE Hold from #WE High
tWHEH
10
nS
#WE Pulse Width High
tWHWL
30
nS
#WE High to RY/#BY Going Low or SR.7 Going "0"
tWHRL
Write Recovery before Read
tWHGL
0
nS
VPP Hold from Valid SRD, RY/#BY High Z (Note 2, 4)
tQVVL
0
nS
#WP VIH Hold from Valid SRD, RY/#BY High Z (Note 2, 4)
tQVSL
0
nS
#BYTE Setup to #WE Going High (Note 5)
tFVWH
50
nS
#BYTE Hold from #WE High (Note 5)
tWHFV
90
nS
100
UNIT
nS
Notes:
1. Read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are the
same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration.
4. VPP should be held at VPPH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration
success (SR.1/3/4/5 = 0).
5. If #BYTE switch during reading cycle, exist the regulations separately.
- 42 -
W28J800B/T
2
3
A IN
t AVAV
A IN
t AVWH
1
Address(A)
VIL
VIH
#CE(E)
VIL
DATA(D/Q)
#BYTE(F)
tELWL
tWHEH
t WHGL
t WHWL
VIH
VIL
VIH
HIGH Z
VIL
t PHWL
t WHQV1,2,3,4
t WLWH
t DVWH
t WHDX
Valid
D IN
DIN
t FVWH
SRD
t WHFV
VIL
t WHRL
t
("1")
VOL
("0")
#WP(S)
DIN
VIH
High Z
RY/#BY(R)
6
t WHAX
VIH
#OE(G) V
IL
#WE(W)
5
4
VIH
VIH
t SHWH
t QVSL
t VPWH
t QVVL
VIL
#RESET(P)
VIH
VIL
VPPH1/2
VPP (V)
VPPLK
VIL
Figure 18. AC Waveform for #WE-Controlled Write Operations
Notes:
1. VDD power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
- 43 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Alternative #CE - Controlled Writes(1)
VDD = 2.7V to 3.6V, TA = 0° C to +70° C for W28J800BT/TT90C; TA = -40° C to +85° C for W28J800BT/TT90L
PARAMETER
SYM.
0 TO +70° C
40 TO +85° C
MIN.
MIN.
MAX.
MAX.
UNIT
Write Cycle Time
tAVAV
90
90
nS
#RESET High Recovery to #CE Going Low (Note 2)
tPHEL
1
1
µS
#WE Setup to #CE Going Low
tWLEL
0
0
nS
#CE Pulse Width
tELEH
65
50
nS
#WP VIH Setup to #CE Going High (Note 2)
tSHEH
100
100
nS
VPP Setup to #CE Going High (Note 2)
tVPEH
100
100
nS
Address Setup to #CE Going High (Note 3)
tAVEH
50
50
nS
Data Setup to #CE Going High (Note 3)
tDVEH
50
50
nS
Data Hold from #CE High
tEHDX
0
0
nS
Address Hold from #CE High
tEHAX
0
0
nS
#WE Hold from #CE High
tEHWH
0
0
nS
#CE Pulse Width High
tEHEL
25
30
nS
#CE High to RY/#BY Going Low or SR.7 Going "0"
tEHRL
Write Recovery before Read
tEHGL
0
0
nS
VPP Hold from Valid SRD, RY/#BY High Z (Note 2, 4)
tQVVL
0
0
nS
#WP VIH Hold from Valid SRD, RY/#BY High Z (Note 2, 4)
tQVSL
0
0
nS
#BYTE Setup to #CE Going High (Note 5)
tFVEH
50
50
nS
#BYTE Hold from #CE High (Note 5)
tEHFV
90
90
nS
100
100
nS
Notes:
1. In systems where #CE defines the write pulse width (within a longer #WE timing waveform), all setup, hold, and inactive #WE
times should be measured relative to the #CE waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration.
4. VPP should be held at VPPH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration
success (SR.1/3/4/5 = 0).
5. If #BYTE switch during reading cycle, exist the regulations separately.
- 44 -
W28J800B/T
1
Address(A)
VIL
VIH
#CE(E)
VIL
DATA(D/Q)
#BYTE(F)
3
A IN
t AVAV
t AVWH
t EHAX
tELEH
tDVEH
t EHGL
VIH
VIL
VIH
HIGH Z
VIL
t PHEL
t EHQV1,2,3,4
t EHWH
t WLEL
t EHDX
Valid
DIN
DIN
t FVEH
SRD
#RESET(P)
DIN
t EHFV
VIH
VIL
t EHRL
t
("1")
VOL
("0")
#WP(S)
6
AIN
High Z
RY/#BY(R)
5
4
tEHEL
VIH
#OE(G)
VIL
#WE(W)
2
VIH
VIH
t SHEH
t QVSL
t VPEH
t QVVL
VIL
VIH
VIL
VPPH1/2
VPP (V)
VPPLK
VIL
Figure 19. AC Waveform for #CE-Controlled Write Operations
Notes:
1. VDD power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
- 45 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
Reset Operations
High Z
RY/#BY(R)
("1")
V OL
("0")
#RESET(P)
V IH
V IL
t PLPH
(A)Reset During Read Array Mode
High Z
RY/#BY(R)
("1")
V OL
t PLRZ
("0")
#RESET(P)
V IH
V IL
t PLPH
(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration
2.7V
VDD
#RESET(P)
V IL
t 2VPH
V IH
V IL
(C)#RESET Rising Timing
Figure 20. AC Waveform for Reset Operation
Reset AC Specifications
PARAMETER
SYMBOL
MIN.
#RESET Pulse Low Time (Note 2)
tPLPH
100
#RESET Low to Reset during Block Erase, Full Chip Erase,
Word/Byte Write or Lock-Bit Configuration (Note 1, 2)
tPLRZ
VDD 2.7V to #RESET High (Note 2, 3)
t2VPH
MAX.
nS
30
100
UNIT
µS
nS
Notes:
1. If #RESET is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing,
the reset will complete within 100ns.
2. A reset time, tPHQV, is required from the later of RY/#BY(SR.7) going High Z("1") or #RESET going high until outputs are valid.
Refer to AC Characteristics - Read-Only Operations for tPHQV.
3. When the device power-up, holding #RESET low minimum 100ns is required after VDD has been in predefined range and also
has been in stable there.
- 46 -
W28J800B/T
Block Erase, Full Chip Erase, Word/Byte Write And Lock-Bit Configuration
Performance(3)
VDD = 2.7V to 3.6V, TA = 0° C to +70° C for W28J800BT/TT90C; TA = -40° C to +85° C for W28J800BT/TT90L
SYM.
tWHQV1
tEHQV1
tWHQV2
tEHQV2
PARAMETER
NOTE
VPP = 2.7V − 3.6V
VPP = 11.7V − 12.3V
Min. Typ.(1) Max.
Min. Typ.(1) Max.
UNIT
32K word Block
2
33
200
20
µS
4K word Block
2
36
200
27
µS
64K byte Block
2
31
200
19
µS
8K byte Block
2
32
200
26
µS
Block Write Time
(In word mode)
32K word Block
2
1.1
4
0.66
S
4K word Block
2
0.15
0.5
0.12
S
Block Write Time
(In byte mode)
64K byte Block
2
2.2
7
1.4
S
8K byte Block
2
0.3
1
0.25
S
32K word Block
64K byte Block
2
1.2
6
0.9
S
4K word Block
8K byte Block
2
0.6
5
0.5
S
TA = 0 to +70° C
2
42
210
32
TA = -40 to +85° C
2
22.8
114
17.5
Word Write Time
Byte Write Time
Block Erase Time
Full Chip Erase
Time
S
tWHQV3
tEHQV3
Set Lock-Bit Time
2
56
200
42
µS
tWHQV4
tEHQV4
Clear Block Lock-Bits Time
2
1
5
0.69
S
tWHRZ1
tEHRZ1
Word/Byte Write Suspend Latency Time
to Read
4
6
15
6
15
µS
tWHRZ2
tEHRZ2
Block Erase Suspend Latency Time to
Read
4
16
30
16
30
µS
tERES
Latency Time from Block Erase
Resume Command to Block Erase
Suspend Command
5
600
600
µS
Notes:
1. Typical values measured at TA = +25° C and VDD = 3.0V, VPP = 3.0V or 12.0V. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. A latency time is required from issuing suspend command (#WE or #CE going high) until RY/#BY going High Z or SR.7 going
"1".
5. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than
tERES and both commands are written repeatedly, a longer time is required than standard block erase until the completion of
the operation.
- 47 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
12. ADDITIONAL INFORMATION
Recommended Operating Conditions
At Device Power-up
AC timing illustrated in Figure 21 is recommended for the supply voltages and the control signals at
device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VDD
VDD(min)
Vss
#RESET(p)
Vpp
*2
tVR
#CE (E)
#WE (W)
#OE (G)
#WE (S)
DATA (D/Q)
tR
t PHQV
VIH
VIL
(V) VPPH1/2
Vss
ADDRESS(A)
t2VPH*1
VIH
tAVQV
tR or tF
tR or tF
Valid Address
VIL
tF
VIH
t ELQV
tR
VIL
VIH
VIL
tF
t GLQV
tR
VIH
VIL
VIH
VIL
VOH
VOL
HIGH Z
Valid Output
* 1 t5VPH for the device in 5V operations.
*2 To prevent the unwanted writes, system designers should consider the VPP switch, which connects VPP to VSS during read
operations and VPPH1/2 during write or erase operations.
Figure 21. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“ described in
specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
- 48 -
W28J800B/T
Rise and Fall Time
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VDD Rise Time (Note 1)
tVR
0.5
30000
µS/ V
Input Signal Rise Time (Note 1, 2)
tR
1
µS/ V
Input Signal Fall Time (Note 1, 2)
tF
1
µS/ V
Notes:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations. tR(Max.) and tF(Max.) for
#RESET are 50µs/V
Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset,
and control signals, as shown in Figure 22 (b). The acceptable glitch noises are illustrated in Figure 22
(a).
Input Singal
Input Singal
VIH(Min.)
VIH(Min.)
VIL (Max.)
VIL (Max.)
Input Singal
Input Singal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure 22. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).
- 49 -
Publication Release Date: October 31, 2002
Revision A3
W28J800B/T
13. ORDERING INFORMATION
ACCESS
TIME
BOOT BLOCK
(nS)
OPERATING
TEMPERATURE
(°C)
W28J800BT90C
90
0 to 70º C
Bottom Boot
48L TSOP
W28J800TT90C
90
0 to 70º C
Top Boot
48L TSOP
W28J800BT90L
90
-40 to 85º C
Bottom Boot
48L TSOP
W28J800TT90L
90
-40 to 85º C
Top Boot
48L TSOP
PART NO.
PACKAGE
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
14. PACKAGE DIMENSION
48-Lead Standard Thin Small Outline Package (measured in millimeters)
1
48
e
MILLIMETER
INCH
Sym. MIN. NOM.
MAX. MIN. NOM. MAX.
E
b
c
D
HD
A2
0.95
1.00
1.05
0.037 0.039 0.041
D
18.3
18.4
18.5
0.720 0.724 0.728
HD
19.8
20.0
20.2
0.780 0.787 0.795
E
11.9
12.0
12.1
0.468 0.472 0.476
b
c
0.17
0.22
0.10
θ L
A1
0.50
Y
- 50 -
0.27 0.007 0.009 0.011
0.020
0.60
0.70
0.020 0.024 0.028
0.031
0.004
0.10
0
0.008
0.21 0.004
0.80
Y
θ
0.002
0.50
e
L1
A
L1
0.05
L
A2
0.047
1.20
A
A1
5
0
5
W28J800B/T
15. VERSION HISTORY
VERSION
DATE
PAGE
A1
May 21, 2002
-
A2
August 7, 2002
All
A3
October 31, 2002
37,40,45
DESCRIPTION
Initial Issued
Update description and correct typo
Correct the typo of W28J800BT/TT90C and
W28J800BT/TT90L
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 51 -
Publication Release Date: October 31, 2002
Revision A3