ACX306AK
3.86cm (1.5 Type) NTSC/PAL Color LCD Panel
Description
The ACX306AK is a 3.86cm diagonal active matrix
TFT-LCD panel addressed by low temperature polycrystalline silicon transistors with built-in peripheral
driving circuitry. This panel provides full-color
representation for NTSC and PAL systems. In
addition, RGB dots are arranged in a delta pattern
that provides smooth picture quality without fixed
color patterns compared to vertical stripe and
mosaic patterns.
Features
• Number of active dots: 118,000, 3.86cm (1.5 Type) in diagonal
• Horizontal resolution: 240 TV lines
• Optical transmittance: 6.5% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
• Low voltage, low power consumption: 12V drive: 43mW (panel block, typ.)
• Smooth pictures with a RGB delta arrangement
• Supports NTSC/PAL
• Built-in picture quality improvement circuit
• Up/down and/or right/left inverse display function
• LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
• Dirt-resistant surface treatment
• Narrow frame
Element Structure
• Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
• Number of pixels
Total number of dots:
494 (H) × 242 (V) = 119,548
Number of active dots:
490 (H) × 240 (V) = 117,600
• Module dimensions
Package dimensions:
38 (W) × 32.6 (D) × 2.2 (H) (mm)
Effective display dimensions: 31.115 (H) × 30.360 (V) (mm)
Applications
LCD monitors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00143-PS
ACX306AK
Block Diagram
The panel block diagram is shown below.
H Level Shifter & Shift Register
COM
LC
V Shift Register
CS
Boost,
Negative Voltage
Generation Circuit
Level Shifter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TESTL
COM
VST
VCK
EN
DWN
VDD
VSS
VDDG
VSSG
TEST2
WIDE
HST
REF
TEST
Cext/Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
TESTR
Common
Voltage
–2–
ACX306AK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
VDD, Cext/Rext
–1.0 to +17
V
• V driver boost supply voltage
VDDG
VDD – 1.0 to +18 V
• V driver negative supply voltage VSSG
–3.0 to +1.0
V
• Common voltage of panel
COM
–1.0 to +17
V
• H driver input pin voltage
HST, HCK1, HCK2, RGT, WIDE
–1.0 to +17
V
• V driver input pin voltage
VST, VCK, EN, DWN, REF
–1.0 to +15
V
• Video signal, uniformity improvement signal input pin voltage
GREEN, RED, BLUE, PSIG
–1.0 to +13
V
• Operating temperature
Topr
–10 to +60
°C
• Storage temperature
Tstg
–30 to +85
°C
Operating Conditions of Panel Block
1. Input/output supply voltage conditions∗1
Item
(VSS = 0V)
Min.
Typ.
Max.
Unit
11.4
12.0
12.6
V
VDD – 3.4
12.0
—
V
VDDG
14.0
15.0
16.3
V
VSSG
∗
2
Resistor connected to Cext/Rext pin
Rext
–2.3
–1.8
–1.5
V
—
10
160
kΩ
Symbol
VDD
Supply voltage
Cext/Rext∗2
VDDG output voltage setting
VSSG output voltage setting∗3
∗1 The VDD typical voltage setting is noted as 12.0V in these specifications.
∗2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below.
∗3 For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing
Zener diode as shown in the figure below.
The Cext/Rext value differs
according to the rising time
of the panel supply voltage.
ACX306AK
VDD
VSSG
Rext
1µF
Cext/Rext
VDD
Cext/Rext
Voltage
VDD
Cext
VSS
Recommended
voltage applied
example Zener
diode.
(RD2.7UM is
recommended)
VDD – Cext/Rext
7
VDDG
text
1µF
Time
Set a Cext value that satisfies
text > 1ms.
–3–
Recommended
voltage applied
example Zener
diode.
(RD4.3UM is
recommended)
ACX306AK
2. Panel input signal voltage conditions
Item
H/V driver input voltage
(VSS = 0V)
Symbol
Min.
Typ.
Max.
Unit
(Low)
VIL
–0.3
0.0
0.3
V
(High)
VIH
2.6
3.0
5.5
V
VIH/2 – 0.3
VIH/2
VIH/2 + 0.3
V
REF input voltage
VREF
Video signal center voltage∗4
VVC
5.8
6.0
6.2
V
Video signal input range∗4
Vsig
1.0
VVC ± 4.0
VDDG – 4.0
(10.5V or less)
V
Uniformity improvement signal∗4
Vpsig
VVC ± 2.3
VVC ± 2.5
VVC ± 2.7
V
Common voltage of panel (Ta = 25°C) Vcom
VVC – 0.6
VVC – 0.5
VVC – 0.4
V
∗4 Input video and uniformity improvement signals should be input the voltage amplitude symmetrical to VVC
as shown in Fig. 1.
PSIG waveform
Vpsig
VVC
Fig. 1
Pin Description of Panel Block
Pin
No.
Symbol
Pin
No.
Symbol
1
TESTL
Panel test output; no connection
13
HST
Start pulse input for H shift register
drive
2
COM
Common voltage input of panel
14
REF
Level shifter circuit REF voltage
input
3
VST
Start pulse input for V shift register
drive
15
TEST
Panel test output; no connection
4
VCK
Clock input for V shift register drive
16
Cext/
Rext
Time constant power supply input
for H shift register drive
5
EN
Gate selection pulse enable input
17
HCK2
Clock input for H shift register drive
6
DWN
V shift register drive direction signal
input
18
HCK1
Clock input for H shift register drive
7
VDD
Power supply input for V driver
19
PSIG
Uniformity improvement signal input
8
VSS
H and V driver GND
20
GREEN Video signal (G) input to panel
9
VDDG
Boost power supply setting for
V driver
21
RED
Video signal (R) input to panel
10
VSSG
Negative power supply setting for
V driver
22
BLUE
Video signal (B) input to panel
11
TEST2
No connection inside the panel.
(with 1MΩ terminating resistor)
23
RGT
H shift register drive direction signal
input
12
WIDE
Uniformity improvement signal
control pulse input
24
TESTR
Panel test output; no connection
Description
–4–
Description
ACX306AK
Input Equivalent Circuits of Panel Block
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to VSS with a
high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) RED, GREEN, BLUE, PSIG
VDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
VDD
VDD
H level shifter and
shift register circuit
HCK1
1MΩ
HCK2
1MΩ
(3) WIDE, REF
VDD
VDD
350Ω
350Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(4) HST
VDD
VDD
175Ω
175Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(5) RGT, REF
VDD
VDD
2kΩ
2kΩ
Level conversion
circuit
Input
1MΩ
REF
1MΩ
–5–
ACX306AK
(6) VST, VCK, EN, REF
VDD
VDD
800Ω
800Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(7) DWN, REF
VDD
VDD
2kΩ
2kΩ
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(8) VDDG, VSSG
VDD
Boost, Negative
voltage
generation circuit
VDDG, VSSG
(9) COM
Input
LC
1MΩ
(10) Cext/Rext
VDD
H driver
Cext/Rext
1MΩ
(11) TEST, TEST2
VDD
350Ω
350Ω
TEST
TEST2
1MΩ
1MΩ
(12) TESTL, TESTR
VDD
4MΩ
TESTL
TESTR
–6–
ACX306AK
Clock Timing Conditions of Panel Block
(VIH = 3.0V, VDD = 12V, Ta = 25°C)
Symbol
Item
HST
HCK
VST
VCK
EN
WIDE
Min.
Typ.
Max.
HST rise time
trHst
—
—
30
HST fall time
tfHst
—
—
30
HST data setup time
tdHst
300
333
363
HST data hold time
HCKn∗5 rise time
thHst
–30
0
30
trHckn
—
—
30
HCKn∗5 fall time
tfHckn
—
—
30
HCK1 fall to HCK2 rise time
to1Hck
–15
0
15
HCK1 rise to HCK2 fall time
to2Hck
–15
0
15
VST rise time
trVst
—
—
100
VST fall time
tfVst
—
—
100
VST data setup time
tdVst
30
32
34
VST data hold time
thVst
–30
–32
–34
VCK rise time
trVckn
—
—
100
VCK fall time
tfVckn
—
—
100
EN rise time
trEn
—
—
100
EN fall time
tfEn
—
—
100
EN fall to VCK rise/fall time
tdEn
500
600
700
EN pulse width
twEn
2900
3000
3100
WIDE rise time
trWide
—
—
100
WIDE fall time
tfWide
—
—
100
WIDE (H) rise to VCK rise/fall time
tdhWide
–0.4
–0.5
–0.6
WIDE (H) pulse width
twhWide
1.4
1.5
1.6
∗5 HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz)
–7–
Unit
ns
µs
ns
µs
ACX306AK
Horizontal Standard Timing
3.1µs
HST
HCK1
HCK2
FRP
0.6µs
VCK
3.0µs
EN
WIDE
1.1µs
0.4µs
1.5µs
–8–
ACX306AK
<Horizontal Shift Register Driving Waveforms>
Item
HST rise time
Symbol
Waveform
trHst
90%
HST
HST
HST fall time
tfHst
HST data setup time
tdHst
Conditions
90%
10%
10%
trHst
tfHst
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
∗6
HST
50%
50% 50%
HCK1
HST data hold time
thHst
thHst
tdHst
HCKn∗5 rise time
trHckn
∗5
90%
HCKn
HCKn∗5 fall time
10%
10%
tfHckn
HCK
tfHckn
∗6
to1Hck
HCK1 50%
50%
50%
HCK1 rise to HCK2 fall
time
• tdHst = 333ns
thHst = 0ns
50%
HCK2
to2Hck
to2Hck
WIDE rise time
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 333ns
thHst = 0ns
90%
trHckn
HCK1 fall to HCK2 rise
time
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
50%
to1Hck
90%
trWide
90%
WIDE
10%
WIDE fall time
10%
tfWide
trWide
∗7
WIDE WIDE rise to VCK rise/
fall time
∗6
tdhWide
VCK
50%
50%
WIDE
WIDE pulse width
tfWide
twhWide
50%
twhWide
tdhWide
∗6 Definitions:
The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement
∗7 WIDE represents every 1H pulse as shown in Horizontal Timing.
–9–
ACX306AK
Vertical Standard Timing
NTSC 4:3 (in case of EVEN field)
VST
VCK
FRP
HST
EN
WIDE
– 10 –
ACX306AK
<Vertical Shift Register Driving Waveforms>
Item
VST rise time
Symbol
Waveform
90%
trVst
Conditions
90%
VST
10%
VST
VST fall time
tfVst
VST data setup time
tdVst
10%
trVst
tfVst
∗6
VST
50%
50%
thVst
tdVst
VCK rise time
50%
50%
VCK
VST data hold time
trVck
90%
VCK
VCK
VCK fall time
tfVck
EN rise time
trEn
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
90%
10%
10%
trVck
tfVck
90%
90%
10%
EN
tfEn
EN fall to VCK rise/fall
time
tdEn
EN pulse width
twEn
tfEn
10%
trEn
∗6
VCK
50%
50%
EN
tdEn
– 11 –
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
thVst
EN
EN fall time
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
50%
twEn
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
ACX306AK
Electrical Characteristics of Panel Block (Ta = 25°C, VDD = 12.0V, VIH = 3.0V, VREF = 1.5V)
1. Horizontal drivers
Item
Symbol
Min.
Typ.
Max.
Unit
Conditions
HCKn input pin capacitance
CHckn
—
55
65
pF
HST input pin capacitance
CHst
—
30
50
pF
Video signal input pin capacitance
Csig
—
120
150
pF
Psig input pin capacitance (4:3 display)
Cpsig
—
5.2
8.0
nF
Input pin current
HCK1
I Hck1
–600
–300
—
µA
HCK1: actual driving
HCK2
I Hck2
–600
–300
—
µA
HCK2: actual driving
HST
I Hst
–200
–100
—
µA
HST = GND
RGT
I RGT
–150
–50
—
µA
RGT = GND
REF
I REF
–900
–300
—
µA
REF = VIH/2
Symbol
Min.
Typ.
Max.
Unit
HCKn: HCK1, HCK2 (1.5MHz)
2. Vertical drivers
Item
Conditions
VCK input pin capacitance
CVck
—
15
20
pF
VST input pin capacitance
CVst
—
15
20
pF
Input pin current
VCK
I Vck
–150
–50
—
µA
VCK = GND
VST
I Vst
–150
–50
—
µA
VST = GND
EN
I En
–150
–50
—
µA
EN = GND
DWN
I DWN
–150
–50
—
µA
DWN = GND
WIDE
I WIDE
–150
–50
—
µA
WIDE = GND
Symbol
Min.
Typ.
Max.
Unit
(Ta = 25°C)
PWR25
—
43
55
mW
(Ta = 60°C)
PWR60
—
—
75
mW
Symbol
Min.
Typ.
Max.
Unit
0.5
1
—
MΩ
3. Total power consumption of the panel
Item
Total power consumption
of the panel (NTSC)
4. Pin input resistance
Item
Pin – VSS input resistance 1
Rin1
– 12 –
ACX306AK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Item
Symbol
Contrast ratio
25°C
CR25
60°C
CR60
Panel transmittance∗1
Measurement
method
T
1
2
Min.
Typ.
Max.
Unit
100
200
—
—
100
180
6.0
6.5
—
%
X
Rx
0.595
0.625
0.655
Y
Ry
0.310
0.340
0.370
X
Gx
0.240
0.270
0.300
Y
Gy
0.580
0.610
0.640
X
Bx
0.120
0.150
0.180
Y
By
0.08
0.110
0.140
25°C
V90-25
1.30
1.50
1.70
60°C
V90-60
1.30
1.50
1.70
25°C
V50-25
1.70
1.90
2.10
60°C
V50-60
1.70
1.90
2.10
25°C
V10-25
2.30
2.50
2.70
60°C
V10-60
2.30
2.50
2.70
R–G
V50RG
–0.115
–0.080
–0.045
B–G
V50BG
0
0.03
0.05
0°C
ton0
—
70
90
25°C
ton25
—
17
25
0°C
toff0
—
120
180
25°C
toff25
—
30
75
Flicker∗1
60°C
F
7
—
–60
–30
dB
Image retention time∗1
60°C
YT1
8
—
—
rank C
s
CR ≥ 10
θT
θB
θL
θR
9
15
50
35
35
20
60
40
40
—
Degree
(°)
θ = 0°
Rf
10
—
0.9
1.5
%
25°C
CTK
11
—
0.9
1.5
%
R
G
Chromaticity
B
V90
V-T
characteristics∗1
V50
V10
Half tone color reproduction
range∗1
ON time
Response
time∗1
OFF time
Viewing angle range
Surface reflection ratio
Cross talk∗1
3
4
5
6
∗1 Conforms to the measurement results for the discrete panel.
– 13 –
CIE
standards
V
V
ms
ACX306AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
VDD = 12.0V, VIH = 3.0V, VREF = 1.5V
VVC = 6.0V, VCOM = 5.5V, Vpsig = 6.0 ± 2.5V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Three types of measurement systems are used as shown below.
(5) R, G and B input signal voltage Vsig
Vsig = 6.0 ± VAC [V] (VAC: signal amplitude)
• Measurement system I
Surface A∗
Luminance
Meter
Using the TOPCON BM-5A luminance meter.
Backlight
LCD panel
Using the Stanley E13585A inverter.
E13585A
DC6.0V
• Measurement system II
Optical fiber
Light receptor lens
Light Detector
Surface A∗
Measurement
Equipment
Measure using the discrete LCD panel.
Drive Cirucuit
Light Source
• Measurement system III
Light
Source
Optical fiber
Spectroscope
Surface A∗
∗ Surface A: See the Package Outline.
1. Contrast Ratio
Contrast ratio (CR) is given by the following formula.
CR = L (White)/L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.0V.
Both luminosities are measured by System I.
– 14 –
ACX306AK
2. Optical Transmittance of Panel
Optical transmittance (T) is given by the following formula.
T = L (White)/Luminance of Backlight × 100 [%]
3. Chromaticity
Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses x and y of
the CIE standards as the chromaticity here.
Signal amplitudes (VAC) supplied to each input
Raster
R input
G input
B input
R
0.5
4.0
4.0
G
4.0
0.5
4.0
B
4.0
4.0
0.5
W
0.0
0.0
0.0
4. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panel, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
Transmittance [%]
(Unit: V)
90
50
10
V90 V50 V10
VAC – Signal amplitude [V]
that is to say the differences between V50R and V50G
and between V50B and V50G, are given by the following
formulas respectively.
V50RG = V50R – V50G
V50BG = V50B – V50G
– 15 –
100
Transmittance [%]
5. Half Tone Color Reproduction Range
The half tone color reproduction range of LCD panels
is characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II.
System II defines signal voltages of each R, G and B
raster mode which correspond to 50% of transmittance,
V50R, V50G and V50B, respectively. V50RG and V50BG,
V50RG
V50BG
50
R raster
G raster
B raster
0
V50R V50B
V50G
VAC – Signal amplitude [V]
ACX306AK
6. Response Time
Response times ton and toff are measured
by System II by applying the input signal
voltages in the figure to the right to each
input pin. These times are defined by the
following formulas.
ton = t1 – tON
toff = t2 – tOFF
t1: time which gives 10% transmittance
of the panel.
t2: time which gives 90% transmittance
of the panel.
Input signal voltage (Waveform applied to measured pixels)
4.0V
0.5V
6.0V
0V
Optical transmittance output
waveform
100%
90%
10%
0%
The relationships between t1, t2, tON and
tOFF are shown in the figure to the right.
tON
t1
tOFF
ton
t2
toff
7. Flicker
Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms)
of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer
in System II.
F [dB] = 20 log {AC component/DC component}
∗ R, G, B input signal voltage for gray raster mode is given by Vsig = 6.0 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures.
Apply the monoscope pattern∗ to the LCD panel for 1 minute and then change to a gray scale signal
(Vsig = 6.0 ± VAC [V]; VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time for the residual image to disappear.
∗ Monoscope pattern input conditions
Black level
Vsig = 6.0 ± 4.0 or 6.0 ± 2.0 [V]
(shown in the figure to the right)
Vcom = 5.5V
White level
4.0V
2.0V
6.0V
2.0V
4.0V
0V
Vsig waveform
– 16 –
ACX306AK
9. Definition of Viewing Angle Range
Viewing angle range is measured by System Ι. The
contrast ratio (CR) is measured at the angles
defined in the figure to the right and the range where
CR ≥ 10 is taken as the viewing angle range.
Measure with surface A∗ facing upwards.
∗ Surface A: See the Package Outline.
Normal (θ = 0°)
θB
θT
Left
θL
θR
Top
Bottom
Right
Surface A
10. Surface Reflection Ratio
Surface reflection ratio (Rf) is given by the following formula.
Rf = Reflected optical luminance of the panel surface A∗/Reflected optical luminance of Al (wafer) × 100 [%]
The incident and reflected angles of light are both 0°.
Both luminosities are measured by System III.
∗ Surface A: See the Package Outline.
11. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi
(i = 1 to 4) around the black window (Vsig = 4.0V/1V).
Cross talk value CTK =
W1 W1'
W2
W4
W2'
W4'
W3 W3'
– 17 –
Wi' – Wi
× 100 [%]
Wi
ACX306AK
Description of Panel Block Operation
1. Color Coding
The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the
display.
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
1
Gate SW
G
B
R
B
R
G
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
B
R
G
G
B
Active area
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
240
B
R
G
B
R
R
G
B
2
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
490
494
– 18 –
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
2
1
R
242
R
ACX306AK
2. Description of LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to each of 240 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
• The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display is
possible by using the enable pin and simultaneously controlling VCK.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry,
applies selected pulses to each of 490 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning
direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT
pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the
DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top
for DWN pin at low level (0V). (These scanning directions are from a front view.)
• The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one
pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 240 × 490 pixels to
display a picture in a single vertical scanning period.
• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots against
adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal
line against the horizontal sync signal to apply a video signal to each pixel properly.
• The video signal should be input with the polarity-inverted every horizontal cycle.
• The relationships between the vertical shift register start pulse VST and the vertical display period, and
between the horizontal shift register start pulse HST and the horizontal display period are shown below for
top to bottom and left to right scan.
(1) Vertical display period (DWN: high level)
VD
VST
VCK
1
2
239
240
Vertical display period 240H (14.5ms)
(2) Vertical display period (DWN: low level)
VD
VST
1
VCK
2
239
240
Vertical display period 240H (14.5ms)
(3) Horizontal display period (RGT: high level)
BLK
HST
165
HCK1
1
2
3
164
166
Horizontal display period (54.6µs)
HCK2
– 19 –
ACX306AK
3. RGB Simultaneous Sampling
The horizontal driver samples R, G and B video signal simultaneously, which requires phase matching
between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching
by an external signal delay circuit is needed before applying the video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block
diagrams are as follows.
The ACX306AK has a right/left inversion function. The following phase relationship diagram indicates the
phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be
inverted for the B and G signals.
B
S/H
S/H
CKB
CKG
R
S/H
S/H
CKR
CKG
G
S/H
AC Amp
22
BLUE
AC Amp
21
RED
AC Amp
20
GREEN
ACX306AK
(1) Sample-and-hold (right scan)
CKG
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CKB
CKR
CKG
B
R
Delay
Delay
AC Amp
22
BLUE
Delay
AC Amp
21
RED
AC Amp
20
GREEN
G
– 20 –
ACX306AK
(2) Delay element (right scan)
ACX306AK
System Configuration
+12.0V
+12.0V
+3.0V
Rext
PSIG
Y/color difference
RED
R/G/B
Cext/Rext
Cext
GREEN
BLUE
∗ See page 3 for the value setting.
COM
HST
HCK1
CXA3522R
Serial data
Zener diode
RD4.3UM
VDDG
HCK2
VST
LCD Panel
ACX306AK
1µF
VCK
+12.0V
DWN
EN
RGT
Zener diode
RD2.7UM
REF
WIDE
VSSG
1µF
– 21 –
ACX306AK
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install grounded conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (Polarizer) is not covered by a protective sheet. Take care of handling
it so as not to damage the polarizer.
c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stains on the surface.
d) Use ionized air to blow dust off the panel.
(3) Others
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storage or use the panel at high temperatures or high humidity, as this may result in damage.
– 22 –
B
32.7 ±0.4
4 ±0.1
BB
LCD panel
Rear View
Center
(reference)
(Polarizer)
16.85
2.15
24.4 ±0.4 (Polarizer)
(0.5)
Pin24
±0.03
1.03
0.3
Erectrode enlarged(back)
P : 0.5±0.02×23=11.5±0.03
0.35
1.4
2.06
9.82
10.18
33.8(Window)
(20)
16.95
1.4 ±0.1
A(3 : 1)
B
φ 0.85 ±0.05
(2.05)
7.5
32.6
Pin1
0.5 ±0.1
34.3(Window)
2
1
Center
(reference)
(1.85)
7
3
4
1
2
3
4
5
6
FPC
Reinforcing board
Polarizer
Shield case(front)
Shield case(rear)
label
Front view
Note1. Tolerance with no indication(±0.2)
2. SONY logotype
3. Design the guaranteed area of polarizer
within the outer circumference of 0.7mm
of the active area.
4. Mass:approximately 7g
12.5 ±0.05
6.6 ±0.5
19
30.48(Effective area)
31.115(Active area)
33.3 ±0.4 (Polarizer)
3.25 ±0.5
12.5 ±0.05
10.94 ±0.5
10.53 ±0.5
Note2
1.85
38
7.81 ±0.5
Unit: mm
1
22.86(Active area)
28.9 ±0.5
3.42
25.4(Window)
(3.78)
16.12
(16.48)
0.5 ±0.15
21.5 ±0.5
3 ±0.3
– 23 –
4 ±0.5
25 ±0.4 (Polarizer)
34.9 ±0.5
3.12
26(Window)
(3.48)
Package Outline
6
3
5
ACX306AK
Sony Corporation