CXA2571N
RF Matrix Amplifier
Description
The CXA2571N is an IC developed for the RF
signal processing of compact disc players.
Features
• Wide band RF signal processing
• RF system VCA circuit
• RF system equalizer (supports CAV mode)
• Supports pickups with built-in RF summing amplifier
• Low power consumption mode (EQ Pass mode)
• RW/ROM switching mode
• Center error amplifier
• Output DC level shift circuit
30 pin SSOP (Plastic)
Absolute Maximum ratings
• Supply voltage
Vcc
• Operating temperature Topr
• Storage temperature
Tstg
• Allowable power dissipation
PD
Functions
• RFAC summing amplifier, equalizer, VCA
• RFDC summing amplifier
• Focus error amplifier
• Tracking error amplifier
• Automatic power control
• VC buffer amplifier (analog system, digital system)
7
V
–20 to +75 °C
–65 to +150 °C
620
mW
Operating Conditions
• Supply voltage
Vcc – GND 3.0 to 5.5
V
• Operating temperature Topr
–20 to +75 °C
Applications
CD-ROM/RW compatible systems
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98260A98-PS
CXA2571N
Connected Circuit Diagram
VCC
0.1µ
VCC
<OP>
ACSUM
A
AC
SUM
VC
B
A
B
C
D
C
VC
D
RFAC
RFAC
EQ
DVCC
5.1k
RFDC
DVC
RW/ROM
A
B
C
D
<DSP>
RFDCI
RW/ROM
DC
SUM
VC
BST Rfc Vfc
AC
VCA
RF
VC
5.1k
ACG
EQI
RFDCO
RW/ROM
A
B
C
D
FEI
DVCC
100k
DVC
FE
FE
VOFST
VC
RW/ROM
RW/ROM
F
F
E
VC
10k
VC VOFST
F
E
DVCC
TE
TE
10k
E
DVC
AVC
RW/ROM
VC
RW/ROM
A
D
VC
Bottom
Hold
VOFST
AVC
DVCC
CEP
CE
RW/ROM
B
C
VC
Bottom
Hold
SW
PD
APC
APC-OFF (Hi-Z)
RW/ROM
(H/L)
VCC
AVC
DVC
r_adj
CE
CEM
CET
DVCC
DVC
VCC
LD
VCC
VC GND VCC
VCC GND
–2–
AVC
DVC
VC
CXA2571N
Pin Description
Pin
NO.
Symbol
I/O
Description
1
LD
Out
2
PD
In
APC amplifier input.
3
EQ_IN
In
RFAC system VCA block and EQ block input.
4
AC_SUM
5
GND
In
Ground.
6
A
In
A signal input.
7
B
In
B signal input.
8
C
In
C signal input.
9
D
In
D signal input.
10
E
In
E signal input.
11
F
In
F signal input.
12
SW
In
Mode switching signal input.
13
CET
In
CE system hold time constant adjustment.
14
CEP
—
CE amplifier non-inverted input.
15
DVCC
In
DVCC.
16
RFAC
Out
RFAC signal output.
17
DVC
Out
DVC output.
18
FE
Out
Focus error signal output.
19
FEI
—
FE amplifier virtual ground.
20
TE
Out
Tracking error signal output.
21
CE
Out
Center error signal output.
22
CEM
—
CE amplifier virtual ground.
23
VCC
In
VCC.
24
RFG
In
RFAC system VCA block low-frequency gain adjustment.
25
BST
In
EQ boost amount adjustment range.
26
VFC
In
EQ cut-off frequency adjustment.
27
RFC
In
EQ cut-off frequency adjustment.
28
VC
Out
VC voltage output.
29
RFDCO
Out
RFDC signal output.
30
RFDCI
—
Out
APC amplifier output.
RFAC system RF SUM output.
RFDC amplifier virtual ground.
–3–
CXA2571N
Pin Description and Equivalent Circuit
Pin
No.
Symbol
I/O
Equivalent circuit
Description
10k
1
LD
O
2
PD
I
1
APC amplifier output.
1k
55k
20k
APC amplifier input.
2
20k
1.1k
3
EQ_IN
I
3
5k
1.1k
Equalizer circuit input.
1.2k
VC
5k
VC
1.6k
1.6k
4
AC_SUM
O
5
GND
—
4
—
–4–
RFAC summing amplifier
output.
Ground.
CXA2571N
Pin
No.
6
Symbol
A
I/O
Equivalent circuit
Description
I
15k
6
7
B
100µA
I
7
8
C
I
RF summing amplifier and
focus error amplifier input.
30k
100µA
8
47k
100µA
9
47k
100µA
9
D
I
10
E
I
VC
27k
27k
Tracking error amplifier input.
10
11
F
I
124
20
11
20
TE
Tracking error amplifier
output.
O
200k
CD-ROM/RW switching input.
RW when connected to VCC,
ROM when connected to
GND.
200k
12
SW
I
12
200k
15
VCC
—
16
RFAC
O
Power supply.
—
100
16
RFAC amplifier output.
17
(DVCC + GND)/2 voltage
output.
2mA
17
DVC
O
150k
25
150k
–5–
CXA2571N
Pin
No.
18
Symbol
FE
I/O
Equivalent circuit
Description
Focus error amplifier output.
O
124
50k
18
Focus error amplifier gain
adjustment. The gain is
adjusted by the external
resistance value connected
between this pin and Pin 18.
VC
19
FEI
I
13
CET
I
124
19
76k
Center error amplifier time
constant adjustment.
124
13
4k
14
CEP
I
Center error amplifier noninverted input.
124
22
40k
21
CE
124
21
O
Center error amplifier input.
40k
14
22
CEM
I
23
VCC
—
24
RFG
I
Center error amplifier inverted
input.
124
VCC. (AVCC)
—
20k
24
VC
Sets the RFAC low-frequency
gain.
100µA
50µA
25
BST
I
20k
25
VC
20k
26
VFC
I
26
VC
100µA
–6–
Input for adjusting the
equalizer circuit boost amount.
Input for adjusting the
equalizer circuit boost
frequency with the control
voltage.
CXA2571N
Pin
No.
Symbol
I/O
Equivalent circuit
Description
1.0V
124
27
28
RFC
VC
I
27
150k
25
O
Input for adjusting the
equalizer circuit boost
frequency with external
resistance.
(VCC + GND)/2 voltage output.
28
150k
29
RFDC
O
1mA
1.5k
30
RFDCI
I
RFDC amplifier output. This
pin serves as the eye pattern
check point.
VC
29
124
124
30
–7–
RFDC amplifier gain
adjustment. The gain is
adjusted by the external
resistance value connected
between this pin and Pin 29.
Measurement No.
–8–
Icc_Aeqoff
Icc_DVcc
Icc_Slp
ACSUM_Ofst
Current consumption (Active, EQ Off)
Current consumption (DVcc)
Current consumption (Sleep)
SUM offset voltage
Low-frequency gain ROM_min Gac_ROM1
Gac_ROM2
Gac_ROM3
Gac_RW1
Low-frequency gain ROM_cnt
Low-frequency gain ROM_max
Low-frequency gain RW_min
12
13
27
26
25
24
23
22
21
20
19
18
17
16
15
O
O
Fac_MinL
Fac_MinH
Fac_ECoff
Vac_H
Vac_L
DC_OfstROM
DC_OfstRW
Gdc_ROM
Gdc_RW
Frequency response Min_L
Frequency response Min_H
Frequency response EQ_OFF
Maximum output voltage H
Maximum output voltage L
Offset voltage ROM
Offset voltage RW
Low-frequency gain ROM
Low-frequency gain RW
O
O
O
O
O
O
O
Gac_EQoff
Low-frequency gain EQ_off
O
Gac_RW3
Low-frequency gain RW_max
O
Gac_RW2
O
O
O
Low-frequency gain RW_cnt
O
O
O
O
AC_OfstRW
Offset voltage RW
11
14
O
AC_OfstROM
Offset voltage ROM
10
Vsum_H
Fsum
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
16
16
16
0V
1.0V
–1.0V
0.8Vp-p 100kHz
0.3Vp-p 100kHz
16
16
16
0V
1.0V
0V
75mVp-p 100kHz
0.8Vp-p 100kHz
0.4Vp-p 100kHz
16
–1.0V
25mVp-p 100kHz
0.1Vp-p 100kHz
29
29
29
29
16
0V
16
16
–2V
0V
0V
16
1.9V
0.2Vp-p 30MHz
0.8Vp-p 30MHz
16
–1.9V
0.2Vp-p 10MHz
O
O
16
0V
2V
4
–0.3V
16
4
0.3V
1.6Vp-p 100kHz
0.2Vp-p 100kHz
O
4
23
15
23
23
Measurement pin
4
0V
E5
0.1Vp-p 30MHz
1.9V
0V
1.9V
0V
E4
4
0V
E3
0.1Vp-p 100kHz
O
O
O
Hi-Z
0V
0V
Bias conditions
E2
Switch conditions
5
0.6
30
50
0
7.5
1.0
45
70
V
mA
mA
mA
mA
–0.3
–0.3
–
0.9
–
0
0
0.3
0.3
–0.5 –0.3
1.25
V
V
V
V
–3.0 –1.5 –0.5 dB
14.0 16.0 18.0 dB
–1.2 –0.6
3.5
0.2
15
30
Min. Typ. Max. Unit
6.0
6.0
2.0
8.5
8.5
5.0
dB
dB
dB
8.0 11.0 dB
12.0 15.0 dB
0.8
1.0
0
150 mV
150 mV
V
V
29.0 32.0 33.0 dB
16.5 19.5 22.5 dB
–150
0
–1.0 –0.8 –0.6
0.6
Pin voltage
20 log (Vout/Vin)
dB
–2.0 –1.0 –0.5 dB
3.5
3.5
–1.0
5.0
9.0
–150
20 log (Vout/Vin)
5.0
8.0 11.0 dB
2.0
–11.0 –8.0 –5.0 dB
5.0
–1.0
Pin voltage
Pin voltage – AC_OfstROM
Pin voltage – AC_OfstROM
20 log (Vout/Vin) – Gac_EQoff
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin)
20 log (Vout/Vin) – Gac_RW2
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin) – Gac_RW2
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin)
20 log (Vout/Vin) – Gac_ROM2 –11.0 –8.0 –5.0 dB
Pin voltage
Pin voltage
Pin voltage
Pin voltage
20 log (Vout/Vin) – Gsum
20 log (Vout/Vin)
Pin voltage
Pin current
Pin current
Pin current
Pin current
Measurement
conditions
(AVCC = 1.9V, AVEE = –1.9V, DVCC = 1.9V, DVEE = –1.9V)
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 V1 amplitude V1 frequency E1
Vsum_L
SUM maximum output voltage H
SUM frequency response
Gsum
Icc_Aeqon
Current consumption (Active, EQ On)
SUM frequency gain
Symbol
Measurement item
SUM maximum output voltage L
RFDC
9
8
7
6
5
4
3
2
RFAC SUM
RFAC EQ
1
Function
Electrical Characteristics
CXA2571N
Measurement No.
Vdc_H
Vdc_L
FE_OfstROM
FE_OfstRW
Gfe_ROM1
Gfe_ROM2
Gfe_RW1
Gfe_RW2
Maximum output voltage H
Maximum output voltage L
Offset voltage ROM
Offset voltage RW
Low-frequency gain ROM1
Low-frequency gain ROM2
Low-frequency gain RW1
Low-frequency gain RW2
Switch conditions
–9–
TE_OfstROM
TE_OfstRW
Gte_ROM1
Gte_ROM2
Gte_RW1
Gte_RW2
Offset voltage ROM
Offset voltage RW
Low-frequency gain ROM1
Low-frequency gain ROM2
Low-frequency gain RW1
Low-frequency gain RW2
Frequency response ROM2
Frequency response RW1
Frequency response RW2
Maximum output voltage H
Maximum output voltage L
51
52
53
54
55
50
49
48
47
46
45
44
Frequency response ROM1
Vfe_L
Maximum output voltage L
Vte_L
O
O
O
O
O
O
O
O
O
Vte_H
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Fte_RW2
Fte_RW1
Fte_ROM2
Fte_ROM1
O
O
Vfe_H
Maximum output voltage H
43
42
O
Ffe_RW2
Frequency response RW2
41
Ffe_RW1
Frequency response RW1
O
O
O
O
O
O
O
40
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
20
20
25mVp-p 200kHz
20
20
25mVp-p 200kHz
–0.3V
20
0.3V
20
0.1Vp-p 200kHz
20
20
20
20
20
20
0.1Vp-p 200kHz
25mVp-p 10kHz
25mVp-p 10kHz
0.1Vp-p 10kHz
0.1Vp-p 10kHz
0V
18
18
25mVp-p 50kHz
18
18
25mVp-p 50kHz
–0.3V
18
0.1Vp-p 100kHz
0.3V
18
0.1Vp-p 100kHz
18
18
18
18
18
18
0V
0
0
dB
dB
150 mV
150 mV
1.5
1.5
dB
dB
–1.5 –1.1
V
V
–
Pin voltage
–
1.2
Pin voltage
1.7
–4.5 –2.0 –0.5 dB
20 log (Vout/Vin) – Gte_RW2
–4.5 –2.0 –0.5 dB
0
0
29.0 32.0 35.0 dB
29.0 32.0 35.0 dB
17.0 20.0 23.0 dB
20 log (Vout/Vin) – Gte_ROM2 –1.5
20 log (Vout/Vin) – Gte_RW1
0
0
V
17.0 20.0 23.0 dB
–150
–150
20 log (Vout/Vin) – Gte_ROM1 –1.5
20 log (Vout/Vin)
20 log (Vout/Vin)
20 log (Vout/Vin)
20 log (Vout/Vin)
Pin voltage
Pin voltage
–1.5 –1.1
V
–
Pin voltage
1.8
1.2
Pin voltage
1.7
–4.0 –2.0 –0.5 dB
20 log (Vout/Vin) – Gfe_RW2
–4.0 –2.0 –0.5 dB
0
0
25.0 28.0 31.0 dB
25.0 28.0 31.0 dB
13.5 16.5 19.5 dB
20 log (Vout/Vin) – Gfe_ROM2 –3.0 –2.0
20 log (Vout/Vin) – Gfe_RW1
150 mV
150 mV
V
V
13.5 16.5 19.5 dB
–150
–150
20 log (Vout/Vin) – Gfe_ROM1 –3.0 –2.0
20 log (Vout/Vin)
20 log (Vout/Vin)
20 log (Vout/Vin)
20 log (Vout/Vin)
Pin voltage
Pin voltage
–1.0 –0.6
–
–
Pin voltage
29
1.6
1.3
Pin voltage
29
20 log (Vout/Vin) – Gdc_ROM –3.0 –1.5 –0.5 dB
–0.25V
29
Min. Typ. Max. Unit
0.25V
0V
Measurement
conditions
–9.0 –7.0 –3.0 dB
0V
Measurement pin
20 log (Vout/Vin) – Gdc_RW
0V
0V
E5
29
0V
E4
25mVp-p 10kHz
25mVp-p 10kHz
0.1Vp-p 10kHz
0.1Vp-p 10kHz
25mVp-p 10MHz
0.1Vp-p 10MHz
E3
E2
Bias conditions
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 V1 amplitude V1 frequency E1
Frequency response ROM2
Ffe_ROM2
Ffe_ROM1
Fdc_RW
Frequency response RW
Frequency response ROM1
Fdc_ROM
Frequency response ROM
Symbol
39
38
37
36
35
34
33
32
31
30
29
28
Function
RFDC
FE
TE
Measurement item
CXA2571N
Measurement No.
– 10 –
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
Function
CE
APC
DVC AVC
Vapc1
Vapc2
Output voltage 1
Output voltage 2
O
Iapc_max
Maximum output current
Output voltage
VdVC
Vavc
O
Vapc_off
APC OFF voltage
Output voltage
O
Vapc3
O
O
O
O
O
O
Hi-Z
O
O
O
O
Vce_L
Maximum output voltage L
O
O
Vce_H
Maximum output voltage H
Output voltage 3
O
O
O
Vce_RW3
I/O characteristics RW3
O
Vce_RW2
I/O characteristics RW2
O
O
O
Vce_RW1
O
I/O characteristics RW1
O
O
O
Vce_ROM3
50mVp-p
50mVp-p
50mVp-p
1
0V
1
0V
17
28
1
1
30mV
1
21
0.5V
21
21
21
21
21
21
21
21
0V
Measurement pin
0.5V
0V
0V
E5
21
–30mV
0V
E4
E3
1MHz 25mV
1MHz 25mV
1MHz 25mV
0.2Vp-p 1MHz 0.1V
0.2Vp-p 1MHz 0.1V
0.2Vp-p 1MHz 0.1V
I/O characteristics ROM3
O
Vce_ROM2
I/O characteristics ROM2
O
O
Vce_ROM1
I/O characteristics ROM1
O
0V
CE_OfstRW
Offset voltage RW
O
0V
E2
Bias conditions
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 V1 amplitude V1 frequency E1
Switch conditions
CE_OfstROM
Symbol
Offset voltage ROM
Measurement item
0
0
–0.1
0.3
0
0.1
0.65 1.0
0.3
0
0
–100
Pin voltage
0.6
100 mV
100 mV
V
0
–0.2
–100
Pin voltage
Pin voltage
V
1.6
1.4
Pin voltage
–
V
V
1.0
1.4
160 210 mV
V
0.7
–1.7 –1.1
–
V
V
V
110
1.7
–
0.1
1.1
0
0.65 1.0
–1.4 –1.0 –0.7
Pin voltage
Pin voltage
Input where output voltage = 0V
Pin voltage
Pin voltage
Pin voltage – CE_OfstRW –0.1
Pin voltage – CE_OfstRW
V
V
V
V
200 mV
200 mV
–1.0 –0.65 –0.3
–200
–200
Min. Typ. Max. Unit
Pin voltage – CE_OfstRW –1.0 –0.65 –0.3
Pin voltage – CE_OfstROM
Pin voltage – CE_OfstROM
Pin voltage – CE_OfstROM
Pin voltage
Pin voltage
Measurement
conditions
CXA2571N
CXA2571N
Electrical Characteristics Measurement Circuit
VCC
1.9V
VCC
10k
5.1k
28
25
F
SW
CET
CEP
DVCC
4
5
6
7
8
9
10
11
12
13
14
15
S1
S2
S3
10k
E2
S4
VEE S5
–1.9V
S6
S7
S8
0.8mA
10k
10k
S9
S10
VEE
V1
E1
– 11 –
20k
200k
DVCC
VEE VCC
VCC
DVC
FEI
S11
RFAC
E
3
FE
CEM
D
2
TE
VCC
C
1
CE
RFG
B
16
BST
17
A
18
VFC
19
GND
20
RFC
21
10k
AC_SUM
22
10k
100k
VC
23
10k
EQ_ IN
24
10k
200k
RFDCO
26
E3
PD
27
E4
RFDCI
29
E5
5.1k
LD
30
S12
CXA2571N
Application Circuits
CE
OUT
VCC
20k
20k
VC
5.1k
CEM
D
E
F
SW
CET
CEP
DVCC
8
9
10
11
12
13
14
15
A
B
C
D
10k
VCC
0.1µ 20k
VCC
20k
20k
E
F
CE
OUT
TE
OUT
20
DVC
FE
17
SW
CET
CEP
DVCC
6
7
8
9
10
11
12
13
14
15
LD
PD IN
Drive
0.1µ
A
B
C
D
10k
10k
E
F
MODE
Control
20k
RFAC
F
5
DVC
E
4
FE
CEM
D
3
FEI
VCC
C
2
TE
RFG
B
1
CE
BST
A
16
VFC
18
GND
19
RFC
21
AC_SUM
22
VC
23
DVC
100k
EQ_ IN
24
RFAC
OUT
RFDCO
25
DVCC
PD
26
20k
FE
OUT
200k
27
20k
MODE
Control
RFDCI
28
10k
RFAC
VCC
C
7
FEI
RFG
B
6
5.1k
29
16
LD
30
17
18
5
RF
SUM
RFDC
OUT
19
4
0.1µ
LD
PD IN
Drive
20
21
BST
22
A
23
VFC
24
GND
3
25
DVC
100k
RFC
EQ_ IN
2
26
RFAC
OUT
AC_SUM
RFDCO
PD
1
27
VC
RFDCI
LD
28
FE
OUT
200k
5.1k
29
TE
OUT
TE
VC
5.1k
30
VCC
0.1µ 20k
CE
RFDC
OUT
20k
DVCC
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 12 –
CXA2571N
Description of Functions
• RFAC
The RF signal input by connecting capacitance to the EQ_IN pin is equalized, arithmetically amplified and then
output from the RFAC pin.
VCC
A 6
B 7
C 8
AC
SUM
D 9
AC_SUM
25
0.1
26
27 RFC
4
3
RF
5.1k
BST VFC
EQ
Amp
EQ_IN
16 RFAC
RFG 24
RW/ROM
When BST = VCC
Low-frequency gain
AC_SUM: 16dB (both ROM/RW)
VCA to RFAC
ROM: 2dB
RW: 14dB
The EQ can be bypassed by connecting the BST control pin (Pin 25) to VCC. In this case only the EQ block
enters sleep mode and the low power consumption mode (slim mode) is activated. The low-frequency gain is
the same value as for EQ ON mode.
The RF_SUM input dynamic range is VC ± 300mV (typ.).
If RF (summing signal) is present at the pickup output pin, input the addition output signal to the EQ_IN pin
(Pin 3) coupled by capacitance.
When using a pickup without a summing output function, perform addition with the AC SUM block and then
input the signal to the EQ_IN pin coupled by capacitance.
RW/ROM switching is done by the VCA block, so either input method can be used without problem.
The RW gain is 12dB higher than the ROM gain.
The VCA low-frequency gain can be adjusted by
the RFG pin (Pin 24) voltage.
The control voltage vs. low-frequency gain
characteristics are shown in the graph to the right.
Gain [dB]
VCA variable range
8
0
–8
Vcut [V]
VC – 1
VC
The RFAC pin (Pin 16) is an NPN transistor emitter follower output.
The maximum drive current is approximately 2mA.
If the load capacitance distorts the output waveform, increase the drive current.
Connect resistance between Pin 16 and GND.
– 13 –
VC + 1
CXA2571N
• EQ
In
Amp
HPF
LPF
LPF
fc
Out
Boost
The diagram to the left shows the EQ internal block
diagram.
The EQ consists of a combination of HPF and LPF.
The HPF and LPF transmittance is the Bessel function.
The boost gain can be adjusted by adjusting the HPF
gain.
The boost frequency is adjusted by the RFC external
resistance value and the VFC control voltage value.
EQ CNT
RFC 27
VFC 26
BST 25
VCC
VC
VC
RFC resistance value: The cut-off frequency fo of each
filter is adjusted by the Pin 27
external resistance value.
The VFC voltage can be varied
using this fo as the reference.
VFC voltage:
The boost gain can be adjusted by the BST pin
control voltage.
The control characteristics are shown in the graph
below.
fo can be changed by the voltage
applied to Pin 26.
The cut-off frequency control characteristics are
shown in the graph below.
Boost Gain [dB]
fc [Hz]
8dB
1.5fo
fo
0dB
0.5fo
Vcut [V]
VC – 1.0
VC
Vcut [V]
VC + 1.0
VC – 1.0
Pin 25 voltage
VC
VC + 1.0
Pin 26 voltage
• APC (Automatic Power Control)
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics. Therefore, the current must be controlled to maintain the monitor photodiode
output at a constant level. This control is performed by the APC function.
VCC
56k
PD 2
1 LD
10k
10k
55k
10k
1k
56k
1.25V
– 14 –
CXA2571N
• Focus Error
The signals input to the A and C pins and the B and D pins are arithmetically amplified and the focus error
signal is output.
This circuit has RW/ROM switching, low-frequency gain adjustment and offset addition functions.
VC
100k
ROM
RW
50k
30k
FEI 19
200k
18 FE
A 6
50k
C 8
B 7
D 9
ROM
50k
ROM
DVC
50k
VOFST
RW
200k
RW
200k
FE = Gain { (B + D) – (A + C) }
Low-frequency gain
ROM: 16dB
RW: 28dB
Cut-off frequency fc (typ.) ROM: 400kHz
RW: 300kHz
• Tracking Error
The signals input to the E and F pins are arithmetically amplified and the tracking error signal is output.
This circuit has RW/ROM switching and offset addition functions.
E
10k
27k
373k
10
F
10k
11
RW
387k
RW
27k
TE = Gain (F – E)
Low-frequency gain ROM: 20dB
RW: 32dB
fc (typ.)
ROM: 1MHz
RW: 250kHz
ROM
20 TE
ROM
373k
VC
• VC Buffer
• DVC Buffer
This outputs the VC ((1/2) VCC) voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the analog system VC voltage.
This outputs the 1/2 DVCC voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the digital system DC voltage.
The output DC voltage of each system is level shifted
using the DVC voltage as the reference.
VCC
25k
DVCC
40k
25k
28
40k
17
40k
40k
– 15 –
CXA2571N
• RFDC
The signals input via the A, B, C and D pins are added, amplified and the RFDC signal is output.
RW/ROM switching and low-frequency gain adjustment are possible.
R (OFST)
5.1k
A 6
15k
B 7
10k
C 8
ROM
RFDCI 30
29 RFDCO
RW
40k
1.5k
D 9
VC
VC
RFDC = Gain (A + B + C + D)
Low-frequency gain ROM: 20dB (17MHz)
RW: 32dB (5.5MHz)
fc (Typ.)
ROM: 12MHz
RW: 5MHz
The gain can be adjusted by the external resistance connected between Pins 29 and 30.
The output voltage offset can be adjusted by the R (OFST) resistance.
• Center Error
The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center error
signal is output.
RW/ROM switching, low-frequency gain adjustment and offset adjustment are possible.
The bottom hold time constant can be adjusted by the CET (Pin 13) external resistance value.
8k
ROM
16k
A 6
16k
32k
VCC
CEP 200k
14
RW
D 9
VC
40p
40k
CE
40k
CEM
21
VC
40p
16k VC
B 7
16k
C 8
32k
8k
200k
22
RW
ROM
CET 20k
13
VCC
The (B + C) – (A + D) signal is arithmetically amplified.
Low-frequency gain ROM: 14dB
RW: 26dB
– 16 –
DVC
CXA2571N
• Output Offset Shift
The RFDC, FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC).
The reference voltage of this IC is the VC voltage, and only the output reference voltage changes.
The maximum output voltage of each output signal should be kept to the digital VCC voltage (DVCC) or less in
order to protect the DSP_IC.
40k
The AVC and DVC voltages are arithmetically amplified
and output as the VOFST voltage.
The VOFST voltage serves as the level shift reference
voltage, and is distributed to each system.
40k
DVC
AVC
VOFST
40k
40k
AVC
• SW
This controls the laser (APC) on/off, active/sleep mode, and RW/ROM mode switching.
Switching is controlled by the voltage applied to the SW pin (Pin 12).
Active/Sleep
12
RSW
(ofst)
RW/ROM
APC_ON/OFF
The VC buffer is kept active even in sleep mode.
In the function block, BGR and MODE_SW are always set to active mode.
Item
APC
Active/Sleep
RW/ROM
VCC
ON
Active
RW
VC or Hi-Z
OFF
Sleep
—
GND
ON
Active
ROM
Control voltage
– 17 –
CXA2571N
Notes on Operation
[RFAC signal]
Stabilizing the RFAC signal
The RFAC system (RFSUM + EQ) is comprised entirely of non-inverted function blocks.
This is in order to support pickups with built-in RFSUM.
Therefore, if the voltage gain of each block is increased, a feedback loop is formed over the entire RFAC
system causing the RFAC signal to become unstable (oscillate).
In these cases, it is recommended to lower the EQ frequency response and the boost gain. This has a large
effect on the board (power supply, I/O signal cross talk, etc.) loop. The RFAC signal easily becomes unstable if
the VCA gain is increased, the EQ boost frequency is set to a high frequency, the EQ boost amount is
increased, etc.
The VCA gain is low in ROM mode, so the RFAC signal is stable.
The area where the RFAC signal becomes unstable is thought to vary for each set, as this is greatly affected
by the board loop as noted above.
Proposed stabilization measures
The board and other loop characteristics can be changed by adding external capacitance as noted below.
This has a particularly large effect on the stabilization when using RFSUM.
RF
SUM
0.1µ
VCA
ACSUM
EQ
AMP
EQI
Add capacitance of 10pF to 20pF
[Limiter circuit]
This IC has a limiter circuit to protect the input range of the rear-end IC (DSP) during excessive voltage output
for each signal (RFDC, FE, TE, CE).
When the limiter circuit operates, the maximum output voltage is limited to the DVCC voltage or less.
However, when limiting the excessive voltage output, the ON/OFF operation of the limiter circuit causes the
maximum output side (clipped portion of the output waveform) to oscillate slightly.
Example) AVcc = 5V, DVcc = 3V
3.0V
0V
– 18 –
CXA2571N
Example of Representative Characteristics
EQ Rfc resistance value – Frequency response
EQ boost voltage – Frequency response
10
14
Rfc = 100kΩ
Vboost = 1.0V
Vbst = VC, Vfc = VC
9
12
Rfc = 20kΩ
Rfc = 5.1kΩ
8
8
Rfc = 100kΩ
Vboost = 0V
6
[dB]
[dB]
6
5
4
4
2
3
0
2
–2
1
–4
1
0.1
10
100
Rfc = 100kΩ
Vboost = 1.0V
0.1
10
EQ Vfc frequency response
RF AC frequency response
20
Rfc = 20kΩ
Vfc = 0V
9
8
Vbst = VC
AC SUM
17
Rfc = 20kΩ
Vfc = 1V
14
Rfc = 20kΩ
Vfc = –1V
7
8
[dB]
[dB]
EQ_Pass
RW mode
11
6
5
5
4
2
3
–1
2
–4
1
–7
1
0.1
10
100
EQ_Pass
ROM mode
0.1
1
10
100
[MHz]
[MHz]
RF DC frequency response
FE frequenxy response
38
34
35
31
RW
32
28
29
25
26
22
23
[dB]
[dB]
100
[MHz]
10
ROM
19
20
16
17
13
14
10
11
7
8
Rfc = 5.1kΩ
Vboost = 1.0V
1
[MHz]
0
Vfc = VC
Rfc = 5.1kΩ
Vboost = 0V
10
Rfc = 100kΩ
7
0
Rfc = 5.1kΩ
Vboost = 1.0V
0.1
1
10
4
0.01
100
[MHz]
RW
ROM
0.1
1
[MHz]
– 19 –
10
CXA2571N
APC I/O characteristics
TE frequency response
35
5.5
32
5.0
RW
4.5
VLD – Output voltage [V]
29
26
[dB]
23
20
ROM
17
16
4.0
VCC = 5.5V
3.5
3.0
2.5
2.0
VCC = 3.0V
13
1.5
10
1.0
0.01
0.1
1
0.5
0.05
10
[MHz]
CE I/O characteristics (DC voltage input)
2.5
BC input,
RW mode
2.5
2.0
BC input,
ROM mode
2.0
Output voltage [dB]
Output voltage [V]
0.25
CE frequency response
3.0
AVCC = 5V,
DVCC = 3V
1.5
AD input,
ROM mode
1.0
0
0.1
0.2
Input voltage [V]
BC input
1.5
AD input
1.0
AD input,
RW mode
0.5
0
0.1
0.15
0.2
VPD – Input voltage [V]
AVCC = 5V, DVCC = 3V
Input signal amplitude = 100mVp-p
0.3
0.5
0.4
– 20 –
0.1
1
10
Input frequency [MHz]
100
CXA2571N
Package Outline
Unit: mm
30PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗9.7 ± 0.1
1
+ 0.1
0.22 – 0.05
7.6 ± 0.2
16
∗5.6 ± 0.1
30
0.10
A
15
+ 0.05
0.15 – 0.02
0.65
0.13 M
0.5 ± 0.2
0.1 ± 0.1
0° to 10°
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-30P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
SSOP030-P-0056
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 21 –