CXA3197R 10-bit 125MSPS D/A Converter Description The CXA3197R is a high-speed D/A converter which can perform multiplexed input of two system 10-bit data. This IC realizes a maximum conversion rate of 125MSPS. Multiplexed operation is possible by inputing the 1/2 frequency-divided clock or by halving the frequency of the clock internally with the clock frequency divider circuit having the reset pin. The data input is at TTL level, and the clock input and reset input can select either TTL or PECL level according to the application. 48 pin LQFP (Plastic) LEAD TREATMENT: PALLADIUM PLATING Structure Bipolar silicon monolithic IC DGND2 C2 C1 C3 DVCC2 AVCCO Applications • LCD • DDS • HDTV • Communications (QPSK, QAM) • Measuring devices AOUTN AGND2 VREF VSET AVCC2 Pin Configuration AOUTP Features • Maximum conversion rate: During PECL operation: 125MSPS During TTL operation: 100MSPS • Resolution: 10 bits • Low power consumption: 480mW (typ.) • Data input level: TTL • Clock, reset input level: TTL and PECL compatible • 2:1 multiplexed input function • 1/2 frequency-divided clock output possible by the built-in clock frequency divider circuit • Voltage output (50Ω load drive possible) • Single power supply or ±dual power supply operation • Reset signal polarity switching function 36 35 34 33 32 31 30 29 28 27 26 25 AGND2 37 24 RESETN/E VOCLP 38 23 RESETP/E 22 RESET/T R POLARITY 39 INV 40 21 CLKN/E PS 41 20 CLKP/E DVCC1 42 19 CLK/T N.C. 43 18 DGND1 44 DIV2OUT 17 DIV2IN (MSB) DA9 45 16 DB0 (LSB) DA8 46 15 DB1 8 9 10 11 12 DB4 7 DB6 DA2 DA1 6 DB5 5 DB7 4 DB8 3 (LSB) DA0 2 (MSB) DB9 1 DA3 13 DB3 DA4 14 DB2 DA6 48 DA5 DA7 47 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97639-PS CXA3197R Absolute Maximum Ratings (Ta = 25°C) • Supply voltage AVCCO, AVCC2, DVCC2 AGND2, DGND2 DVCC1 AVCC2 – AGND2 AVCCO – AGND2 DVCC2 – DGND2 –0.5 to +6.0 –6.0 to +0.5 –0.5 to +6.0 –0.5 to +6.0 –0.5 to +6.0 –0.5 to +6.0 V V V V V V • Input voltage (Analog) (Digital) VSET AGND2 – 0.5 to AVCC2 + 0.5 V TTL input pin DGND1 – 0.5 to DVCC1 + 0.5 V PECL input pin DGND1 – 0.5 to DVCC1 + 0.5 V PS DGND1 – 0.5 to DVCC1 + 0.5 V (Others) VOCLP DGND1 – 0.5 to DVCC1 + 0.5 V • Storage temperature Tstg – 65 to +150 °C • Allowable power dissipation Pd 1.4 W (when mounted on a two-layer glass fabric base epoxy board with dimensions of 76mm × 114mm, t = 1.6mm) Recommended Operating Conditions [Single power supply] • Supply voltage Min. Typ. Max. AVCCO +4.75 +5.0 +5.25 AVCC2 +4.75 +5.0 +5.25 AGND2 –0.05 0.0 +0.05 DVCC1 +4.75 +5.0 +5.25 DGND1 –0.05 0.0 +0.05 DVCC2 +4.75 +5.0 +5.25 DGND2 –0.05 0.0 +0.05 • Input voltage (Analog) (Digital) VSET TTL input pin PECL input pin • • • • • VIH VIL VIH VIL [Dual power supply] Min. Typ. Max. –0.05 0.0 +0.05 –0.05 0.0 +0.05 –5.50 –5.0 –4.75 +4.75 +5.0 +5.25 –0.05 0.0 +0.05 –0.05 0.0 +0.05 –5.50 –5.0 –4.75 Min. AGND2 + 0.65 DGND1 + 2.0 Typ. DVCC1 – 1.05 DVCC1 – 3.2 VID∗1 0.5 (Others) VOCLP DGND1 + 2.4 CLK pulse width (for RECL CLK) tpw1 3.5 tpw0 3.5 Maximum conversion rate During PECL operation Fc 125 During TTL operation Fc 100 Load resistance RL 50 Analog output full-scale voltage VFS 1.5 RL ≥ 10kΩ RL = 50Ω VFS 0.75 Operating temperature Ta –20 0.8 50 2.0 1.0 ∗1 VID: Input Voltage Differential PECL input signal switching level DVCC1 VIH (Max.) VIL VID VIH VIL (Min.) DGND1 –2– Unit V V V V V V V Max. Unit AGND2 + 1.03 V V DGND1 + 0.8 V DVCC1 – 0.5 V DVCC1 – 1.4 V V DVCC1 V ns ns MSPS MSPS ≥ 10k Ω 2.1 1.05 +75 V V °C CXA3197R Pin Description [ Typical voltage level for a single power supply [Symbol] [Pin No.] [Description] DA0 to DA9 DB0 to DB9 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DGND2 C1 C2 C3 DVCC2 AVCCO AOUTN AOUTP AGND2 VREF VSET 1 to 6, 45 to 48 7 to 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Side A data input. TTL Side B data input. TTL 1/2 frequency-divided clock input. TTL 1/2 frequency-divided clock output. TTL TTL clock input. TTL PECL clock input. PECL PECL clock input. PECL TTL reset input. TTL PECL reset input. PECL PECL reset input. PECL Digital ground. 0V Function setting. TTL Function setting. TTL Function setting. TTL Digital power supply. 5V Analog output power supply. 5V (typ.) Negative analog output. AVCCO – VFS Positive analog output. AVCCO – VFS Analog ground. 0V Analog reference voltage. AGND2 + 1.25V Full-scale adjustment. AGND2 + 0.65V to AGND2 + 1.03V AVCC2 AGND2 VOCLP R POLARITY INV PS DVCC1 N.C. DGND1 36 37 38 39 40 41 42 43 44 Analog power supply. Analog ground. TTL High level clamp. Reset signal polarity switching. Analog output inversion. Power saving. Digital power supply. Not connected. Digital ground. –3– 5V 0V Clamp voltage TTL TTL TTL 5V — 0V ] [ Typical voltage level for dual power supply TTL TTL TTL TTL TTL PECL PECL TTL PECL PECL –5V TTL TTL TTL 0V 0V (typ.) AVCCO – VFS AVCCO – VFS –5V AGND2 + 1.25V AGND2 + 0.65V to AGND2 + 1.03V 0V –5V Clamp voltage TTL TTL TTL 5V — 0V ] CXA3197R Block Diagram DVCC1 DVCC2 VOCLP INV PS 42 29 38 40 41 36 AVCC2 DA0 to DA9 1 to 6 45 to 48 10bit Input Latch A 30 AVCCO 10bit RO = 50Ω 10bit MUX 32 AOUTP 10bit Latch 31 AOUTN 10bit DB0 to DB9 Input Latch B 7 to 16 10bit AGND2 DIV2OUT 18 Current Cont. D DIV2IN 17 Q BGR Q 34 VREF CLK/T 19 CLKP/E 20 CLKN/E 21 35 VSET RESET/T 22 RESETP/E 23 RESETN/E 24 33 R POLARITY 39 37 44 DGND1 25 26 27 28 DGND2 C1 C2 C3 –4– AGND2 CXA3197R Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol 1 to 6 45 to 48 DA0 to DA9 I/O Typical voltage level I Equivalent circuit TTL Description Side A data input. DVCC1 1 to 6 45 to 48 7 7 to 16 DB0 to DB9 I TTL to 16 1.5V DGND1 Side B data input. DVCC1 17 DIV2IN I TTL 17 1.5V DGND1 DVCC1 DIV2OUT O 18 TTL 100K 18 DGND1 1/2 frequency-divided clock input. Use this pin in MUX.1A or MUX.2 mode. Leave open for other modes. 1/2 frequency-divided clock output. The 1/2 frequencydivided clock signal (DIV2OUT) is output in MUX.1A mode. Set to high impedance for other modes. DVCC1 19 CLK/T I TTL 19 1.5V DGND1 –5– Clock input. Use this pin when the clock is input at TTL level. At this time, leave Pins 20 and 21 open. CXA3197R Pin No. Symbol I/O Typical voltage level Equivalent circuit Description Clock input. Use this pin when the clock is input at PECL level. At this time, leave Pin 19 open. CLKP/E and CLKN/E are complementary and should be used together. DVCC1 20 CLKP/E I PECL 20 21 DGND1 21 CLKN/E I CLKP/E complementary input. PECL DVCC1 22 RESET/T I TTL 22 1.5V DGND1 23 RESETP/E I PECL DVCC1 23 24 24 RESETN/E I PECL DGND1 Single power supply: GND Dual power supply: –5V 25 DGND2 26 C1 I TTL 27 C2 I TTL Digital power supply. Function setting. DVCC1 26 Function setting. 27 28 28 C3 I TTL Reset signal input. When multiple CXA3197R are operated at the same time in MUX.1A or MUX.1B mode, the start timing of the internal 1/2 frequency divider circuits should be matched. At this time, the reset signal is used; when the reset signal is at TTL level, Pin 22 is used and Pins 23 and 24 are left open. When the reset signal is at PECL level, Pins 23 and 24 are used and Pin 22 is left open. The reset signal polarity can be set by Pin 39 (R POLARITY). Leave the reset pin open when other modes are used. RESETP/E and RESETN/E are complementary and should be used together. 1.5V Function setting. DGND1 –6– CXA3197R Pin No. 29 30 Symbol I/O Typical voltage level DVCC2 AVCCO Equivalent circuit Description Single power supply: +5V Dual power supply: GND Digital power supply. Single power supply: +5V Dual power supply: GND Analog output power supply. The AVCCO pin voltage can be varied within the range that satisfies the analog output compliance voltage. AVCCO – VFS Negative analog output. The inverse of the positive analog output pin is output. When the positive output is terminated with 50Ω, the inverse output pin should also be terminated with 50Ω even if the inverse output is not used. AVCCO RO RO 31 31 AOUTN O 32 AGND2 32 33 AOUTP O AGND2 AVCCO – VFS Positive analog output. Single power supply: GND Dual power supply: –5V Analog ground. AVCC2 34 VREF O AGND + 1.25V (Typ.) BGR 34 Reference voltage output. AGND2 AVCC2 35 VSET I AGND2 + 0.65V to AGND2 + 1.03V 35 Analog output full-scale adjustment. AGND2 36 AVCC2 Single power supply: +5V Dual power supply: GND Analog power supply. –7– CXA3197R Pin No. 37 Symbol I/O Typical voltage level AGND2 Equivalent circuit Description Single power supply: GND Dual power supply: –5V Analog power supply. Clamp voltage TTL output High level clamp. A TTL level signal is output from the DIV2OUT pin in MUX.1A mode. The TTL High level voltage can be clamped to the value approximately equivalent to the voltage applied to this pin. Leave the VOCLP pin open for other modes. DVCC1 38 VOCLP I 38 DGND1 DVCC1 39 R POLARITY I TTL 39 1.5V Reset signal polarity switching. At High level, the reset polarity is active Low; at Low level, active High. DGND1 DVCC1 40 INV I TTL 40 1.5V Analog output polarity inversion. The analog output is inverted at Low level. DGND1 DVCC1 41 41 PS I TTL Power saving. Power saving mode is activated at Low level. Normally pull up the PS pin to High level as this pin is open Low. DGND1 42 DVCC1 43 N.C. 44 DGND1 Digital power supply. 5V Not connected. Digital ground. 0V –8– CXA3197R Electrical Characteristics (DVCC1, DVCC2, AVCC2, AVCCO = +5V, DGND1, DGND2 = 0V, Ta = 25°C) Item Symbol Resolution n Differential linearity error DLE Integral linearity error ILE Digital input (PECL) Digital input voltage Digital input current VIH VIL IIH IIL Conditions VFS = 1000mV Min. Typ. Max. Unit 10 10 10 bit –0.85/+0.5 –1.2/+0.5 ±1.2 LSB LSB LSB DVCC1 – 0.5 DVCC1 – 1.4 20 0 5 V V µA µA pF ∗2 DVCC1 – 1.05 DVCC1 – 3.2 0 –30 VIH = DVCC1 – 0.8V VIL = DVCC1 – 1.6V Digital input capacitance Digital input (TTL) Digital input voltage Threshold voltage Digital input current VIH VIL VTH IIH IIL VOH VOL Leak current at high impedance Digital output rise time Digital output fall time PS pin input (PS) PS pin input voltage PS pin input current Clamp pin (VOCLP) VOCLP pin input current Analog output characteristics Output full-scale voltage : RL ≥ 10kΩ : RL = 50Ω Output zero offset voltage : RL ≥ 10kΩ : RL = 50Ω Analog output resistance Analog output capacitance Absolute amplitude error Absolute amplitude error temperature characteristics Analog output rise time Analog output fall time Settling time Glitch energy Compliance voltage Tr Tf 0.5 100 1 1.5 1.2 V V µA µA ns ns V V µA µA 0.8 1.5 VIH = 3.5V VIL = 0.2V –1 –2 IOH = –2.0mA IOL = 1.0mA When VO = 5V When VO = 0V 0.8 to 2.4V (CL = 10pF) 0.8 to 2.4V (CL = 10pF) 2.4 Digital input capacitance Digital output (TTL) Digital output voltage 1 0 5 V V V µA µA pF 2 10 –1 1 0.6 2 VIH VIL IIH IIL VIH = 3.5V VIL = 0.2V 1 –1 0.8 100 0 IVOCLP IVOCLP VOCLP = DVCC1 VOCLP = 2.4V 0 –60 5 –10 µA µA 2.1 1.05 V V 20 10 mV mV 4.0 Ω pF % of F.S. 60 ppm/°C 1.05 0.85 3.5 5 1.5 ns ns ns pVsec V 1.5 0.75 VFS VFS VOF VOF }V SET = AGND2 + 937.5mV 0 0 50 10 RO CO EG VSET = AGND2 + 937.5mV TCG VFS = 1000mV at 25°C Tr Tf R = 50Ω, } When V = 1V,10 – 90% –4.0 0.85 0.75 L FS tSET GE VOC 2 1 Mesured to DVCC2 –9– ∗3 –2.1 CXA3197R Item Symbol Reference/control amplifier characteristics VREF pin output voltage VREF VREF pin output voltage VREF in PS mode VREF voltage drift coefficient ISET VSET pin input current Multiplying bandwidth Current consumption ICC DICC1 DICC2 AICC2 AICCO Current consumption in PS ICC mode ∗4 DICC1 DICC2 AICC2 AICCO ∗2 64-step D.L.E. Conditions }I REFOUT = 1mA 100mVp-p, SIN, at –3dB Total current consumption DIcc1 current consumption DIcc2 current consumption AIcc2 current consumption AIccO current consumption Min. Typ. Max. AGND2 + 1.18 AGND2 + 1.25 AGND2 + 1.32 AGND2 + 1.18 AGND2 + 1.25 AGND2 + 1.32 –5 50 Unit V V 250 ppm/°C 0 µA MHz 63 96 129 mA 7 15.5 24 mA 13 19 25 mA 6 8.5 11 mA 37 53 69 mA 0.432 4 mA 0.38 1.5 mA 0.001 0.2 mA 0.05 0.3 mA 0.001 2 mA Total current consumption in PS mode DIcc1 current consumption in PS mode DIcc2 current consumption in PS mode AIcc2 current consumption in PS mode AIccO current consumption in PS mode This indicates the D.L.E. when the INV pin is High and the data input code changes between: (MSB) (LSB) (MSB) (LSB) 0 0 0 0 1 1 1 1 1 1 ←→ 0 0 0 1 0 0 0 0 0 0 at the AOUTP side output or between: (MSB) (LSB) (MSB) (LSB) 1 1 1 1 0 0 0 0 0 0 ←→ 1 1 1 0 1 1 1 1 1 1 at the AOUTN side output. ∗3 When using the analog output within the compliance voltage range, set AVCCO so that it satisfies the following equations. VOC (min) = (AVCCO – VFS) – DVCC2 ≥ –2.1V VOC (max) = (AVCCO – VOF) – DVCC2 ≤ 1.5V – 10 – CXA3197R ∗4 The current consumption in power saving mode does not include the VREF pin output current. When grounding the VREF pin to the AGND2 level using external resistance, a voltage of 1.18 to 1.32V is generated at the VREF pin even in power saving mode. Therefore, the current indicated by the following equation flows from the AVCC2 pin to the VREF pin. This value must be added to obtain the actual current consumption in power saving mode. VREF pin voltage = IREFOUT External resistance AVCC2 BGR 34 VREF In power saving mode: IREFOUT = AGND2 – 11 – VREF pin voltage External resistance MUX.1A mode MUX.1B mode Switching characteristics – 12 – Analog output delay 3 5.5 tPD (B) tdo 5.0 2 4.0 th Data input hold time tPD (A) 1.0 ts Data input setup time Analog output pipeline delay 1.0 th-rst Reset signal hold time 3.5 Tpw0 Clock Low pulse width 0 3.5 Tpw1 Clock High pulse width ts-rst 125 FC Maximum conversion rate Reset signal setup time 5.5 5.0 tdo Analog output delay 4 5 tPD (A) 5.0 6.5 tPD (B) Analog output pipeline delay th ts Data input setup time Data input hold time 2T-tm DIV2OUT to DIV2IN maximum delay time 1.0 5.5 CL = 10pF td-DIV DIV2OUT output delay 0 ts-rst Reset signal setup time 1.0 3.5 Tpw0 Clock Low pulse width th-rst 3.5 Tpw1 Clock High pulse width Reset signal hold time 125 FC Symbol Conditions Min. Typ. PECL Reset signal level Maximum conversion rate Item PECL CLK signal level 6.0 6.0 2T – 7 8 Max. 6.5 8.5 5.5 7.5 5.0 3 4.0 6.0 3 1.0 1.0 2 0 3.0 5.5 5 4 6.5 2 4.0 3.5 3.0 1.0 3.5 5.0 5.0 1.0 5.5 0 4.0 3.5 3.5 125 4.5 8.5 2T – 7 12.0 TTL 8 Max. 6.0 6.0 2T – 7 PECL Min. Typ. 125 7.5 5 4 9.5 Max. 100 6.5 5.0 1.0 8.0 3.0 1.0 3.0 4.5 100 Min. Typ. TTL TTL ns CLK ns ns ns ns ns ns MSPS ns CLK ns ns ns ns ns ns ns ns MSPS Unit CXA3197R MUX.2 mode – 13 – Switching characteristics ts th Data input setup time Data input hold time tdo 5.0 2.0 5.5 1 th Data input hold time 1.0 tPD (B) ts Data input setup time 2.5 1.0 3.5 3.5 125 5.5 1 th-C2 C2 signal hold time Analog output delay 5.0 tPD (A) ts-C2 C2 signal setup time Analog output pipeline delay Tpw0 Tpw1 Clock High pulse width Clock Low pulse width FC tdo Maximum conversion rate Analog output delay 5.0 1.0 0 3 th-DIV DIV2IN hold time 4.5 tPD (B) ts-DIV DIV2IN setup time 3.5 2 Tpw0 Clock Low pulse width 3.5 125 Min. Typ. PECL — ∗4 tPD (A) Tpw1 Clock High pulse width Analog output pipeline delay FC Symbol Conditions Maximum conversion rate Item Reset signal level ∗4 The reset signal is not input in MUX.2, SELE.A or SELE.B mode. SELE.A, SELE.B modes CLK signal level 6.0 6.0 Max. 6.5 3.5 1.5 3.5 1.0 3.0 4.5 100 6.5 5.0 1.0 3.5 2.0 3.0 4.5 100 7.5 1 1 7.5 3 2 Min. Typ. TTL — ∗4 8.5 8.5 Max. ns CLK ns ns ns ns ns ns MSPS ns CLK ns ns ns ns ns ns MSPS Unit CXA3197R CXA3197R Electrical Characteristics Measurement Circuits +5V Differential Linearity Error Integral Linearity Error DVCC1 DGND1 DVCC2 AVCC2 AVCCO AOUTP DA0 to DA9 10 10-bit Data input 50Ω CXA3197R DB0 to DB9 10 AOUTN DVM (Digital Voltmeter) 50Ω VSET CLK/T DGND2 AGND2 1MHz TTL CLK C1 C2 C3 937.5mV PC –5V –5V +5V Current Consumption +5V I1 I2 I3 ICC = I1 + I2 + I3 + I4 DICC1 = I1 DICC2 = I2 AICC2 = I3 AICCO = I4 I4 DVCC1 DVCC2 AVCC2 AVCCO High for all side A data Low for all side B data DA0 to DA9 DB0 to DB9 10 10 AOUTP AOUTN CXA3197R VSET CLK/T 1MHz TTL CLK 937.5mV DIV2IN +5 DIV2OUT DGND1 DGND2 AGND2 PS C1 C2 C3 Analog Output Characteristics Output Full-Scale Absolute Amplitude Error Output Zero Offset Voltage High for all side A data Low for all side B data +5V DVCC1 10 DA0 to DA9 10 DB0 to DB9 DGND1 DVCC2 AVCC2 AOUTP AVCCO 50Ω CXA3197R AOUTN CLK/T 1MHz TTL CLK +5 50Ω VSET INV C1 C2 C3 DGND2 AGND2 937.5mV –5V –5V +5 – 14 – CXA3197R Analog Output Rise Time Analog Output Fall Time Settling Time Glitch Energy Oscilloscope +5V 50Ω 50Ω DVCC1 10 D. P. G. (Digital Pattern Generator) 10 DA0 to DA9 DB0 to DB9 DGND1 DVCC2 AVCC2 AOUTP AVCCO AOUTN CXA3197R CLKP/E CLKN/E VREF 100MHz PECL CLK VSET DGND2 AGND2 C1 C2 C3 –5V +5V –5V Reference/Control Amplifier Characteristics VREF Pin Output Voltage VREF Pin Output Voltage in Power Saving Mode Multiplying Bandwidth Oscilloscope +5V DVCC1 High for all side A data High for all side B data 10 10 DA0 to DA9 DB0 to DB9 DGND1 DVCC2 AVCC2 AVCCO AOUTP AVCCO (= 0V) AOUTN CLKP/E CLKN/E VFS 50Ω CXA3197R AOUTP output VREF 1mA 20MHz PECL CLK +5V 50Ω 0.1µF VSET PS C1 C2 C3 DGND2 AGND2 50Ω –5V +5V –5V – 15 – VSET pin output 100mVp-p AGND2 + 937.5mV CXA3197R AVCCO AVCCO – VOF AOUTP output (INV = 1) AVCCO – VFS (AVCCO – VOF) – (AVCCO – VFS) 1023 D.L.E. = I.L.E. = V (n + 1) = 1LSB V (n + 1) – V (n) –1 1LSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 V (n) – n × 1LSB 1LSB 1 1 1 1 1 1 1 1 0 1 · · · · · · · · · · · V (n) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 D9 (MSB) Data input code Data input code INV = 1 (MSB) D9 0 D0 (LSB) Analog output level INV = 0 (LSB) D0 1 1 1 1 1 1 1 1 1 1 : 0 0 0 0 0 0 0 0 0 0 (MSB) D9 (LSB) D0 0 0 0 0 0 0 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 Table 1. I/O Correspondence Table – 16 – AOUTP AOUTN AVCCO – VOF : AVCCO – VFS AVCCO – VFS : AVCCO – VOF CXA3197R Description of Operation The CXA3197R has four types of operation modes to support various applications. The operation mode is set by switching the function setting pins (C1, C2 and C3). Operation Mode Table Mode C1 C2 C3 MUX.1A 0 0 0 MUX.1B 0 0 1 0 1 0 SELE.A 1 0 0 SELE.B 1 1 0 MUX.2 CLK IN Data IN AOUT (MSPS) (Mbps) (Mbps) 62.5 125 125 DIV2OUT pin Description of operation Outputs CLK/2 at TTL level MUX operation by the internal CLK/2 High impedance MUX operation by the internal CLK/2 High impedance MUX operation by DIV2IN High impedance D/A conversion of side A data input High impedance D/A conversion of side B data input 125 The CXA3197R can input data divided into two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplex the data, and output it as an analog signal, making it possible to halve the data rate. This lets the CXA3197R support the TTL data input level in contrast to the ECL data input level for conventional high-speed D/A converters. The clock signal and reset signal input levels can be selected from either TTL or PECL according to the application. (However, setting both signals to either TTL or PECL input level is recommended.) 1. MUX.1A mode Set C1, C2 and C3 all Low for this mode. In MUX.1A mode, the frequency of the clock input from the clock input pin is halved internally, and the 1/2 frequency-divided signal is output at TTL level from the DIV2OUT pin. Data synchronized with the DIV2OUT signal (the signal output from the DIV2OUT pin) can be obtained by operating the CXA3197R front-end system with the DIV2OUT signal. The timing at which the data output delay of the CXA3197R front-end system matches with the hold time during CXA3197R data input can be easily set by inputting this synchronized data to the data input pins and the DIV2OUT signal to the DIV2IN pin. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplexed, and extracted as analog output. Clock input pin Clock input 1/2 td – DIV DIV2OUT pin (DIV2OUT signal) DIV2IN pin CXA3197R front-end system CXA3197R (MUX.1A mode) 10bit Data. A DA0 to DA9 10bit Data. B DB0 to DB9 10bit 10bit Data input pins Front-end system data output delay = CXA3197R data input hold time – 17 – CXA3197R When using the multiple CXA3197R in MUX.1A mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below. As a countermeasure, the MUX.1A mode has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See the timing chart for the detailed timing. Example when not using the reset signal CLK CXA3197R CLK DIV2OUT CLK DIV2OUT CXA3197R DIV2OUT CLK DIV2OUT Example when using the reset signal CLK CXA3197R CLK CLK DIV2OUT Reset signal (when active Low) DIV2OUT RESET CXA3197R CLK DIV2OUT Reset signal DIV2OUT RESET – 18 – CXA3197R 2. MUX.1B mode Set C1 and C2 Low and C3 High for this mode. In MUX.1B mode, the frequency of the clock input from the clock input pin is halved internally, and the data is loaded by this 1/2 frequency-divided signal. The 1/2 frequency-divided signal cannot be observed at this time, so the data is actually loaded by observing the clock and reset signals to estimate the rising edge of the internally 1/2 frequency-divided signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3-clock pipeline delay after loading by the clock. Clock input pin Clock th-rst CXA3197R (MUX.1B mode) 1/2 ts-rst Reset signal (when active Low) Reset input pin Internally 1/2 frequency-divided signal (This signal cannot be observed.) ts DA0 to DA9 th DB0 to DB9 Data input signal After the reset is released, the internal 1/2 frequency-divided signal commences at the first clock edge, so be sure to input the data in a manner that satisfies the setup time (ts) and hold time (th) with respect to this clock edge. – 19 – CXA3197R Like MUX.1A mode, when using the multiple CXA3197R in MUX.1B mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below. As a countermeasure, the MUX.1B mode also has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See the timing chart for the detailed timing. Example when not using the reset signal CLK CXA3197R CLK CLK CXA3197R CLK Internally 1/2 frequency-divided signal Internally 1/2 frequency-divided signal Example when using the reset signal CLK CXA3197R CLK CLK Reset signal (when active Low) Internally 1/2 frequency-divided signal RESET CXA3197R CLK RESET signal Internally 1/2 frequency-divided signal RESET – 20 – CXA3197R 3. MUX.2 mode Set C1 and C3 Low and C2 High for this mode. In MUX.2 mode, the clock is input to the clock input pin, and the signal with a cycle half that of the clock (hereafter, DIV2IN signal) is input to the DIV2IN pin at TTL level. The DIV2IN signal is internally latched by the clock, so consideration must be given to the setup time (ts_DIV) and hold time (th_DIV) with respect to the clock. In addition, the data is loaded by the DIV2IN signal, so consideration must also be given to the setup time (ts) and hold time (th) with respect to the DIV2IN signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3clock pipeline delay from the clock that loads the DIV2IN signal. See the timing chart for the detailed timing. tPD (B) tPD (A) 0 1 CXA3197R (MUX.2 mode) 2 Clock input pin 3 Clock ts_DIV th_DIV DIV2IN input pin DIV2IN signal ts th DA0 to DA9 System A data A0 A1 A2 System B data B0 B1 B2 DB0 to DB9 Analog output signal A0 B0 A1 – 21 – B1 CXA3197R 4. SELE.A mode and SELE.B mode Set C1 High and C2 and C3 Low for SELE.A mode. In SELE.A mode, the clock is input to the clock input pin, and the data is input to the system A (DA0 to DA9) data input pins. Set C1 and C2 High and C3 Low for SELE.B mode. In SELE.B mode, the clock is input to the clock input pin, and the data is input to the system B (DB0 to DB9) data input pins. In either mode, consideration must be given to the setup time (ts) and hold time (th) with respect to the clock. Also, the data is output as an analog signal with a 1-clock pipeline delay after loading by the clock. Switching between SELE.A mode and SELE.B mode is done by switching the C2 pin between High and Low levels. Also, the mode can be switched at high speed in sync with the clock by inputting the switching signal (C2 signal) to the C2 pin. The C2 signal is internally latched by the clock, so consideration must be given to the setup time (ts_C2) and hold time (th_C2) with respect to the clock. See the timing chart for the detailed timing. tPD (A) 0 CXA3197R (SELE.A mode/SELE.B mode) tPD (B) 1 0 Clock input pin 1 Clock ts_C2 th_C2 C2 input pin C2 signal ts th System A data A0 A1 A2 A6 A8 DA0 to DA9 Select System B data B3 Analog output signal A0 A1 B4 A2 B5 B3 DB0 to DB9 B7 B4 – 22 – B5 A6 CXA3197R Block Diagram & Timing Chart (MUX.1A Mode) CLK RESET R Q CLK/2 (Internal) D Q DIV2OUT DIV2IN Input Data A Input Latch A Latch MUX Input Data B Input Latch B Analog out DAC Latch Latch tPD (B) tPD (A) Tpw1 Tpw0 CLK RESET ts-rst th-rst (Active High) (Active Low) 0 1 2 4 3 5 td-DIV DIV2OUT tm DIV2IN 2T-tm ts th Input Data A N$ N$ N N+2 N+4 Input Data B N$ N$ N +1 N+3 N+5 tdo N$ N$ N$ N$ N N+1 tdo In MUX.1A mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit and the CLK/2 can be output at TTL level (DIV2OUT). CLK/2 can be reset by the reset signal. (Timing judgment points) CLK PECL TTL ±1/2LSB 2.0V 0.8V 2.0V 0.8V Analog output ±1/2LSB tdo – 23 – tSET CXA3197R Block Diagram & Timing Chart (MUX.1B Mode) CLK RESET R Q CLK/2 (Internal) D Q Input Data A Input Latch A MUX Input Data B Latch Analog out DAC Input Latch B tPD (B) Tpw1 Tpw0 tPD (A) CLK RESET (Active High) ts-rst th-rst (Active High) (Active Low) 0 1 2 3 D-FF out CLK/2 (Internal) ts th Input Data A N–2 N N+2 N+4 N+6 N+8 Input Data B N–1 N+1 N+3 N+5 N+7 N+9 tdo N N+1 N+2 N+3 N+4 N+5 tdo In MUX.1B mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit. CLK/2 can be reset by the reset signal. – 24 – CXA3197R Block Diagram & Timing Chart (MUX.2 Mode) CLK R Q DIV2IN CLK/2 (Internal) D Q Input Data A Input Latch A Latch MUX Input Data B Input Latch B Analog out DAC Latch Latch tPD (B) Tpw1 Tpw0 tPD (A) CLK ts-DIV th-DIV 0 1 2 3 DIV2IN ts th Input Data A N–2 N N+2 N+4 N+6 N+8 Input Data B N–1 N +1 N+3 N+5 N+7 N+9 tdo N N+1 N+2 N+3 N+4 N+5 tdo In MUX.2 mode, the 1/2 frequency-divided clock signal (DIV2IN) and Data A and Data B, which are synchronized with DIV2IN, are provided simultaneously. These signals are internally multiplexed and the resulting signal can be analog output. – 25 – CXA3197R Block Diagram & Timing Chart (SELE.A, SELE.B Mode) CLK C2 Latch Input Latch A Input Data A Select Analog out Input Latch B Input Data B Tpw1 DAC Latch Tpw0 tPD (A) tPD (B) CLK 0 1 0 ts-C2 th-C2 1 C2 ts th Input Data A N–2 N N+2 N+4 N+6 N+8 Input Data B N–1 N +1 N+3 N+5 N+7 N+9 C2 Latch OUT SELE. A SELE. B tdo tdo N–4 N N–2 N+2 N+5 N+7 In SELE.A and SELE.B modes, input Data A or Data B is selected and the selected data can be analog output. When C1 = 1 and C3 = 0, Data A is selected for C2 = 0, and Data B is selected for C2 = 1. – 26 – CXA3197R Application Circuit The circuit shown below is the basic circuit when the analog output is terminated with external resistance of 50Ω for operation with dual ±5V power supply in MUX.2 mode. The analog output uses AVCCO as the reference. The analog output full-scale voltage VFS is obtained with the following equation. VFS = VSET 63 × (15 + )×R 375 64 Here, VSET = R = RO//RL RO: Output impedance (= 50Ω) RL: External termination resistance R2 VREF R1 + R2 –5V(A) 0V(D) +5V(D) (VREF ≈ 1.2V) (R1 + R2 ≥ 1.2kΩ) 0V(A) VOCLP AGND2 R POLARITY INV PS DVCC1 NC DGND1 DA8 VREF 34 4 DA2 AGND2 33 5 DA1 AOUTP 32 6 DA0 (LSB) AOUTN 31 7 DB9 (MSB) AVCCO 30 8 DB8 DVCC2 29 9 DB7 C3 28 10 DB6 C2 27 R1 R2 –5V(A) –5V(A) 0V(A) 0V(A) RL 0V(A) 0V(D) RL C1 26 RESETN/E RESETP/E RESET/T CLKN/E CLK/T DB1 DB3 DB2 12 DB4 CLKP/E 11 DB5 DIV2OUT DB0 to DB9 VSET 35 DA3 DIV2IN RAM · Latch · etc 2 DA4 0V(A) AVCC2 36 3 DB0 (LSB) DA0 to DA9 DA5 (MSB) DA9 1 DA7 DA6 48 47 46 45 44 43 42 41 40 39 38 37 DGND2 25 0V(A) –5V(D) +5V(D) 13 14 15 16 17 18 19 20 21 22 23 24 TTL CLK/2 PECL CLK 82 130 0V(D) 82 130 VBB Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 27 – CXA3197R Notes on Use • The CXA3197R has PECL and TTL input pins for the clock and reset inputs. When the clock is input at PECL level, it is recommended to also input the reset signal at PECL level. Likewise, when the clock is input at TTL level, it is recommended to also input the reset signal at TTL level. • The input signal impedance should be properly matched to ensure the stable CXA3197R operation at high speed. Particularly when ringing appears in the input clock in the MUX.1A and MUX.1B modes, if this ringing exceeds the clock input threshold value, the internal 1/2 frequency divider circuit may misoperate. • All TTL input pins of the CXA3197R except for the PS pin go to High level when left open, and only the PS pin goes to Low level when left open. Set the PS pin to High level to operate the IC. When the PECL input pins are left open, the P (positive) side goes to High level and the N (negative) side goes to Low level. The PECL input pins are complementary, so be sure to use the P and N sides together. • When the clock and reset input signal level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open. When the clock and reset input signal level is PECL, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. • The power supply and grounding have a profound influence on converter characteristics. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows. — The ground pattern should be as wide as possible. It is recommended to make the power supply and ground wider at an inner layer using a multi-layer board. To prevent a DC offset from being generated between the analog and digital power supply patterns, it is recommended to connect the patterns at one point via a ferrite-bead filter, etc. — When using the CXA3197R with a single power supply, connect DGND1 and DGND2 to a common digital ground, and AGND2 to an analog ground. Also, DVCC1 and DVCC2 should use a common digital power supply, and AVCC2 should be connected to an analog power supply. AVCCO serves as the analog output reference, so while it does not need to share the analog power supply, it should be used within the range that satisfies the analog output compliance voltage. — When using the CXA3197R with dual power supply, connect DGND1 and DVCC2 to the digital ground, and AVCC2 to the analog ground. DVCC1 uses a positive digital power supply (+5V, typ.), DGND2 uses a negative digital power supply (–5V, typ.), and AGND2 uses a negative analog power supply (–5V, typ.). Like when using a single power supply, the AVCCO pin can be used within the range that satisfies the analog output compliance voltage. However, connecting it to the analog ground and using the analog ground as the reference for the analog output is recommended. — Ground the power supply pins as close to each pin as possible with a 0.1µF or more ceramic chip capacitor. When using a single power supply, connect DVCC1 and DVCC2 to the digital ground, and AVCC2 and AVCCO to the analog ground. When using dual power supply, connect DVCC1 and DGND2 to the digital ground, and AGND2 to the analog ground. In this case, when using AVCCO within the range that satisfies the compliance voltage, be sure to also connect the AVCCO pin to the analog ground using a ceramic chip capacitor. • The CXA3197R is designed with an analog output impedance of 50Ω. The analog outputs are wired with a characteristic impedance of 50Ω, and waveforms free of reflection can be obtained by terminating the analog outputs with 50Ω. Even when using only one of either AOUTP or AOUTN, if one analog output is terminated with 50Ω, be sure to also terminate the other analog output with 50Ω. (See the Application Circuit.) – 28 – CXA3197R Example of Representative Characteristics Output full-scale voltage vs. VSET pin voltage Output full-scale voltage vs. Ambient temperature 1100 RL = 50Ω VSET = AGND2 + 937.5mW VFS – Output full-scale voltage [mV] Output full-scale voltage [mV] 1100 1000 900 RL = 50Ω 800 1050 1000 950 700 0.65 0.84 900 1.03 0 50 25 75 Ta – Ambient temperature [°C] VREF pin voltage vs. Ambient temperature Output zero offset voltage vs. Ambient temperature VOF – Output zero offset voltage [mV] VSET pin voltage [V] 1280 1260 1240 1220 0 –25 25 50 7 RL = 50Ω VSET = AGND2 + 937.5mW 6 5 4 3 75 –25 Ta – Ambient temperature [°C] 0 50 25 Ta – Ambient temperature [°C] Multiplying bandwidth 0 Analog output amplitude [dB] VREF pin voltage [mV] –25 –3 1 10 VSET pin input frequency [MHz] – 29 – 100 75 CXA3197R Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 25 A 13 48 (0.22) 0.5 ± 0.2 (8.0) 24 37 12 1 + 0.05 0.127 – 0.02 0.5 ± 0.08 + 0.2 1.5 – 0.1 + 0.08 0.18 – 0.03 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE LQFP-48P-L01 LEAD TREATMENT EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 30 –