CXB1573R Post-Amplifier for Optical Fiber Communication Receiver Description The CXB1573R achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is equipped with the signal detection function, which is used to enable TTL/ECL outputs. Also, the output disable function performs the output shutdown. 32 pin LQFP (Plastic) Features • Output disable function (TTL input) • Signal detection function (TTL/ECL output) Applications • SONET/SDH: • Fibre Channel: : • Gigabit-Ethernet: 622.08Mbps 531.25Mbps 1.062Gbps 1.25Gbps Absolute maximum Ratings • Supply voltage • Storage temperature • Input voltage difference | VD – VD | • SW input voltage • ECL output current • TTL output current (High level) • TTL output current (Low level) • D/DB input voltage • ODIS input voltage Recommended Operating Conditions • Supply voltage • Termination voltage (for data) • Termination voltage (for alarm 1,alarm 2) • Termination resistance (for data) • Termination resistance (for alarm 1) • Termination resistance (for alarm 2) • Operating temperature VCC – VEE Tstg Vdif Vi IOQ/SD-ECL IOH SD-TTL IOL SD-TTL –0.3 to +6 –65 to +150 0 to +2 VEE to VCC –30 to 0 –20 to 0 0 to 20 Vcc – 2 to Vcc VEE – 0.5 to VEE + 5.5 V °C V V mA mA mA V V 3.3 ± 0.2 1.8 to 2.2 VEE 46 to 56 240 to 300 460 to 560 –40 to +85 V V V Ω Ω Ω °C VCC – VEE VCC – VTD VTA RTD RTA1 RTA2 Ta Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98401-PS CXB1573R VEE4 VccZ CAP3 CAP2 VEE2 VEEI DN UP Block Diagram and Pin Configuration 24 23 22 21 20 19 18 17 VCC4 25 ∆V 16 VCC2 15 VEE1 14 D SD-TTL 26 peak hold peak hold SDB-TTL 27 SD-ECL 28 SDB-ECL 29 13 DB 12 CAP1 11 CAP1B Q 30 10 VccY QB 31 VCC3 32 ODIS SW VCC2 5 6 7 8 TM 4 VEE1 3 VEE2 2 VccX 1 VEE3 9 –2– VCC1 CXB1573R Pin Description Pin No. Symbol Typical pin voltage (V) DC 1 VEE3 Equivalent circuit Description AC Negative power supply for ECL output buffer. 0 VCC2 10k 2 ODIS 0 or 3.3 (Open) VREF 2 300 10k Controls the output shutdown function. High voltage when open; the Q output is fixed to Low. Low voltage when connected to VEE; the D input results in the Q output with ECL level. TTL level is also available. VEE2 VCC2 3 SW 0 or 3.3 (Open) Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 40mVp-p. Low voltage when connected to VEE; the amplitude becomes 20mVp-p. 60k 3 40k VEE2 4 VCC2 3.3 Positive power supply for digital block. 5 VccX 3.3 Positive power supply for digital block. 6 VEE2 0 Negative power supply for digital block. 7 VEE1 0 Negative power supply for analog block. 8 TM 8 7 Chip temperature monitor. 1.6 VEE1 9 VCC1 Positive power supply for analog block. 3.3 –3– CXB1573R Pin No. Symbol 10 VccY 11 CAP1B 12 CAP1 Typical pin voltage (V) DC Equivalent circuit AC Positive power supply for analog block. 3.3 VCC1 7.5k 14 13 DB Description 2 1.6 to 2.4 200 12 100p 13 11 1k 7.5k 200 1k 14 D 2 15 VEE1 0 16 VCC2 3.3 17 UP 1.6 to 2.4 VEE1 Negative power supply for analog block. Positive power supply for digital block. VCC2 986 140.9 18 Pins 11 and 12 connect a capacitor which determines the cut-off frequency for DC feedback block. Pins 13 and 14 are input pins for limiting amplifier block. Input the signal with AC coupled. DN 140.9 17 Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor by shorting the VEEI pin to VEE. 100 18 100 SW VCS SW 19 VEEl 0 VEE2 19 20 VEE2 Generates the default voltage between UP and DOWN. The voltage (8.0mV for input conversion) can be generated between UP and DOWN (Pins 17 and 18) as alarm setting level by connecting this pin to VEE. Negative power supply for digital block. 0 –4– CXB1573R Pin No. Symbol Typical pin voltage (V) DC Equivalent circuit Description AC 21 VCC2 80 10p 21 CAP2 1.5 200 5µA VEE2 22 VCC2 80 10p 22 CAP3 1.5 Connects a peak hold circuit capacitor for alarm block. 470pF should be connected to Vcc each. CAP2 pin connects a peak hold capacitor for alarm level setting block. CAP3 pin connects a peak hold capacitor for limiting amplifier signal. 200 5µA VEE2 3.3 Positive power supply for ECL output buffer. VEE4 0 Negative power supply for TTL output buffer. VCC4 3.3 Positive power supply for TTL output buffer. 23 VccZ 24 25 VCC4 26 SD-TTL VEE or 2.2 26 40k VEE4 –5– Alarm signal TTL level output. CXB1573R Pin No. Symbol Typical pin voltage (V) DC Equivalent circuit Description AC VCC4 27 VEE or 2.2 SDB-TTL Alarm signal TTL level output. 27 40k VEE4 28 1.6 or 2.4 SD-ECL VCC3 28 29 29 30 SDB-ECL 1.6 or 2.4 Q 1.6 or 2.4 VEE3 VCC3 30 31 31 QB 32 VCC3 Alarm signal ECL level output. Terminate this pin in 270Ω to VEE. 1.6 or 2.4 Data signal output. Terminates this pin in 50Ω to VTT = Vcc – 2V. VEE3 Positive power supply for ECL output buffer. 3.3 –6– CXB1573R Electrical Characteristics DC Characteristics Item VCC = 3.3 ± 0.2V, VEE = GND, Ta = –40 to +85°C Symbol Supply current IEE Q/QB High output voltage VOH Q/QB Low output voltage VOL SD-ECL/SDB-ECL High output voltage VOH-E Conditions 50Ω to VTT 270Ω to VEE SD-ECL/SDB-ECL Low output voltage VOL-E SD-TTL/SDB-TTL High output voltage VOH-T IOH = –0.4mA Ta = 0 to +85°C SD-TTL/SDB-TTL Low output voltage VOL-T IOL = 2mA Ta = 0 to +85°C SW High input voltage VIHSW at SW pin Open: High SW Low input voltage VILSW SW High input current IIHSW SW Low input current IILSW ODIS High input voltage VIHOD ODIS Low input voltage VILOD ODIS High input current IIHOD VIH = Vcc ODIS Low input current IILOD VIL = VEE D/DB input resistance Rin TM voltage VTM Min. Typ. –74 –51 Max. mA VCC – 1100 VCC – 860 VCC – 1860 VCC – 1620 VCC – 1100 VCC – 860 VCC – 1900 VCC – 1620 0.5 VCC – 0.5 VCC 0 0.5 –100 2.0 VCC + 0.5 0 0.8 20 –400 765 Iin = 1mA –7– mV 2.2 10 at ODIS pin Open: High Unit 1.2 1020 V µA V µA 1275 Ω 2.0 V CXB1573R AC Characteristics Item Maximum input voltage amplitude VCC = 3.3 ± 0.2V, VEE = GND, Ta = –40 to +85°C Symbol Vmax Conditions single-ended input Amplifier gain (excluding the output buffer) GL Identification maximum voltage amplitude of alarm level Min. Max. mVp-p 52 dB 20 SW: Open High, VmaxA2 single-ended input 40 mVp-p ∆P1 SW: Low, at default alarm level 3 ∆P2 SW: Open High, at default alarm level 3 6 7 Alarm setting level for default Vdef SW: Open High, VEEI = VEE, fin = 100Mbps Differential voltage input 6.6 8.0 9.3 Q/QB rise time TrQ 230 350 Q/QB fall time TfQ 230 350 SD-TTL/SDB-TTL rise time TrSDT SD-TTL/SDB-TTL fall time TfSDT SD-ECL/SDB-ECL rise time TrSDE SD-ECL/SDB-ECL fall time TfSDE Propagation delay time TPD SD response assert time Tas SD response deassert time SD/SDB hysteresis width Unit 1600 SW: Low, single-ended input VmaxA1 Typ. 6 7 dB 20% to 80% 50Ω to VTT 0.6V to 2.2V CL = 10pF 10 20% to 80% 510Ω to VEE 1.6 mV ps 10 ns 1.6 0.4 1.9 ∗1 0 100 Tdas ∗2 2.3 100 SD response assert time for alarm level default Tasd ∗3 0 100 SD response deassert time for alarm level default Tdasd ∗4 2.3 100 µs ∗1 VUP – VDOWN = 100mV, Vin = 100mVp-p (single ended), SW: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, VEEI: Open. ∗2 VUP – VDOWN = 100mV, Vin = 1Vp-p (single ended), SW: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, connect VEEI: Open. ∗3 Vin = 50mVp-p (single ended), SW: Low, peak hold capacitance of 470pF, connect VEEI to VEE. ∗4 Vin = 1Vp-p (single ended), SW: Low, peak hold capacitance of 470pF, connect VEEI to VEE. –8– CXB1573R DC Electrical Characteristics Measurement Circuit 22 21 20 19 UP DN VEEI VEE2 CAP2 VEE4 VccZ 23 24 C3 CAP3 C3 18 17 VCC2 VCC4 25 16 VEE1 15 ∆V C1 VD D SD-TTL 14 26 peak hold SDB-TTL C1 DB peak hold 27 13 SD-ECL CAP1 28 12 29 11 30 10 270 CAP1B SDB-ECL 270 VccY Q 51 QB 31 51 VCC1 VCC3 32 9 8 TM 7 VEE1 SW VSW VEE2 ODIS VODIS 6 5 4 3 VccX 2 VCC2 1 VEE3 VTT 1.3V 3.3V –9– C2 CXB1573R AC Electrical Characteristics Measurement Circuit 23 22 21 20 19 UP DN VEEI REX1 VEE2 CAP3 VccZ VEE4 24 470p CAP2 470p 18 17 VCC2 VCC4 25 16 VEE1 15 ∆V SD-TTL D 0.047µF DB 0.047µF 14 26 peak hold Oscilloscope Hi-Z input SDB-TTL peak hold 27 13 SD-ECL Z0 = 50 CAP1 28 12 29 11 30 10 CAP1B SDB-ECL Z0 = 50 Oscilloscope 50Ω input Q Z0 = 50 VccY QB 31 Z0 = 50 VCC3 VCC1 32 9 VCC +2V – 10 – VEE1 VEE2 VccX VEE –1.3V 7 8 TM 6 5 4 3 VCC2 SW 2 ODIS VEE3 1 1µF CXB1573R Application Circuit VEE 24 23 22 21 20 19 UP DN REX1 VEEI VEE2 470p CAP2 CAP3 VEE4 VccZ 470p 18 17 VCC4 25 16 ∆V SD-TTL 26 TTL Output 15 VEE1 VTT D 14 0.047µF DB 0.047µF 51Ω Signal Generator 51Ω VIN peak hold SDB-TTL peak hold 27 13 SD-ECL ECL Output VCC2 28 12 29 11 30 10 VccY 51Ω VTT CAP1B SDB-ECL 51Ω 51Ω VTT CAP1 1µF Q ECL Output 51Ω QB 31 VCC3 32 TTL Input 6 7 8 TM 5 VEE1 4 VEE2 3 VccX 2 ODIS VEE3 1 VCC2 9 SW VCC –2V VCC1 VEE Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – CXB1573R Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 13 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1kΩ R2 (internal): 7.5kΩ f2: 3.4kHz f1: 21Hz C1 (external): 0.047µF C2 (external): 1µF 14 D C1 To IC interior 13 C1 R1 R1 R2 12 C2 R2 11 Fig. 1 Gain Feedback frequency response f1 f2 Frequency Fig. 2 – 12 – Amplifier frequency response CXB1573R 2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 17 and 18 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to connect Pin 19 to VEE and leave Pins 17 and 18 open to set an alarm level default value (8mV for input conversion). The other is to connect Pin 19 to VEE and set a desired alarm level using the external resistors REX1, REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 17 and 18 or connect REX3 between Pin 18 and Vcc when less alarm level is desired to be set than its default value; connect REX2 between Pin 17 and Vcc when more alarm level is desired to be set than its default value. However, the Pin 17 voltage must be higher than that of Pin 18. This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to 40mVp-p when Pin 3 is left open (High level) and it is set to 20mVp-p when Pin 3 is Low level. Therefore, the noise margin can be increased by setting Pin 3 to Low level when the small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 5. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. This IC is designed to externally have the capacitor C3, and the C3 value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 6. REX1: 100Ω (when the alarm level is set to 4mV for input conversion.) REX2: 8kΩ (when the alarm level is set to 10mV for input conversion.) REX3: 4kΩ (when the alarm level is set to 4mV for input conversion.) C3: 470pF The table below shows the alarm logic. The table below shows the output disable function logic. SD SD Optical signal input state Q Q Signal input High level Low level ODIS: Open High Fixed Low Fixed High Signal interruption Low level High level ODIS: Low Data Data Optical signal input state Ra1, Ra2A and Ra2B values are typical values. From limiting amplifier Peak Hold SD-TTL SDB-TTL VCCA Ra1 986 Ra2A 141 SD-ECL SDB-ECL Peak Hold Ra2B 141 VCCA VCS VCCA 10p 10p ∆V 3 19 18 17 21 22 IC interior 19 REX2 VEEI 18 DN UP 17 IC exterior VEE Fig. 3 – 13 – REX1 VCC C3 C3 REX3 VCC VCC VCC CXB1573R VDAS → Deassert level VAS → Assert level Peak hold output voltage SD output High level Low level VDAS VAS Small Large 3dB 3dB Alarm setting input level Hysteresis SW → Low SW → Open High 0 Input electrical signal amplitude Fig. 4 20 40 Input voltage [mVp-p] Fig. 5 Data input (D) Hysteresis width Alarm setting level Data output (Q) Alarm output (SD) Assert time Deassert time Fig. 6 – 14 – CXB1573R Example of Representative Characteristics 1. Q/QB output waveform VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 622Mbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 500ps/div Fig. 7 VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 622Mbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 500ps/div Fig. 8 VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 1.25Gbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 200ps/div Fig. 9 – 15 – CXB1573R VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 1.25Gbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 200ps/div Fig. 10 2. Bit error rate Bit error rate vs. Data input level 10 –3 622Mbps 1.0Gbps 1.25Gbps 10 –4 Bit error rate 10 –5 VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT 10 –6 10 –7 10 –8 10 –9 10 –10 1.5 2 2.5 3 3.5 Data input level [mVp-p] Alarm level vs. REX1 Alarm level vs.Temperature 6.0 9 SW = H SW = L 5.0 Alarm level [mV] Alarm level [mV] SW = H SW = L 5.5 7 6 5 4 4.5 4.0 3.5 3.0 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 3 2 102 4.5 Fig. 11 3. Alarm level 8 4 fin = 100Mbps VCC – VEE = 3.3V Up-Down = 200Ω (REX1) 2.5 2.0 103 UP-DOWN (REX1) [Ω] 104 Fig. 12 –40 –20 0 20 40 Ta [°C] Fig. 13 – 16 – 60 80 100 CXB1573R Alarm level vs. Supply voltage Alarm level vs. REX2 6.0 16 SW = H SW = L 5.5 14 Alarm level [mV] 5.0 Alarm level [mV] fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 15 4.5 4.0 3.5 13 12 11 10 3.0 fin = 100Mbps Ta = 27°C Up-Down = 200Ω (REX1) 2.5 2.0 3.0 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 SW = H SW = L 9 8 103 3.6 104 VCC-UP (REX2) [Ω] Fig. 14 Fig. 15 Alarm level vs. Temperature Alarm level vs. Supply voltage 15.0 15.0 SW = H SW = L 14.5 SW = H SW = L 14.5 14.0 Alarm level [mV] 14.0 Alarm level [mV] 105 13.5 13.0 12.5 12.0 13.5 12.0 12.5 12.0 fin = 100Mbps VCC – VEE = 3.3V VCC-UP = 5kΩ (REX2) 11.5 11.0 –40 –20 0 20 40 Ta [°C] 60 80 fin = 100Mbps Ta = 27°C VCC-UP = 5kΩ (REX2) 11.5 11.0 3.0 100 3.1 3.2 3.4 3.3 VCC – VEE [V] Fig. 16 3.5 3.6 Fig. 17 Alarm level vs. REX3 Alarm level vs. Temperature 6.0 9 SW = H SW = L SW = H SW = L 5.5 8 fin = 100Mbps VCC – VEE = 3.3V VCC-Down = 3kΩ (REX3) Alarm level [mV] Alarm level [mV] 5.0 7 6 5 3 103 4.0 3.5 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 4 4.5 3.0 2.5 104 VCC-DOWN (REX3) [Ω] –40 105 Fig. 18 –20 0 20 40 Ta [°C] Fig. 19 – 17 – 60 80 100 CXB1573R Alarm level vs. Supply voltage Hysteresis width vs. Alarm level 6.0 8.0 5.0 6.0 4.5 5.0 4.0 4.0 3.5 3.0 3.0 2.0 2.5 1.0 2.0 3.0 3.3 3.2 3.4 VCC – VEE [V] 3.1 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C 0 2.0 3.6 3.5 SW = H SW = L 7.0 HYS [dB] Alarm level [mV] fin = 100Mbps Ta = 27°C VCC-Down = 3kΩ (REX3) SW = H SW = L 5.5 4.0 6.0 10.0 8.0 Alarm level [mV] Fig. 20 14.0 Fig. 21 Hysteresis width vs. Temperature Hyteresis width vs. Supply voltage 8.0 8.0 SW = H SW = L 7.0 SW = H SW = L 7.0 6.0 6.0 5.0 5.0 HYS [dB] HYS [dB] 12.0 4.0 3.0 4.0 3.0 2.0 2.0 fin = 100Mbps VCC – VEE = 3.3V Up, Down = Open VEEI = VEE 1.0 1.0 0 –40 –20 0 20 40 Ta [°C] 60 fin = 100Mbps Ta = 27°C Up, Down = Open VEEI = VEE 0 3.0 80 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 Fig. 22 Fig. 23 Alarm level vs. Data rate Hysteresis width vs. Data rate 16 3.6 12 SW = H SW = L 14 SW = H SW = L 10 8 HYS [dB] Alarm level [mV] 12 10 8 6 4 6 VCC – VEE = 3.3V Ta = 27°C Up, Down = Open VEEI = VEE 4 VCC – VEE = 3.3V Ta = 27°C Up, Down = Open VEEI = VEE 2 2 0 0 200 400 600 800 fin [Mbps] 1000 1200 1400 0 Fig. 24 200 400 600 800 fin [Mbps] Fig. 25 – 18 – 1000 1200 1400 CXB1573R 4. DC voltage SD-ECL "H" level vs. Supply voltage SD-ECL "H" level vs. Temperature –860 –860 Ta = 27°C SD-ECL SDB-ECL –900 –900 –940 –940 "H" level [mV] "H" level [mV] SD-ECL SDB-ECL –980 –980 –1020 –1020 –1060 –1060 –1100 –1100 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 –40 –20 0 Fig. 26 20 40 Ta [°C] SD-ECL "L" level vs. Supply voltage 80 100 SD-ECL "L" level vs. Temperature –1640 Ta = 27°C SD-ECL SDB-ECL –1680 SD-ECL SDB-ECL –1680 –1720 VCC – VEE = 3.3V "L" level [mV] –1720 –1760 –1760 –1800 –1800 –1840 –1840 –1880 –1880 3.0 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 3.6 –40 –20 0 Fig. 28 20 40 Ta [°C] SD-TTL "H" level vs. Supply voltage 80 100 SD-TTL "H" level vs. Temperature 3.4 Ta = 27°C VCC – VEE = 3.3V 3.2 3.0 3.0 "H" level [V] 3.2 2.8 2.8 2.6 2.6 2.4 2.4 2.2 3.0 60 Fig. 29 3.4 "H" level [V] 60 Fig. 27 –1640 "L" level [mV] VCC – VEE = 3.3V 2.2 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 3.6 –40 Fig. 30 –20 0 20 40 Ta [°C] Fig. 31 – 19 – 60 80 100 CXB1573R SD-TTL "L" level vs. Supply voltage SD-TTL "L" level vs. Temperature 400 400 Ta = 27°C VCC – VEE = 3.3V 350 "L" level [mV] "L" level [mV] 350 300 250 300 250 200 200 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 –40 –20 0 Fig. 32 Q "H" level vs. Supply voltage 80 100 Q "H" level vs. Temperature –860 Ta = 27°C Q-H QB-H Q-H QB-H –900 –900 –940 –940 "H" level [mV] "H" level [mV] 60 Fig. 33 –860 –980 VCC – VEE = 3.3V –980 –1020 –1020 –1060 –1060 –1100 –1100 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 –40 –20 0 Fig. 34 20 40 Ta [°C] 60 80 100 Fig. 35 Q "L" level vs. Supply voltage Q "L" level vs. Temperature –1620 –1620 Ta = 27°C Q-L QB-L Q-L QB-L –1660 –1660 –1700 –1700 "L" level [mV] "L" level [mV] 20 40 Ta [°C] –1740 –1740 –1780 –1780 –1820 –1820 –1860 VCC – VEE = 3.3V –1860 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 –40 Fig. 36 –20 0 20 40 Ta [°C] Fig. 37 – 20 – 60 80 100 CXB1573R Package Outline Unit: mm 32PIN LQFP (PLASTIC) 7.0 1.7MAX 5.0 S B 0.08 S 17 24 B A 25 16 A 9 32 (0.5) 8 1 X4 X4 0.2 S 0.2 AB S AB S AB 0.5 0.08 M 0.2 ± 0.03 (0.2) (0.125) 0.1 ± 0.05 0.125 ± 0.02 0.6 ± 0.15 0.25 (0.5) 0° to 8° DETAIL B DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-32P-L01 LEAD TREATMENT PALLADIUM PLATING EIAJ CODE LQFP032-P-0505 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 21 –