CXB1562AQ 2R IC for Optical Fiber Communication Receiver Description The CXB1562AQ achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. 32 pin QFP (Plastic) Features • Auto-offset canceler circuit • Signal interruption alarm output • 2-level switching function of identification maximum voltage amplitude for alarm block • Single 5V power supply Applications • FDDI • SONET/SDH • ESCON • Fiber channel : 125Mb/s : 155.52Mb/s : 200Mb/s : 265.625Mb/s Absolute Maximum Ratings • Supply voltage • Storage temperature • Input voltage difference : I VD – VD I • SW input voltage • Output current (Continuous) (Surge current) VCC – VEE Tstg Vdif Vi IO Recommended Operating Conditions • Supply voltage VCC – VEE • Termination voltage (for data/alarm) VCC – VT1 • Termination voltage (for alarm 2) VT2 • Termination resistance (for data/alarm) RT1 • Termination resistance (for alarm 2) RT2 • Operating temperature Ta –0.3 to +7.0 –65 to +150 0.0 to +2.5 VEE to VCC 0 to 50 0 to 100 V °C V V mA mA 5.0±0.5 1.8 to 2.2 VEE 45 to 55 460 to 560 –40 to +85 V V V Ω Ω °C Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94930B6Z CXB1562AQ VccD VccDA SD SD VccDA Q Q N.C. Block Diagram and Pin Configuration 24 23 22 21 20 19 18 17 N.C. 25 16 TM 15 VccD 14 VEED 13 VccA 12 VEEA N.C. 26 N.C. 27 Limiting Amplifier Block R2 ∆V DOWN 30 R2 CAP2 29 peak hold peak hold CAP3 28 Alarm Block 11 CAP1 UP 31 R4 R1 VccA 32 DR R3 R1 4 –2– VccP VccR VEEI SW 5 6 7 8 CAP1 3 VCCA 2 D 1 D RR RP 10 R2K 9 R1K CXB1562AQ Pin Description Typical pin Pin No. Symbol voltage (V) DC AC 1 Equivalent circuit VCCP Description 50k Positive power supply for external power supply. 2 VCCR 10 32 1 2 VccA 993 110.3 110.3 31 3 VEEI –5V 30 SW Vcs VEEA Generates the default voltage between UP and DOWN. The voltage (8.0mV for input conversion) can be generated between UP and DOWN (Pins 30 and 31) as alarm setting level by connecting this pin to VEEA. 3 VCCA Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 50mVp-p. Low voltage when connecting this pin to VEE; the amplitude becomes 20mVp-p. 150k 100k 0V 4 SW 4 (OPEN) VREF or –5V VEEA 5 6 D –1.3V –0.9V to –1.7V D –1.3V –0.9V to –1.7V Limiting amplifier block input. Be sure to make this input with AC coupled. VCCA 200 7 VCCA 0V 5 11 6 200 10k 100p 200 2k 10 8 CAP1 –1.8V 1.5k 9 R1K 1.5k 10 R2K 11 CAP1 –1.8V 10k 200 1k 9 8 VEEA –3– Positive power supply for analog block. Pins 8 and 11 connect a capacitor which determines the cut-off frequency for feedback block, and 1kΩ is connected between Pins 8 and 9; 2kΩ between Pins 10 and 11. A resistor which is to be inserted in parallel with a capacitor can be selected 5 ways by external wiring, and DC feedback can be varied. CXB1562AQ Typical pin Pin No. Symbol voltage (V) DC AC Equivalent circuit Description 12 VEEA –5V Negative power supply for analog block. 13 VCCA 0V Positive power supply for analog block. 14 VEED –5V Negative power supply for digital block. 15 VCCD 0V Positive power supply for digital block. 16 TM 17 N.C 18 14 –3.0V 16 Chip temperature monitor. No connected. VCCDA –0.9V to –1.7V Q 19 19 20 21 –0.9V to –1.7V Q VCCDA 18 VEED Positive power supply for output buffer. 0V VCCDA –0.9V to –1.7V SD 21 22 –0.9V to –1.7V SD Data signal output. Terminate this pin in 50Ω at VTT = –2V. Alarm signal output. Terminate this pin in 50Ω at VTT = –2V. 22 VEED 23 VccDA 0V Positive power supply for digital block. 24 VccD 0V Positive power supply for digital block. 25 N.C 26 N.C 27 N.C No connected. –4– CXB1562AQ Typical pin Pin No. Symbol voltage (V) DC AC Equivalent circuit Description 28 29 VCCA 80 29 CAP2 –1.8V 5µA 80 10p CAP3 –1.8V 10p 28 5µA VEEA Connects a peak hold circuit capacitor for alarm block. 470pF should be connected to VccA each. CAP2 pin → Peak hold capacitor connection for alarm level setting block. CAP3 pin → Peak hold capacitor connection for limiting amplifier signal. VccA 30 –0.84V (for DOWN VEEI = –5V) 993 110.3 110.3 31 30 31 32 UP VccA –0.8V (for VEEI = –5V) Vcs SW Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor by shorting the VEEI pin to VEEA. VEEA 3 Positive power supply for analog block. 0V –5– CXB1562AQ Electrical Characteristics • DC characteristics (VCC = GND, VEE = –5V±10%, Ta = –40 to +85°C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Symbol Power supply IEE Q/Q SD/SD High output voltage VOH Q/Q SD/SD Low output voltage VOL SD/SD High output voltage 2 VOHb SD/SD Low output voltage 2 VOLb SW High input voltage Conditions RT1 = 50Ω, VT1 = –2V termination Min. Typ. Max. Unit –50 –37 –28 mA RT1 = 50Ω, VT1 = –2V termination Ta = 0 to 85°C –1025 –880 –1810 –1620 RT2 = 510Ω, VEE termination Ta = 0 to 85°C –1075 –830 –1860 –1570 VIH –1900 0 SW Low input voltage VIL VEE –2500 SW High input current IIH SW Low input current IIL –60 D/D input resistance Rin 1125 1500 1875 Internal resistance 1 for alarm level setting Ra1 Refer to Fig. 3. 745 993 1241 Internal resistance 2 for alarm level setting Ra2A, B Refer to Fig. 3. 82.7 110.3 137.9 Resistance between VccA and VccP RP Resistance between VccA and VccR RR Pare ratio of internal resistance 2 for alarm level setting δRa2 Resistance between CAP1 and R1K R3 745 993 1241 Resistance between CAP1 and R2K R4 1489 1986 2482 2 mV µA Ω 10 37.5 Ra2A/Ra2B –6– 50 0.97 62.5 kΩ 1.03 Ω CXB1562AQ • AC characteristics (VCC = GND, VEE = –5V±10%, Ta = –40 to +85°C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Symbol Conditions Typ. Max. mVpp IC internal amplitude of 400mV 60 dB VminA1 SW pad: Low, single-ended input 20 VminA2 SW pad: Open High, single-ended input 50 Vmax Single-ended input Amplifier gain (except for output buffer) GL Hysteresis width ∆P SD response assert time Tas SD response deassert time mVpp 4 6 7 0 100 Tdas Low → High∗1 High → Low∗2 2.3 100 SD response assert time for alarm level default Tasd Low → High∗3 0 100 SD response deassert time for alarm level default Tdasd High → Low∗4 2.3 100 Alarm setting level for default Vdef UP/DOWN pins; Open, connect VEEI to VEE. 6.6 8.0 9.3 Propagation delay time TPD D to Q 0.95 1.65 2.75 Q/Q SD/SD rise time Tr 0.45 1.6 Q/Q SD/SD fall time Tf RT1 = 50Ω, VT1 = –2 V termination VEE = –5V, 20% to 80% 0.45 1.6 ∗1 ∗2 ∗3 ∗4 Unit 1600 Maximum input voltage amplitude Identification maximum voltage amplitude of alarm level Min. VUP – VDOWN = 100mV, Vin = 100mVpp (single ended), SW pin: High Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE. VUP – VDOWN = 100mV, Vin = 1Vpp (single ended), SW pin: High Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE. Vin = 50mVpp (single ended), SW pin: Low Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE. Vin = 1Vpp (single ended), SW pin: Low Peak hold capacitance (CAP2, CAP3 pins) of 470pF; connect VEEI to VEE. –7– dB µs mV ns CXB1562AQ DC Electrical Characteristics Measurement Circuit V 23 24 VT1 –2V 51 51 V 21 22 51 51 V 19 20 V 17 18 25 16 26 15 27 Alarm Block C3 14 Limiting Amplifier Block peak hold C3 R2 ∆V 30 12 R2 29 13 peak hold 28 11 V 31 R1 R4 32 V R3 RR RP 1 V R1 C2 V 9 DR V V 10 2 5 4 3 6 7 8 V V A C1 VS V C1 A VD VEE –8– –5V CXB1562AQ AC Electrical Characteristics Measurement Circuit Oscilloscope 50Ω input Z0 = 50 Z0 = 50 Z0 = 50 Z0 = 50 23 24 21 22 20 19 17 18 25 16 26 15 27 Alarm Block 14 28 Limiting Amplifier Block REX1 ∆V 30 V 12 R2 29 13 peak hold peak hold 470pF R2 470pF 11 31 R4 R1 10 32 REX2 0.22µF 9 DR R3 R1 RR RP 1 2 3 5 4 0.022µF 6 7 8 0.022µF VEE –3V –9– VCC +2V CXB1562AQ Application Circuit VT1 51 23 24 –2V 51 51 21 22 20 51 19 17 18 25 16 26 15 27 Alarm Block 14 28 Limiting Amplifier Block 470pF 29 ∆V 30 12 R2 470pF 13 peak hold peak hold C3 R2 C3 11 31 R1 R4 10 32 9 DR R1 C2 0.22µF R3 RR RP 1 2 3 5 4 C1 0.022µF 6 7 C1 0.022µF 8 VEE –5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXB1562AQ Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 6 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1.5kΩ R2 (internal): 10kΩ f2: 4.8kHz f1: 72Hz C1 (external): 0.022µF C2 (external): 0.22µF 1kΩ is incorporated between Pins 8 and 9; 2kΩ between Pins 10 and 11. A resistance value which is to be inserted in parallel with a capacitor f2 can be selected 5 ways (∞, 3kΩ, 2kΩ, 1kΩ, 1k//2kΩ) by external wiring, and DC feedback can be varied. D 5 C1 To IC interior 6 C1 R1 R1 8 R3 R2 R4 R2 9 C2 10 11 Fig. 1 Gain Feedback frequency response f1 f2 Frequency Fig. 2 – 11 – Amplifier frequency response CXB1562AQ 2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 30 and 31 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to connect VEE to Pin 3 and leave Pins 30 and 31 open to set an alarm level default value (8mV for input conversion). The other is to connect Pin 3 to VEE and set a desired alarm level using the external resistors REX1 and REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 30 and 31, or between Pin 30 and VCC when less alarm level is desired to be set than its default value; connect REX2 between Pin 31 and Vcc potential when more alarm level is desired to be set than its default value. However, the Pin 31 voltage must be higher than that of Pin 30. Refer to Figs. 5, 8 to 11 for this alarm level setting. This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to 50mVp-p when Pin 4 is left open (High level) and it is set to 20mVp-p when Pin 4 is Low level. Therefore, noise margin can be increased by setting Pin 4 to Low level when small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 6. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. The C3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 7. The typical values of REX1, REX2, REX3 and C3 are as follows: (Approximately 10pF capacitor is built in Pins 28 and 29 each.) REX1 : 217Ω (when the alarm level is set to 4mV for input conversion.) REX2 : 634Ω (when the alarm level is set to 19mV for input conversion.) REX3 : 4kΩ (when the alarm level is set to 4mV for input conversion.) C3 : 470pF The table below shows the alarm logic. Optical signal input state SD SD Signal input High level Low level Signal interruption Low level High level Ra1, Ra2A and Ra2B values are typical values. From Limiting Amplifier Peak hold VCCA Ra1 Ra2A 110.3 SD SD 993 Ra2B 110.3 Peak hold Vcs VccA ∆V 4 3 31 VccA 10p 30 10p IC interior 31 30 28 29 C3 3 REX2 IC exterior Vcc Fig. 3 – 12 – REX1 C3 REX3 Vcc Vcc Vcc CXB1562AQ VDAS → Deassert level VAS → Assert level High level VAS, VDAS [mV] Low level VAS VDAS Small Large 3dB 3dB Alarm setting input level VAS SW = High SW = Low 20 15 VDAS 10 5 0 0 Hysteresis 20 40 60 80 Voltage between Pins 30 and 31 [mV] Input electrical signal amplitude Fig. 4 Peak hold output voltage SD output AAA AAA 25 Fig. 5 SW → Low SW → Open High 0 20mVpp 50mVpp Input voltage [Vp-p] Fig. 6 Data input (D) Hysteresis width Alarm setting level Data output (Q) Alarm output (SD) Assert time Deassert time Fig. 7 – 13 – 100 CXB1562AQ REX1-VUD temperature characteristics data 40 2600 35 2400 30 Vup-Vdown [mV] TM-VEE [mV] TM pin temperature characteristics 2800 2200 2000 1800 25 20 15 Iin = 100µA Iin = 1mA Iin = 5mA 1600 1400 –50 –25 0 –40°C 27°C 85°C 125°C 10 25 50 75 100 5 125 0 400 800 Tj [°C] Fig. 8 2000 REX3-VUD temperature characteristics data REX2-VUD temperature characteristics data 40 –40°C 27°C 85°C 125°C 120 35 30 Vup-Vdown [mV] 110 Vup-Vdown [mV] 1600 Fig. 9 130 100 90 80 70 25 20 15 –40°C 27°C 85°C 125°C 10 60 5 50 40 1200 REX1 [Ω] 0 1000 2000 3000 4000 5000 6000 7000 0 0 5 10 15 REX3 [kΩ] REX2 [Ω] Fig. 10 Fig. 11 3. Others Pay attention to handling this IC because its electrostatic discharge strength is weak. – 14 – 20 25 30 CXB1562AQ Example of Representative Characteristics AAAAAAAAA A A A A A A AAAAAAAAA A A A A A A AAAAAAAAA A A A A A A AAAAAAAAA AA AAAA AAAAAAAAA A A A A A A AAAAAAAAA AA AAAA Bit Error Rate vs. Data Input Level 140 Output RMS Jitter [pS] Bit Error Rate 10–7 10–8 10–9 VEE = –5.0V Ta = 27°C D = 155.52Mbps 10–10 10–11 10–12 1. 2 1. 1.4 1. 1. 3 5 6 Data Input Level [mVpp] VEE = –5.0V Ta = 27°C D = 155.52Mbps 120 100 pattern: PRBS223–1 80 60 40 20 pattern: PRBS223–1 1. 1 AAAAAAAA AAAAAAAAA A A A A A A A A A A A A A A A A AAAAAAAAA A A A A A A A A AAAAAAAAA AAAAAAAA AAAAAAAAA A A A A A A A A AAAAAAAAA AAAAAAAAA A AAAAAAA Output RMS Jitter vs. Data Input Level 10–6 0 1.7 1 10 100 1000 Data Input Level [mVpp] Fig. 12 Fig. 13 Q Output Waveform -520mV VEE = –5.0V Ta = 27°C D = 155.52Mbps, 2mVp-p pattern: PRBS223–1 -1320mV X Axis : 200 mV / div Y Axis : 2 ns / div 16ns -2120mV 36ns 26ns Fig. 14 – 15 – CXB1562AQ Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 ± 0.12 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP032-P-0707-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE – 16 – 0.50 8 + 0.15 0.3 – 0.1