CXD2507AQ CD Digital Signal Processor For the availability of this product, please contact the sales office. Description The CXD2507AQ is a digital signal processor for CD players and is equipped with the following functions. 64 pin QFP (Plastic) -L01 -L121 Features • Digital PLL • EFM frame sync protection • SEC strategy-based error correction • Subcode demodulation, CRC checking • Digital spindle servo • Servo auto-sequencer • Asymmetry compensation circuit • Digital audio interface output • 16K RAM • Double-speed playback capability • New microcomputer interface circuit Absolute Maximum Ratings • Supply voltage VDD –0.3 to +7.0 • Supply voltage variation VSS – AVSS –0.3 to +0.3 VDD – AVDD –0.3 to +0.3 • Input voltage VI –0.3 to +7.0 VIN VSS – 0.3 to VDD + 0.3 • Output voltage VO –0.3 to +7.0 • Storage temperature Tstg –40 to +125 Recommended Operating Conditions • Supply voltage VDD • Operating temperature Topr V V V V V V °C 4.5 to 5.5V (double-speed playback) 3.5 to 5.5V (normal-speed playback) 3.0 to 5.5V (low power consumption, special playback mode) ∗ –20 (min.) 75 (max.) °C ∗ When the internal operation of the LSI is set to double-speed mode and the crystal oscillation frequency is halved, normal-speed playback results. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94601A11 CXD2507AQ DATA XRST SENS MUTE SQCK SQSO EXCK SBSO SCOR Vss WFCK EMPH DOUT C4M FSTT XTSL XTAO XTAI MNT0 Pin Configuration 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 XLAT 52 32 MNT1 CLOK 53 31 MNT3 SEIN 54 30 XROF CNIN 55 29 C2PO DATO 56 28 RFCK XLTO 57 27 GFS 26 VDD VDD 58 8 9 10 11 12 13 14 15 16 17 18 19 WDCK 7 ASYE 6 ASYO 5 ASYI 4 BIAS 3 RF 2 AVDD 1 CLTV 20 LRCK AVss XLON 64 Vss 21 PCMD PCO SPOD 63 FILI 22 BCK FILO SPOC 62 TEST 23 GTOP LOCK SPOB 61 MDS 24 XUGF MDP SPOA 60 MON 25 XPCK FOK CLKO 59 –2– CXD2507AQ BCK DOUT PCMD WDCK 28 29 48 19 20 21 22 39 LRCK MUTE C2PO RFCK Block Diagram Digital OUT D/A Interface Digital CLV 30 XROF 5 LOCK 4 MDS 3 MDP 2 MON 47 SQCK 46 SQSO MNT0 33 Error corrector MNT1 32 16K RAM MNT3 31 CPU Interface WFCK 41 EMPH 40 EFM Demodulator GFS 27 SUB code processor XUGF 24 GTOP 23 Digital PLL XTSL 36 XTAO 35 Clock generator Servo auto sequencer Asymmetry corrector 54 55 SEIN CNIN PCO –3– 1 FOK 9 12 CLTV 8 FILI FILO 25 7 XPCK BIAS ASYE ASYO C4M 16 17 18 15 ASYI FSTT 14 RF 38 EXCK SBSO 43 SCOR 64 XLON 60 SPOA to D 53 CLOK 52 XLAT 51 DATA 49 SENS 59 CLKO 57 XLTO 56 DATO XTAI 34 37 45 44 CXD2507AQ Pin Description Pin No. Symbol Description I/O Focus OK input. Used for SENS output and the servo auto sequencer. 1 FOK I 2 MON O 1, 0 3 MDP O 1, Z, 0 Spindle motor servo control. 4 MDS O 1, Z, 0 Spindle motor servo control. 5 LOCK O 1, 0 6 TEST I 7 FILO O 8 FILI I 9 PCO O 1, Z, 0 10 VSS — — GND. 11 AVSS — — Analog GND. 12 CLTV I 13 AVDD — 14 RF I EFM signal input. 15 BIAS I Constant current input of asymmetry circuit. 16 ASYI I Asymmetry comparator voltage input. 17 ASYO O 18 ASYE I 19 WDCK O 1, 0 D/A interface. Word clock f = 2Fs. 20 LRCK O 1, 0 D/A interface. LR clock f = Fs. 21 PCMD O 1, 0 D/A interface. Serial data (two's complement, MSB first). 22 BCK O 1, 0 D/A interface. Bit clock. 23 GTOP O 1, 0 GTOP output. 24 XUGF O 1, 0 XUGF output. 25 XPCK O 1, 0 XPLCK output. 26 VDD — — 27 GFS O 1, 0 GFS output. 28 RFCK O 1, 0 RFCK output. 29 C2PO O 1, 0 C2PO output. 30 XROF O 1, 0 XRAOF output. 31 MNT3 O 1, 0 MNT3 output. 32 MNT1 O 1, 0 MNT1 output. 33 MNT0 O 1, 0 MNT0 output. 34 XTAI I 35 XTAO O 36 XTSL I Spindle motor on/off control output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. TEST pin. Normally GND. Analog Master PLL (slave = digital PLL) filter output. Master PLL filter input. Master PLL charge pump output. Master VCO control voltage input. — 1, 0 Analog power supply (+5V). EFM full-swing output (low = Vss, high = VDD). Low: asymmetry circuit off; high: asymmetry circuit on. Power supply (+5V). 16.9344MHz crystal oscillation circuit input, or 33.8688MHz input. 1, 0 16.9344MHz crystal oscillation circuit output. Crystal selection input. Set low when the crystal is 16.9344MHz, high when 33.8688MHz. –4– CXD2507AQ Pin No. Symbol 37 FSTT O 1, 0 2/3 frequency divider output for Pins 34 and 35. 38 C4M O 1, 0 4.2336MHz output. 39 DOUT O 1, 0 Digital Out output. 40 EMPH O 1, 0 Outputs high signal when the playback disc has emphasis, low signal when no emphasis. 41 WFCK O 1, 0 WFCK output. 42 VSS — — 43 SCOR O 1, 0 Outputs high signal when either subcode sync S0 or S1 is detected. 44 SBSO O 1, 0 Sub P to W serial output. 45 EXCK I 46 SQSO O 47 SQCK I SQSO readout clock input. 48 MUTE I High: mute; low: release 49 SENS O 50 XRST I System reset. Reset when low. 51 DATA I Serial data input from CPU. 52 XLAT I Latch input from CPU. Serial data is latched at the falling edge. 53 CLOK I Serial data transfer clock input from CPU. 54 SEIN I Sense input from SSP. 55 CNIN I Track jump count signal input. 56 DATO O 1, 0 Serial data output to SSP. 57 XLTO O 1, 0 Serial data latch output to SSP. Latched at the falling edge. 58 VDD — — 59 CLKO O 1, 0 60 SPOA I Microcomputer extended interface (input A). 61 SPOB I Microcomputer extended interface (input B). 62 SPOC I Microcomputer extended interface (input C). 63 SPOD I Microcomputer extended interface (input D). 64 XLON O Notes) Description I/O GND. SBSO readout clock input. 1, 0 1, 0 1, 0 SubQ 80-bit serial output. SENS output to CPU. Power supply (+5V). Serial data transfer clock output to SSP. Microcomputer extended interface (output). • PCMD is two's complement output of MSB first. • GTOP is used to monitor the frame sync protection status. • XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync protection. • XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. • GFS goes high when the frame sync and the insertion protection timing match. • RFCK is derived from the crystal accuracy. This signal has a cycle of 136µ. • C2PO represents the data error status. • XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin. –5– CXD2507AQ Electrical Characteristics DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Output voltage (3) Output voltage (2) Output voltage (1) Input voltage (3) Input voltage (2) Input voltage (1) Item High level input voltage Conditions VIL (1) High level input voltage VIH (2) Typ. Max. 0.7VDD VIH (1) Low level input voltage Min. Unit V 0.3VDD 0.8VDD VIL (2) Input voltage VIN (3) Analog input High level output voltage VOH (1) IOH = –4mA Low level output voltage VOL (1) IOL = 4mA High level output voltage VOH (2) IOH = –2mA Low level output voltage VOL (2) IOL = 4mA High level output voltage VOH (4) IOH = –0.28mA Low level output voltage VOL (4) IOL = 0.36mA V 0.2VDD V VSS VDD V VDD – 0.8 VDD V 0 0.4 V VDD – 0.8 VDD V 0 0.4 V VDD – 0.5 VDD V 0 ∗1 V Schmitt input Low level input voltage Applicable pins 0.4 V ∗2 ∗3 ∗4 ∗5 ∗6 Input leak current ILI VI = 0 to 5.25V ±5 µA ∗1, ∗2, ∗3 Tri-state pin output leak current ILO VO = 0 to 5.25V ±5 µA ∗7 Applicable pins ∗1 XTSL, DATA, XLAT ∗2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, ASYE ∗3 CLTV, FILI, RF ∗4 MDP, PCO ∗5 ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, LRCK, WFCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, XROF, MNT0, MNT1, MNT3 ∗6 FILO ∗7 MDS, MDP, PCO –6– CXD2507AQ AC Characteristics 1) XTAI and VCOI pins (1) When using self-oscillation (Topr = –20 to +75°C, VDD =AVDD = 5.0V ± 5%) Item Symbol Oscillation frequency Min. fMAX Typ. Max. Unit 34 MHz 7 (2) When inputting pulses to XTAI and VCOI (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCX 26 1,000 ns Input high level VIHX VDD – 1.0 Input low level VILX 0.8 V Rise time, fall time tR, tF 10 ns V tCX tWLX tWHX VIHX VIHX × 0.9 VDD/2 XTAI VIHX × 0.1 VILX tR tF (3) When inputting sine waves to XTAI and VCOI pins via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Symbol Min. Input amplitude V1 2.0 Typ. Max. Unit VDD + 0.3 Vp-p –7– CXD2507AQ 2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Symbol Clock frequency fCK Clock pulse width Latch pulse width tWCK tSU tH tD tWL EXCK SQCK frequency fT EXCK SQCK pulse width tWT Setup time Hold time Delay time Min. Typ. Max. Unit 0.65 MHz 750 ns 300 ns 300 ns 300 ns 750 ns 0.65∗ 750∗ MHz ns 1/fCX tWCK tWCK CLK DATA XLT tSU tH EXCK CNIN SQCK tWL tD tWT tWT 1/fr SBSO SQSO tSU tH ∗ In low power consumption and special playback mode, when SL0 = SL1 = 1, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs. Description of Functions 1. CPU Interface and Instructions • CPU interface This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D1 D2 Data D3 D0 D1 D2 D3 750ns or more Address XLAT Valid Registers 4 to E 300ns max • Information on each address and the data is provided in Table 1-1. • The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2. Note) When XLAT is low, EXCK and SQCK must be set high. –8– –9– CLV CTRL CLV mode TEST mode D E F 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 D1 1 0 1 0 1 0 1 0 1 0 1 0 D0 D2 D1 Data 1 D0 — — — D3 — — — D2 — — — D1 Data 2 SL0 0 CPUSR 0 Mute ATT DOUT DOUT WSEL MUTE ON/OFF DSPB 0 ON/OFF 0 Table 1-1 Don't Use CM3 CM2 CM1 CM0 Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 DCLV TP CLVS Gain PWMmod TB SL1 0 0 CDROM — — — — — — 0 — — — — — — — 0 — — — — — — — 0 — 3276816384 8192 4096 2048 1024 512 11.6ms 5.8ms 2.9ms 1.45ms 0.36ms 0.18ms 0.09ms 0.05ms 0.18ms 0.09ms 0.05ms 0.02ms AS3 AS2 AS1 AS0 D3 Values shown as "0" in the above table must be sent as "0". Servo coefficient setting C 0 0 1 Audio CTRL A 1 0 1 Function specification 9 Serial bus CTRL 0 1 MODE specification 8 B 1 0 Auto sequence (N) track jump count setting 7 1 1 0 0 KICK (D) Brake (B) Blind (A, E), Overflow (C) 1 D2 Address 6 5 0 4 Auto sequence D3 Command Register name CD2507 Command Table — — — — — — 0 — 256 — — — D0 — — — — — — — — — — — — — — — 64 — — — D2 — 128 — — — D3 — — — — — — — — 32 — — — D1 Data 3 — — — — — — — — 16 — — — D0 — — — — — — — — 8 — — — D3 — — — — — — — — 4 — — — D2 — — — — — — — — 2 — — — D1 Data 4 — — — — — — — — 1 — — — D0 CXD2507AQ Servo coefficient setting CLV CTRL CLV mode TEST mode C D – 10 – E F 1 1 1 1 1 1 1 1 0 0 1 Audio CTRL A 1 0 1 Function specification 9 Serial bus CTRL 0 1 MODE specification 8 B 1 0 Auto sequencer (N) track jump count setting 7 1 0 1 0 KICK (D) Brake (B) Blind (A, E), Overflow (C) 1 D2 1 1 0 0 1 1 0 0 1 1 0 0 D1 Address 6 5 0 4 Auto sequence D3 Command Register name CXD2507 Reset Initialization 1 0 1 0 1 0 1 0 1 0 1 0 D0 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 1 1 1 0 1 0 1 0 0 D1 0 0 0 0 1 0 0 0 1 1 0 D0 — — — — — — 0 — 0 — — — D3 Table 1-2 Don't Use 0 0 1 0 0 0 0 0 1 1 0 D2 Data 1 — — — — — — 0 — 0 — — — D2 — — — — — — 0 — 0 — — — D1 Data 2 — — — — — — 0 — 1 — — — D0 — — — — — — — — — — — — — — — — 0 — — 0 — — — — D2 D3 — — — — — — — — 0 — — — D1 Data 3 — — — — — — — — 0 — — — D0 — — — — — — — — 0 — — — D3 — — — — — — — — 0 — — — D2 — — — — — — — — 0 — — — D1 Data 4 — — — — — — — — 0 — — — D0 CXD2507AQ CXD2507AQ 1-1. The meaning of the data for each address is explained below. $4X commands Command AS3 AS2 AS1 AS0 CANCEL 0 0 0 0 FOCUS-ON 0 1 1 1 1 TRACK JUMP 1 0 0 RXF 10 TRACK JUMP 1 0 1 RXF 2N TRACK JUMP 1 1 0 RXF N TRACK MOVE 1 1 1 RXF RXF = 0 RXF = 1 FORWARD REVERSE • When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted. • When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Setting timers: A, E, C, B Command D3 D2 D1 D0 Blind (A, E), Over flow (C) 0.18ms 0.09ms 0.05ms 0.02ms Brake (B) 0.36ms 0.18ms 0.09ms 0.05ms Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Setting timer: D Command KICK (D) D3 D2 D1 D0 11.6ms 5.8ms 2.9ms 1.45ms Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial reset) D = 10.15ms $7X commands Auto sequence TRACK JUMP/MOVE count setting (N) Command Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Auto sequence track jump 15 14 13 12 11 10 2 2 2 2 2 2 count setting 29 28 27 26 25 24 23 22 21 20 This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto sequence. • The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. • The number of track jump is counted according to the signals input from CNIN pin. – 11 – CXD2507AQ $8X commands Command D3 D2 D1 D0 MODE specification CDROM DOUT MUTE DOUT ON-OFF WSEL Command bit C2PO timing CDROM = 1 1-3 CDROM mode; average value interpolation and pre-value hold are not performed. CDROM = 0 1-3 Audio mode; average value interpolation and pre-value hold are performed. Processing Command bit Processing DOUT MUTE = 1 Digital out output is muted. (DA output is not muted.) DOUT MUTE = 0 When no other mute conditions are set, digital out is not muted. Command bit Processing DOUT ON-OFF = 1 Digital out is output from the DOUT pin. DOUT ON-OFF = 0 Digital out is not output from the DOUT pin. Command bit Sync protection window width Application WSEL = 1 ±26 channel clock∗ Anti-rolling is enhanced. WSEL = 0 ±6 channel clock Sync window protection is enhanced. ∗ In normal-speed playback, channel clock = 4.3218MHz. $9X commands Command Function specifications Data 1 Data 2 D3 D2 D1 D0 D3 D2 D1 D0 0 DSPB ON-OFF 0 0 0 0 0 0 Command bit Processing DSPB = 0 Normal-speed playback DSPB = 1 Double-speed playback $AX commands Command Audio CTRL Data 1 D3 D2 D1 D0 0 0 Mute ATT Command bit Command bit Meaning Mute = 0 Mute off if other mute conditions are not set. Mute = 1 Mute on. – 12 – Meaning ATT = 0 Attenuation off. ATT = 1 –12dB CXD2507AQ $BX commands Command Serial bus CTRL D3 D2 D1 D0 SL1 SL0 CPUSR 0 This command switches the method of interfacing with the CPU. With the CDL500 Series, the number of signal lines between the CPU and the DSP can be reduced in comparison with the CDL40 Series. Also, the error rate can be measured with the CPU. Command bits Processing SL1 SL0 0 0 Same interface mode as the CDL40 Series. 0 1 SBSO is output from SQSO pin. In other words, subcodes P to W are read out from SQSO. Input the read clock to SQCK. 1 0 SENS is output from SQSO pin. 1 1 Each output signal is output from SQSO pin. Input the read clock to SQCK. (See to Timing Chart 1-4.) Command bits Processing CPUSR = 1 XLON pin is high. CPUSR = 0 XLON pin is low. $CX commands Command D3 D2 D1 D0 Servo coefficient setting Gain MDP1 Gain MDP0 Gain MDS1 Gain MDS0 Gain CLVS CLV CTRL ($DX) • CLVS mode gain setting: GCLVS Gain MDS1 Gain MDS0 Gain CLVS GCLVS 0 0 0 –12dB 0 0 1 –6dB 0 1 0 –6dB 0 1 1 0dB 1 0 0 0dB 1 0 1 +6dB • CLVP mode gain setting: GMDP, GMDS Gain MDP1 Gain MDP0 GMDP Gain MDS1 Gain MDS0 GMDS 0 0 –6dB 0 0 –6dB 0 1 0dB 0 1 0dB 1 0 +6dB 1 0 +6dB – 13 – CXD2507AQ $DX commands Command D3 D2 D1 D0 CLV CTRL DCLV PWM MD TB TP CLVS Gain See the $CX command. Explanation (See Timing Chart 1-5.) Command bit DCLV PWM MD = 1 CLV PWM mode specified. Both MDS and MDP are used. DCLV PWM MD = 0 CLV PWM mode specified. Ternary MDP values are output. Explanation Command bit TB = 0 Bottom hold in CLVS mode at cycle of RFCK/32 TB = 1 Bottom hold in CLVS mode at cycle of RFCK/16 TP = 0 Peak hold in CLVS mode at cycle of RFCK/4 TP = 1 Peak hold in CLVS mode at cycle of RFCK/2 $EX commands Command D3 D2 D1 D0 CLV mode CM3 CM2 CM1 CM0 CM3 CM2 CM1 CM0 Mode Explanation 0 0 0 0 STOP See Timing Chart 1-6. 1 0 0 0 KICK See Timing Chart 1-9. 1 0 1 0 BRAKE See Timing Chart 1-8. 1 1 1 0 CLVS 1 1 1 1 CLVP 0 1 1 0 CLVA STOP KICK BRAKE CLVS CLVP CLVA : Spindle motor stop mode : Spindle motor forward rotation mode : Spindle motor reverse rotation mode : Rough servo mode. When RF-PLL circuit lock is disengaged, this mode is used to pull the disc rotations within the RF-PLL capture range. : PLL servo mode. : Automatic CLVS/CLVP switching mode. This mode is normally used during playback. – 14 – – 15 – C2P0 CDROM = 1 C2P0 CDROM = 0 WDCK LRCK Timing Chart 1-3 C2 Pointer for lower 8bits Rch C2 Pointer C2 Pointer for upper 8bits Rch 16bit C1 Pointer C2 Pointer for lower 8bits Lch C2 Pointer C2 Pointer for upper 8bits Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG CXD2507AQ SQSO SQCK XLAT Timing Chart 1-4 SPOA SPOB SPOD SCOR GFS GTOP – 16 – LOCK RFCK 0 1 1 No Error Single error correction Irretrievable error 0 0 1 1 1 1 0 0 C2F1 C2F2 FOK 0 EMPH C1F1 C1F2 C2F1 Irretrievable error Single error correction No Error C2 correction status XRAOF 750ns or more (1500ns or more in low power consumption mode) C1 correction status WFCK C1F1 C1F2 SPOC Internal signal latch Set SQCK and EXCK high during this interval. $BC latch C2F2 CXD2507AQ CXD2507AQ Timing Chart 1-5 DCLV PWM MD = 0 Z MDS n • 236(ns) n = 0 to 31 Acceleration MDP Z 132kHz 7.6µs Deceleration DCLV PWM MD = 1 MDS Deceleration Acceleration MDP n • 236(ns) n = 0 to 31 7.6µs Timing Chart 1-6 DCLV PWM MD=0 STOP MDS Z MDP Z MON L DCLV PWM MD=1 STOP MDS MDP L MON L – 17 – CXD2507AQ Timing Chart 1-7 DCLV PWM MD=1 STOP MDS MDP L MON L DCLV PWM MD = 0 KICK Z MDS H MDP Z 7.6µs H MON DCLV PWM MD = 1 KICK MDS MDP H H L MON H – 18 – CXD2507AQ Timing Chart 1-8 DCLV PWM MD = 0 BRAKE Z MDS L MDP Z H MON DCLV PWM MD = 1 MDS MDP MON H – 19 – CXD2507AQ 1-2. Description of SENS Output The following signals are output from SENS, depending on the microcomputer serial register value (latching not required). Microcomputer serial register SENS value (latching not required) output Meaning $0X, 1X, 2X, 3X SEIN $4X XBUSY Low while the auto sequencer is in operation, high when operation terminates. $5X FOK $6X SEIN $AX GFS High when the played back frame sync is obtained with the correct timing. $EX OV64 Low when the EFM signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. $7X, 8X, 9X, BX, CX, DX, FX Low SEIN, a signal input to the CXD2507 from the SSP, is output. Outputs the signal input to the FOK pin. Normally, FOK (from RF) is input. High for "focus OK". SEIN, a signal input to CXD2507 from the SSP, is output. The SENS pin is fixed low. Note that the SENS output can be read from the SQSO pin when SL1=1 and SL0=0. (See the $BX commands.) 2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2507. Sub Q can be read out after the CRC check of the 80 bits of information in the subcode frame. This accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from SQSO pin. 2-1. P to W Subcode Read Data can be read out by inputting EXCK immediately after WFCK falls. (See Fig. 2-1.) Also, SBSO can be read out from SQSO pin when SL1 = 0 and SL0 = 1. (See the $BX commands.) 2-2. 80-bit Sub Q Read Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register. • First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. • 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the parallel/serial register. When SQSO goes high 400µs or more later (monostable multivibrator time constant) after the subcode is read out, the CPU determines that new data (which passed the CRC check) has been loaded. • In the CXD2507, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first. • Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read. In the CXD2507, the SQCK input is detected, and the retriggerable monostable multivibrator for low is reset. • The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration of SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register. • While the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by CRCOK and others. • Fig. 2-3 shows Timing Chart. • Although a clock is input from SQCK pin to actually perform these operations, the high and low intervals for this clock should be between 750ns and 120µs. – 20 – CXD2507AQ Timing Chart 2-1 Interrel PLL clock 4.3218 ± ∆MHz WFCK SCOR EXCK 400ns max SBSO S0-S1 Q R WFCK SCOR EXCK SBSO S0-S1 Q R S T U V W S0-S1 Same P1 Q R S T U V W P1 Same Subcode P.Q.R.S.T.U.V.W Read Timing – 21 – P2 P3 SUBQ SI LD H G F E D C B A A B C D E F G H SIN Order Inversion – 22 – CRCC SUBQ 8 LD (ASEC) 8 (AMIN) 80bit S/P Register 8 80bit S/P Register Mono/Multi LD (AFRAM) LD SHIFT 8 8 8 8 LD Mix CRCF 8 SHIFT SQSO 8 ADDRS CTRL LD Block Diagram 2-2 SQCK SO CXD2507AQ LD LD – 23 – SQSO SQCK CRCF Mono/multi (Interral) SQCK SQSO SCOR WFCK Timing Chart 2-3 CRCF1 1 2 Order Inversion ADR1 3 2 1 ADR3 270 to 400µs for SQCK = high ADR2 94 CTL0 Determined by mode 93 92 91 Register load forbidder 80 Clock 750ns to 120µs 300ns max ADR0 3 95 L CTL1 96 CTL2 97 CTL3 CRCF2 98 CXD2507AQ CXD2507AQ 3. Description of Other Functions 3-1. Channel Clock Regeneration by Digital PLL Circuit • The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is channel clock, is required. In an actual player, the fluctuation in the spindle rotation alters the width of the EFM signal pulses, making a PLL necessary for regenerating channel clock. The block diagram of this PLL is shown in Fig. 3-1. The CXD2507 has a built-in two-stage PLL as shown in the diagram. • The first-stage PLL generates a high-frequency clock needed by the second-stage digital PLL. • The second-stage PLL is a digital PLL that regenerates actual channel clock, and has a ±250kHz (normal state) or more capture range. Block Diagram 3-1 OSC X'tal 1/M Phase comparator XTSL PCO 1/N FILI FILO CLTV VCO VDD Digital PLL RFPLL CXD2507 – 24 – CXD2507AQ 3-2. Frame Sync Protection • In a CD player operating at normal speed, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame sync can not be recognized, the data is processed as error data because it can not be recognized what the data is. As a result, recognizing the frame sync properly is extremely important for improving playability. • There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter is fixed to 3. In other words, when the frame sync is being played back normally and then can not be detected due to scratches, a maximum of 13 frames are inserted. If frame sync can not be detected for 13 frames or more, the window is released and the frame sync is resynchronized. In addition, immediately after the window is released and resynchronization is executed, if a proper frame sync can not be detected within 3 frames, the window is released immediately. 3-3. Error Correction • In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance 5. • The CXD2507 SEC strategy provides excellent playability through powerful frame sync protection and C1 and C2 error corrections. • The correction status can be monitored outside the LSI. See Table 3-2. • When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held for that data, or an average value interpolation was made. MNT3 MNT1 MNT0 Description 0 0 0 No C1 errors 0 0 1 One C1 errors corrected 0 1 1 C1 correction impossible 1 0 0 No C2 errors 1 0 1 One C2 errors corrected 1 1 0 C2 correction impossible Table 3-2 – 25 – CXD2507AQ Timing Chart 3-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT1 MNT0 Strobe Strobe C4M MNT0, 1, 3 Valid Valid Invalid 3-4. DA Interface • The CXD2507 DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. – 26 – R0 1 2 – 27 – PCMD WDCK BCK (4.23M) LRCK (88.2k) R0 1 2 3 4 5 Lch MSB (15) Lch MSB (15) 48bit slot Double-Speed Playback PCMD WDCK BCK (2.12M) LRCK (44.1k) 48bit slot Normal-Speed Playback Timing Chart 3-4 6 7 8 9 L14 10 L13 11 L12 12 L0 24 L11 L9 Rch MSB L10 L8 L7 L6 L5 L4 L3 L2 L1 L0 24 RMSB CXD2507AQ CXD2507AQ 3-5. Digital Out There are three digital out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2507 supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3) of channel status. Digital Out C bit 0 2 3 From sub Q 0 ID0 16 1 0 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID1 COPY Emph 0 0 0 32 48 0 176 bit0 to 3 – Sub Q control bits that matched twice with CRCOK Table 3-5 3-6. Servo Auto Sequencer This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1 track jump, 2N track jumps, and N track move are executed automatically. SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the SSP, but they can be sent to the CXD2507. Connect the CPU, RF and SSP as shown in Fig. 3-6. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is designed to prevent the transfer of erroneous data to the SSP when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). – 28 – CXD2507AQ (a) Auto Focus ($47) Focus search up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Figure. 3-7. The auto focus is executed after focus search up, and the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Connection diagram for using auto sequencer (example) RF FOK FOK DATA CXD2507 SSP CLOK XLAT C. out CNIN SENS SEIN DATA DATO CLK CLKO XLT XLTO Micro-computer SENS Fig. 3-6. Auto focus Focus search up FOK=H NO YES (Checks whether FZC has stayed high longer than the period of time E set in register 5) FZC = H NO YES FZC = L NO YES Focus servo ON END Fig. 3-7-(a). Auto Focus Flow Chart – 29 – CXD2507AQ $47latch XLT FOK SEIN (FZC) BUSY Blind E Command for SSP $08 $03 Fig. 3-7-(b). Auto Focus Timing Chart (b) Track Jump 1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking, and the sled servo are on. Note that tracking gain up and braking on ($17) should be sent beforehand because they are not performed. • 1-track jump When $48 ($49 for REV) is received from the CPU, an FWD (REV) 1-track jump is performed in accordance with Fig. 3-8. Set blind A and brake B with register 5. • 10-track jump When $4A ($4B for REV) is received from the CPU, an FWD (REV) 10-track jump is performed in accordance with Fig. 3-9. The principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. In addition, after kicking the actuator, 5 tracks have been counted through CNIN, and the brake is applied to the actuator. Then, the actuator speed is found to have slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set in register 5), and the tracking and sled servos are turned on. • 2N-track jump When $4C ($4D for REV) is received from the CPU, an FWD (REV) 2N-track jump is performed in accordance with Fig. 3-10. The track jump count "N" is set in register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6. • N-track move When $4E ($4F for REV) is received from the CPU, an FWD (REV) N-track move is performed in accordance with Fig. 3-11. N can be set to a maximum of 216 tracks. CNIN is used for counting the number of jumps. This N-track move uses a method in which only the sled is moved, and is suited for moves over thousands of tracks. – 30 – CXD2507AQ Track Track kick sled servo (REV kick for REV jump) WAIT (Blind A) CNIN = NO YES Track REV kick (FWD kick for REV jump) WAIT (Brake B) Track, sled servo ON END Fig. 3-8-(a). 1-Track Jump Flow Chart $48 (REV = $49) latch XLT CNIN BUSY Brake B Blind A Command for SSP $2C ($28) $28 ($2C) Fig. 3-8-(b). 1-Track Jump Timing Chart – 31 – $25 CXD2507AQ 10 Track Track, sled FWD kick WAIT (Blind A) (Counts CNIN × 5) CNIN = 5 ? NO YES Track, REV kick (Checks whether the CNIN cycle is longer than overflow C) C = Overflow ? NO YES Track, sled servo ON END Fig. 3-9-(a). 10-Track Jump Flow Chart $4A (REV = $4B) latch XLT CNIN BUSY Blind A Command for SSP Overflow C CNIN 5count $2E ($2B) $2A ($2F) Fig. 3-9-(b). 10-Track Jump Timing Chart – 32 – $25 CXD2507AQ 2N Track Track, sled FWD kick WAIT (Blind A) CNIN = N NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 3-10-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) latch XLT CNIN BUSY Blind A Command for SSP $2A ($2F) CNIN N count Overflow $2E ($2B) $26 ($27) Fig. 3-10-(b). 2N-Track Jump Timing Chart – 33 – Kick D $25 CXD2507AQ N Track move Track servo OFF Sled FWD kick WAIT (Blind A) CNIN = N NO YES Track, sled servo ON END END Fig. 3-11-(a). N-Track Move Flow Chart $4E (REV = $4F) latch XLT CNIN BUSY Blind A Command for SSP CNIN N count $25 $22 ($23) Fig. 3-11-(b). N-Track Move Timing Chart – 34 – CXD2507AQ 3-7. Digital CLV Fig. 3-12 shows the Block Diagram. Digital CLV makes PWM output in CLVS and CLVP with the MDS error and MDP error signal sampling frequency increased to 130kHz during normal speed operation. In addition, the digital spindle servo can set the gain. Digital CLV Gain CLVS U/D MDS Error MDP Error 0, –6dB Measure Measure Over Sampling Filter-1 2/1 MUX CLV P/S GS (Gain) GP (Gain) 1/2 CLV P Mux CLV S Over Sampling Filter-2 CLV • P/S Noise Shape KICK, BRAKE STOP Modulation Mode Select DCLVMD Fig. 3-12. Block Diagram – 35 – MDP MDS CXD2507AQ 3-8. Asymmetry Compensation Fig. 3-13 shows the Block Diagram and Circuit Example. ASYE ASYO R1 RF R1 R2 R1 ASYI R1 BIAS R1 2 = R2 5 Fig. 3-13. Example of Asymmetry Correction Application Circuit Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 36 – CXD2507AQ Application Circuit FOK LDON SENS XRST XLT DATA SQCK SUBQ QFS CLK MUTE SCOR VDD GND to CPU GND LDON SSP GND XLAT CLOK SEIN CNIN DATO VDD XLTO CLKO SPOA SPOB SPOC DATA 51 2 MON XRST 50 3 MDP SENS 49 4 MDS MUTE 48 5 LOCK SQCK 47 6 TEST SQSO 46 7 FILO EXCK 45 8 FILI SBSO 44 9 PCO SCOR 43 GND 10 Vss GND 11 AVss WFCK 41 12 CLTV EMPH 40 13 AVDD DOUT 39 Vss 42 14 RF RF FSTT 37 GND MNT0 MNT1 RFCK XPCK XUGF BCK MNT3 MNT0 33 XROF GND 19 WDCK C2PO XTAI 34 GFS GND 18 ASYE VDD XTAO 35 GTOP XTSL 36 17 ASYO PCMD 16 ASYI LRCK GND GND C4M 38 15 BIAS GND OPEN MNT1 MNT2 XROF RFCK GND GND C2PO EMPH MUTE C2PO PCMD BCK LRCK WDCK GND GND MNT3 GFS XPCK XUGF GTOP 20 21 22 23 24 25 26 27 28 29 30 31 32 to D/A converter Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 37 – to error rate counter DRIVER 1 FOK SPOD RF XLON 64 63 62 61 60 59 58 57 56 55 54 53 52 CXD2507AQ Unit: mm 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 0.8 ± 0.2 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP–64P–L01 LEAD TREATMENT EIAJ CODE ∗ QFP064–P–1420 LEAD MATERIAL SOLDER/PALLADIUM PLATING COPPER /42 ALLOY PACKAGE WEIGHT 1.5g JEDEC CODE 64PIN QFP (PLASTIC) 24.98 ± 0.4 20.20 MAX 0.15 ± 0.05 0.15 33 32 64 20 1 (16.4) 52 19.00 ± 0.4 51 14.20 MAX + 0.1 0.1 – 0.05 19 1.0 1.3 ± 0.2 Package Outline 2.1 MAX 0.55 MAX ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-64P-L121 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP064-P-1420-AX LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 1.5g JEDEC CODE – 38 –