CXG1091TN SP4T GSM Dualband Antenna Switch 5V + Logic For the availability of this product, please contact the sales office. Description The SP4T + logic is a high power antenna switch MMIC for use in dualband GSM handsets. One Antenna can be routed to either of the 2 Tx or 2 Rx ports. It operates from 3 CMOS control lines (Tx ON/OFF and GSM900/1800 and Standby). The Sony's J-FET process is used for low insertion loss. 16 pin TSSOP (Plastic) Features • 3 CMOS compatible control lines • 34dBm power handling at 5.0V (GSM900) • Low second harmonic < – 30dBm at 34dBm • Small package size: 16-pin TSSOP (3.9 × 4.1mm) Applications Dualband handsets using combinations of GSM900/GSM1800/GSM1900 and DECT Structure GaAs J-FET MMIC Truth Table Band select Tx (H)/Rx (L) Standby Ant.-Tx1 GSM900 H H H Ant.-Tx2 GSM1800 L H H Ant.-Rx1 GSM900/1800 L L H Ant.-Rx2 GSM900/1800 H L H OFF — — L On Pass Absolute Maximum Ratings (Ta = 25°C) 7 • Bias voltage VDD • Control voltage Vctl 5 • Operating temperature Topr –35 to +85 • Storage temperature Tstg –65 to +150 V V °C °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99758A9Y-PS CXG1091TN Electrical Characteristics (Ta = 25°C) Item Port Symbol Ant-Tx1, Tx2 Insertion loss IL Ant-Rx1, Rx2 Ant-Tx1, Tx2 Isolation ISO. Ant-Rx1, Rx2 Condition Typ. Max. Unit ∗1 0.5 0.75 dB ∗2 0.6 0.85 dB ∗3 0.55 0.75 dB ∗4 0.7 0.9 dB ∗1 20 25 dB ∗2 17 20 dB ∗3 24 28 dB ∗4 20 24 dB VSWR VSWR 2fo Harmonics Note) 3fo 1.2 ∗1, ∗2 Ant-Tx1, Tx2 –30 dBm ∗1, ∗2 –30 dBm Ant-Tx1, Tx2 ∗1, ∗2 P1dB compression input power P1dB Switching speed TSW Control current ICTL Supply current IDD STBY = H Leakage current IIK STBY = L ∗1 ∗2 ∗3 ∗4 Pin = 34dBm, 880 to 915MHz, VDD = 5.0V Pin = 32dBm, 1710 to 1785MHz, VDD = 5.0V Pin = 10dBm, 925 to 960MHz Pin = 10dBm, 1805 to 1880MHz Note) Harmonics measured with Tx inputs harmonically matched. CMOS Logic Values Logic High Low (Ta = 25°C) Min. Typ. 2.4V 3.0V 0.0V Min. Max. 0.8V –2– 36 dBm 1 µs 100 µA 0.5 1 mA 50 µA CXG1091TN Recommended Circuit 100pF 9 GND Tx1 8 10 GND GND 7 11 ANT Tx2 6 100pF ( 100pF RRF ) 12 GND GND 5 13 VDD Rx1 4 14 GND GND 3 100pF 100pF 100pF Rx2 2 15 Band Select 100pF STDBY 1 16 Tx/Rx 100pF 100pF PCB Layout Recommendations • As indicated in the diagram AC coupling capacitors are necessary to the Ant, Tx1, Tx2, Rx1, Rx2 pins. • Ground plane should be included under the device and all ground pins connected to this. • RRF (68kΩ) is used to be stabilized the electrical characteristics at high power signal input. –3– CXG1091TN Unit: mm 16PIN TSSOP(PLASTIC) 1.2MAX 4.1 S 2.05 A 16 B 0.08 S X2 9 0.2 S A B 0.1 ± 0.05 (3.0) 3.9 2.9 0.1 X 0.25 0.1 X 8 X4 0.1 0.5 S A B 0.45 ± 0.1 1 0° to 8° 0.08 M S A B 0.2 ± 0.02 + 0.036 0.22 – 0.03 DETAIL B 0.1 ± 0.01 + 0.026 0.12 – 0.02 Package Outline PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.03g SONY CODE TSSOP-16P-L01 –4–