CXL1511M CCD Delay Line for PAL For the availability of this product, please contact the sales office. Description The CXL1511M is an IC developed for use in conjunction with Y/C signal processing ICs for PAL. This CCD delay line provides the comb filter output for eliminating the chrominance signal cross talk and 1H delay output for luminance signals. 24 pin SOP (Plastic) Features • Single power supply (5V) • Built-in triplex progression PLL circuit • Comb filter characteristics selectable • Delay time for 1H delay output selectable • Built-in peripheral circuits • Positive phase signal input, positive phase signal output Functions • Comb filter output • 1H delay output for luminance signal • Clock driver • Autobias circuit • Input clamp circuit (for luminance signals) • Center bias circuit (for chrominance signals) • Sample-and-hold circuit • Triplex progression PLL circuit • Luminance signal delay time/comb filter characteristics selection circuit • Clock buffer output circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD +6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Voltage (Ta = 25°C) VDD 5V ± 5% Structure CMOS-CCD Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95224-ST CXL1511M Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.) • Clock frequency fCLK 4.433619MHz • Input clock waveform sine wave Input Signal Amplitude Vsig 350mVp-p (Typ.), 575mVp-p (Max.) Vss C-OUT CONT AB-C fsc AB-P (NC) (NC) (NC) PCOUT VCOIN Vss Block Diagram and Pin Configuration (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 PLL fsc buffer Selector Timing D Output circuit (S/H) Autobias circuit (C) 1H/2H + D Driver φ1 φ2 Autobias circuit (Y) Bias circuit VDD C-IN2 (NC) (NC) 7 8 9 10 11 12 CLK 6 (NC) 5 (NC) 4 Y-OUT 3 (NC) 2 Output circuit (S/H) 1H Y-IN 1 C-IN1 Clamp circuit Vss Bias circuit Driver –2– CXL1511M SOP 24pin Pin No. Symbol Description I/O 1 VSS 2 C-IN1 3 VDD 4 C-IN2 I Chrominance signal input 2 5 (NC) — — 6 (NC) — — 7 Y-IN I 8 (NC) — 9 Y-OUT O 10 (NC) — — 11 (NC) — — 12 CLK I 13 VSS — 14 VCOIN I VCO input 15 PCOUT O Phase comparator output 16 (NC) — — 17 (NC) — — 18 (NC) — — 19 AB-P O Autobias output (P) 20 fsc O fsc buffer output 21 AB-C O Autobias output (C) 22 CONT I Control input 23 C-OUT O Chrominance signal output 24 VSS — GND — I — GND Chrominance signal input 1 Power supply Luminance signal input — Luminance signal output Clock input GND –3– CXL1511M Description of Functions The CXL1511M enables the chrominance comb filter characteristics and luminance signal delay time to be selected in the control input state. CONT Mode (typical example) Chrominance comb filter chracteristics Luminance signal delay time (number of CCD bits) L PAL/GBI 2H (1702.5bit) 1H (848.5bit) H 4.43NTSC 1H (844.5bit) 1H (842.5bit) CONT Input Level L/H Min. Typ. Max. L — 0 0.5 H 2.0 5.0 6.0 Unit V • fsc Output Pin The buffer output of the clock input from the CLK pin is provided at the fsc output pin. Since a pull-up resistor is contained inside the IC, the supply voltage is produced during open, and the output is stopped. Connect a 2.2kΩ pull-down resistor when the fsc output is to be used. <When in use> <When not in use> fsc fsc 2.2k –4– VDD CXL1511M Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 500mVp-p sine wave) See electrical Characteristics Measurement Circuit Item Supply current Symbol IDD1 IDD2 SW condition Measurement condition 1 2 3 4 5 6 b b b a a a — — b b b a b a — — — 7 Min. 8 Typ. Max. Unit NOTE 35 50 mA 1 Chrominance Signal Characteristics (No signals input to Y-IN) Item Symbol Low GLC1 frequency GLC2 gain Frequency response FC1 FC2 2 3 4 5 6 7 a a b a — a b a a b a — a b a a b a — a b a a b a — a b a a b a — a b a a b a — a b a a b a — a b a a b a — a b a a b a — a d a a b a — a d b b b a — a b b b b a — a b a b b — — a a (See Note 2) (See Note 3) LIC1 Linearity LIC2 Comb CCD1 depth min. CCD2 gain SNC1 SN ratio Coupling level Delay time SNC2 CPC1 CPC2 DC SW condition Measurement condition 1 (See Note 4) (See Note 5) 50% white video signal (See Note 7) (See Note 8) –5– Min. Typ. Max. Unit NOTE –2 0 2 dB 2 –2.7 –1.7 0 dB 3 –0.3 0 0.3 dB 4 –40 –25 dB 5 dB 6 52 — 56 10 50 mVrms 7 260 — ns 8 CXL1511M <Luminance Signal Characteristics> (No signals input to C-IN1, C-IN2) Item Symbol 2 3 4 5 6 7 b b a — b b b b b a — a b b b b a — b b b b b a — b b b b b a — a b c b b a — a b c b b a — a b c b b a — a b c b b a — a b a b b a — a b a b b a — b b d b b a — b b d b b b — b b b b b b — b b b Low GLY1 frequency GLY2 gain (See Note 2) Frequency FY1 response FY2 (See Note 3) Differential DGY1 gain DGY2 5-step staircase wave Differential DPY1 Phase DPY2 5-step staircase wave LNY1 Linearity LNY2 SNY1 SN ratio Coupling level SNY2 (See Note 10) 50% white video signal CPY1 CPY2 SW condition Measurement condition 1 (See Note 7) –6– Min. Typ. Max. Unit NOTE –2 0 2 dB 2 –2.7 –1.7 0 dB 3 0 3 5 % 9 0 3 5 deg 9 35 40 43 % 10 52 56 dB 6 mVrms 7 10 50 CXL1511M Note 1. This is the IC's supply current value when no signals are input. 2. This is the C-OUT and Y-OUT pin output gain when 500mVp-p sine waves are input to C-IN1, C-IN2 and Y-IN. (Example of calculation) GLC1 = 20 log C-OUT pin output voltage (mVp-p) [dB] 500 (mVp-p) Input signal frequency GLC1 (2H) GLC2 (1H) GLY1, GLY2 : 203.126kHz : 204.750kHz : 200kHz 3. This indicates the difference in the C-OUT and Y-OUT pin output gain when 200mVp-p low- and highfrequency sine waves are input to C-IN1, C-IN2 and Y-IN. Set the input bias (Vbias) to 2.0V when measuring the luminance signal characteristics (GLY1, GLY2, GHY1, GHY2). (Example of calculation) FC1 = 20 log C-OUT pin output voltage (high frequency) (mVp-p) [dB] C-OUT pin output voltage (low frequency) (mVp-p) Input signal frequency (low frequency) → see Note 2 Input signal frequency (high frequency) Chrominance signal (2H) : 4.429712MHz Chrominance signal (1H) : 4.425744MHz Luminance system : 4.43MHz 4. Calculate with the gain applying when 200mVp-p and 500mVp-p sine waves (see Note 2 for the frequencies) are input to C-IN1 and C-IN2. (Example of calculation) LIC1 = 20 log Output voltage with 500mVp-p input (mVp-p) 500mVp-p Output voltage with 200mVp-p input (mVp-p) 200mVp-p –7– [dB] CXL1511M 5. Measure the difference of the C-OUT output gain when 500mVp-p sine waves have been input to C-IN1 and C-IN2 at the following frequencies. Input signal frequency CCD1 CCD2 fp 4.429712MHz 4.425744MHz fN 4.425806MHz 4.417869MHz The frequency response for the outputs at fp and fN are shown in the figure below. Gain fN fp Frequency 6. Using the BPF 100kHz to 5MHz in the Sub Carrier Trap mode, measure the SN ratio on the video noise meter when the 50% white video signal shown in the figure below is input. 178mV 321mV 143mV 7. Measure the internal clock component (3fsc: 13.300856MHz component) when no signals are input. 8. Measure the delay time of the C-OUT output when the C-IN1 signal is input. –8– CXL1511M 9. On the vector scope, measure the differential gain and differential phase when the 5-step staircase wave shown in the figure below is input. 143mV 357mV 500mV 143mV 10. Input the 5-step staircase wave only for the luminance signal shown in the figure below, and measure the Y-OUT luminance level (Y) and SYNC level (S). (Example of calculation) Y LNY1 = 357mV 500mV S 143mV –9– S (mV) × 100 Y (mV) Signal generator – 10 – 0.01µ 0.01µ b 0.1µ a SW3 b a SW2 b a SW1 SW4 b a 1 24 2 3.3µ 23 Electrical Characteristics Measurement Circuit 4 21 A 5V 1000P 3 22 5 20 0.1µ 6 19 1M a 7 Vbias 1k 8 17 SW5 b 18 0.1µ 9 16 10 15 11 14 12 13 0.01µ 5V 0.1µ 1k CLK fsc (4.433619MHz) 0.5Vp-p sine wave 82k 1k 0.1µ 5V 1k b SW7 a SW6 d c b a BPF LPF Noise meter Vector scope Spectrum analyzer Oscilloscope CXL1511M Application Circuit – 11 – Y-IN C-IN2 C-IN1 0.1µ 0.01µ 0.01µ 1 24 3.3µ 5V 4 21 1000P 3 22 5 20 2.2k 18 0.1µ 6 1M 7 CXL1511M 19 fsc out 8 17 9 16 10 15 11 14 12 13 0.01µ 5V 0.1µ 1k CLK fsc (4.433619MHz) 0.5Vp-p sine wave 82k 1k 0.1µ 5V 1k Y-OUT C-OUT Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 2 23 0.1µ CONT1 (0/5V) When Pin 20 (fsc) output is used (connect to VDD when not used) CXL1511M CXL1511M Example of Representative Characteristics Frequency response vs. Supply voltage Low frequency gain vs. Supply voltage –1 Frequency response [dB] Low frequency gain [dB] 2 1 0 –1 –2 4.75 5 –2 –3 4.75 5.25 5 5.25 Supply voltage [V] Supply voltage [V] Comb depth vs. Supply voltage Chrominance linearity vs. Supply voltage –30 0.3 Chrominance linearity [dB] Comb depth [dB] 0.2 –35 0.1 0 –0.1 –0.2 5 –0.3 4.75 5.25 5.25 Supply voltage [V] Differential gain vs. Supply voltage Differential phase vs. Supply voltage 5 5 4 4 3 2 3 2 1 1 0 4.75 5 Supply voltage [V] Differential phase [degree] Differential gain [%] –40 4.75 5 0 4.75 5.25 5 Supply voltage [V] Supply voltage [V] – 12 – 5.25 CXL1511M Frequency response vs. Ambient temperature Low frequency gain vs. Ambient temperature –1 Frequency response [dB] Low frequency gain [dB] 2 1 0 –1 –2 –10 0 10 20 30 40 Ambient temperature [°C] 50 –2 –3 60 –10 Comb depth vs. Ambient temperature 50 60 Chrominance linearity [dB] 2 –35 –40 –10 0 10 20 30 40 50 1 0 –1 –2 60 –10 0 Ambient temperature [°C] Differential phase [degree] 4 2 0 –10 0 10 20 30 40 Ambient temperature [°C] 50 10 20 30 40 Ambient temperature [°C] 50 60 Differential phase vs. Ambient temperature Differential gain vs. Ambient temperature Differential gain [%] 10 20 30 40 Ambient temperature [°C] Chrominance linearity vs. Ambient temperature –30 Comb depth [dB] 0 4 2 0 60 – 13 – –10 0 10 20 30 40 Ambient temperature [°C] 50 60 CXL1511M Package Outline Unit: mm 24PIN SOP (PLASTIC) + 0.4 15.0 – 0.1 24 + 0.4 1.85 – 0.15 13 6.9 + 0.2 0.1 – 0.05 12 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.5 ± 0.2 1 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 ± 0.12 M PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE SOP-24P-L01 EIAJ CODE ∗SOP024-P-0300-A JEDEC CODE EPOXY/PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER ALLOY / 42ALLOY PACKAGE WEIGHT 0.3g – 14 –