SONY CXP85460

CXP85452/85460
CMOS 8-bit Single Chip Microcomputer
Description
The CXP85452/85460 are a highly integrated microcomputers composed of a 8-bit CPU, ROM, RAM,
and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design,
including an A/D converter, serial interface,
timer/counter, time-base timer, on-screen display
function, I2C bus interface, PWM output, remote
control reception circuit, HSYNC counter, and
watchdog timer.
Futhermore, the CXP85452/85460 series provides
power-on reset and sleep functions which enable to
lower power consumption.
64 pin SDIP (PIastic)
64 pin QFP (PIastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which covers various types of data
– 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
0.5µs at 8MHz
• Incorporated ROM capacity 52K bytes (CXP85452)
60K bytes (CXP85460)
• Incorporated RAM capacity 960 bytes
• Peripheral functions
– A/D converter
8-bit, 4-channel successive approximation method
(Conversion time of 20µs at 8MHz)
– Serial interface
8-bit clock sync type, 1 channel
– Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
– On screen display (OSD) function 12 × 18 dots, 384 character types, 15 character colors,
12lines of 32 characters,
black frame output/half blanking, shadow, background
color on full screen/half blanking,
double scanning, jitter elimination circuit
– I2C bus interface
– PWM output
14 bits, 1 channel
8 bits, 8 channels
– Remote control reception circuit
8-bit pulse measurement circuit, 6-state FIFO
– HSYNC counter
2 channels
– Watchdog timer
• Interruption
13 factors, 13 vectors, multi-interruption possible
• Standby mode
SLEEP
• Package
64-pin plastic SDIP/QFP
• Piggyback/evaluator
CXP85400 64-pin ceramic PSDIP/PQFP
CXP85490 64-pin ceramic PSDIP (accommodates custom font)
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94323B86
HSYNC COUNTER 1
A/D CONVERTER
I2C BUS
INTERFACE UNIT
HS1
AN0
to
AN3
SCL0
SCL1
SDA0
SDA1
FIFO
HSYNC COUNTER 0
REMOCON
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
SERIAL INTERFACE UNIT
HS0
RMC
EC
TO
SI
SO
SCK
ON SCREEN DISPLAY
2
2
INT2
INT1
INTERRUPT
CONTROLLER
INT0
14 BIT PWM
WATCH DOG TIMER
PWM
XLC
EXLC
R
G
B
I
YS
YM
HSYNC
VSYNC
8 BIT PWM
8CH
ROM
52K/60K
SPC700
CPU CORE
PWM0
to
PWM7
VSS
VDD
RST
MP
EXTAL
XTAL
PRESCALER/
TIME BASE TIMER
RAM
960 BYTES
CLOCK GENERATOR/
SYSTEM CONTROL
PF0 to PF7
PE6 to PE7
PE0 to PE5
PD0 to PD7
PC0 to PC7
PA0 to PA7
PB0 to PB7
PORT A
PORT B
PORT C
PORT D
PORT E
–2–
PORT F
Block Diagram
CXP85452/85460
CXP85452/85460
Pin Assignment (Top View) 64-pin SDIP
HSYNC/PA7
1
64
VDD
VSYNC/PA6
2
63
NC
PA5
3
62
VSS
PA4
4
61
MP
PA3
5
60
PF0/PWM0
PA2
6
59
PF1/PWM1
PA1
7
58
PF2/PWM2
PA0
8
57
PF3/PWM3
PB7
9
56
PF4/PWM4/SCL0
PB6
10
55
PF5/PWM5/SCL1
PB5
11
54
PF6/PWM6/SDA0
PB4
12
53
PF7/PWM7/SDA1
PB3
13
52
YM
PB2
14
51
YS
PB1
15
50
I
PB0
16
49
B
PC7
17
48
G
PC6
18
47
R
PC5
19
46
EXLC
PC4
20
45
XLC
PC3
21
44
PE0/INT0
PC2
22
43
PE1/INT1
PC1
23
42
AN0/PE2
PC0
24
41
AN1/PE3
EC/PD7
25
40
AN2/PE4
RMC/PD6
26
39
AN3/PE5
HS1/PD5
27
38
PE6/PWM
HS0/PD4
28
37
PE7/TO
SI/PD3
29
36
RST
SO/PD2
30
35
EXTAL
SCK/PD1
31
34
XTAL
32
33
PD0/INT2
VSS
Note) 1. NC (Pin 63) is always connected to VDD.
2. Vss (Pins 32 and 62) are both connected to GND.
3. MP (Pin 61) is always connected to GND.
–3–
CXP85452/85460
PF2/PWM2
PF1/PWM1
PF0/PWM0
MP
VDD
NC
PA7/HSYNC
VSS
PA5
PA6/VSYNC
PA3
PA4
PA2
Pin Assignment (Top View) 64-pin QFP
64 63 62 61 60 59 58 57 56 55 54 53 52
1
51
PF3/PWM3
PA0
2
50
PF4/PWM4/SCL0
PB7
3
49
PF5/PWM5/SCL1
PB6
4
48
PF6/PWM6/SDA0
PB5
PA1
5
47
PF7/PWM7/SDA1
PB4
6
46
YM
PB3
7
45
YS
PB2
8
44
I
PB1
9
43
B
PB0
10
42
G
PC7
11
41
R
PC6
12
40
EXLC
PC5
13
39
XLC
14
38
PE0/INT0
PE1/INT1
PC4
15
37
PC2
16
36
AN0/PE2
PC1
17
35
AN1/PE3
PC0
18
34
AN2/PE4
19
33
AN3/PE5
TO/PE7
PWM/PE6
RST
EXTAL
XTAL
VSS
INT2/PD0
SCK/PD1
SI/PD3
SO/PD2
HS1/PD5
20 21 22 23 24 25 26 27 28 29 30 31 32
HS0/PD4
EC/PD7
RMC/PD6
PC3
Note) 1. NC (Pin 56) is always connected to VDD.
2. Vss (Pins 26 and 58) are both connected to GND.
3. MP (Pin 55) is always connected to GND.
–4–
CXP85452/85460
Pin Description
Symbol
I/O
Description
PA0 to PA5
I/O
PA6/VSYNC
I/O/Input
(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
OSD display vertical synchronization signal input pin.
PA7/HSYNC
I/O/Input
OSD display horizontal synchronization signal input pin.
PB0 to PB7
I/O
(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
PC0 to PC7
I/O
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
PD0/INT2
I/O/Input
PD1/SCK
I/O/I/O
PD2/SO
I/O/Output
PD3/SI
I/O/Input
PD4/HS0
I/O/Input
PD5/HS1
I/O/Input
PD6/RMC
I/O/Input
Remote control reception circuit input pin.
PD7/EC
I/O/Input
External event input pin for timer/counter.
PE0/INT0
PE1/INT1
Input/Input
Input pin for external interruption request.
Active when falling edge.
(2 pins)
PE2/AN0
to
PE5/AN3
Input/Input
PE6/PWM
Output/Output
PE7/TO
Output/Output
PF0/PWM0
to
PF3/PWM3
Output/Output
PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
Output/Output/
I/O
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1
Output/Output/
I/O
R, G, B, I, YS, YM Output
Input pin for external interruption request.
Active when falling edge.
(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
12mA sink current
drive possible.
(8 pins)
(Port E)
8-bit port. Lower
6 bits are for inputs;
upper 2 bits are for
outputs.
(8 pins)
Serial clock I/O pin.
Serial data output pin.
Serial data input pin.
HSYNC counter (CH0) input pin.
HSYNC counter (CH1) input pin.
Analog input pin for A/D converter.
(4 pins)
14-bit PWM output pin.
(CMOS output)
Timer/counter rectangular wave output pin.
(Port F)
8-bit output port.
Large current
(12mA) N-ch open
drain output.
Lower 4 bits are
mid-voltage drive
(12V); upper 4 bits
are 5V drive.
(8 pins)
8-bit PWM output pin.
(8 pins)
I2C bus interface transfer clock I/O pin.
(2 pins)
I2C bus interface transfer data I/O pin.
(2 pins)
OSD display 6-bit output pin. (6 pins)
–5–
CXP85452/85460
Symbol
I/O
Description
EXLC
Input
XLC
Output
EXTAL
Input
XTAL
Output
RST
I/O
System reset pin for active at low level. This pin becomes I/O pin, and
outputs low level at the power on with power-on reset function executed.
(Mask option)
MP
Input
Test mode input pin. Always connect to GND.
OSD display clock oscillation I/O pin.
Oscillation frequency is determined by the external L and C.
Crystal connection pin for system clock oscillation. When using an external
clock, input to EXTAL pin and leave XTAL pin open.
NC
NC. Under normal operation, connect to VDD.
VDD
Positive supply voltage pin.
Vss
GND. Both Vss pins should be connected to common GND.
–6–
CXP85452/85460
Input/Output Circuit Formats for Pins
Pin
Circuit format
Port A
Port B
Port C
PA0 to PA5
PB0 to PB7
PC0 to PC7
When reset
AAAAA
AAAAA
AAAAA
AAAAA
AA
AA
AA
AA
Ports A, B, C data
Ports A, B, C direction
“0” when reset
IP
Data bus
RD
(Ports A, B, C)
22 pins
Port A
AAAA
AAAA
AAAA
Port A direction
“0” when reset
PA6/VSYNC
PA7/HSYNC
Input protection
circuit
AA
AA
AA
AA
Port A data
IP
Data bus
RD (Port A)
Schmitt input
VSYNC
HSYNC
Hi-Z
Hi-Z
AAAA
AAAA
Input multiplexer
2 pins
“0” when reset
Port D
PD0/INT2
PD3/SI
PD4/HS0
PD5/HS1
AAAA
AAAA
AAAA
Port D data
Port D direction
“0” when reset
PD6/RMC
PD7/EC
AA
AA
AA
AA
∗
Schmitt input
Data bus
RD (Port D)
IP
∗ Large current 12mA
INT2, SI, HS0, HS1, RMC, EC
6 pins
–7–
Hi-Z
CXP85452/85460
Pin
Circuit format
When reset
Port D
AA
AA
AA
AA
SCK or SO
Output enable
∗
AAAA
AAAA
PD1/SCK
PD2/SO
Port D data
IP
Port D direction
“0” when reset
Hi-Z
Schmitt input
Data bus
RD (Port D)
∗ Large current 12mA
SCK only
2 pins
Port E
PE0/INT0
PE1/INT1
AAAA
AA
A
AA
A
AA
AAAAA
AAAAA
Schmitt input
(Interrupt circuit)
IP
2 pins
Port E
PE2/AN0
to
PE5/AN3
Hi-Z
Data bus
RD (Port E)
Input multiplexer
IP
Port E function selection
“0” when reset
4 pins
To A/D converter
Hi-Z
Data bus
RD (Port E)
Port E
AAAAA
AAAAA
AAAAA
AAAAA
AA
AA
TO, PWM
PE6/PWM
PE7/TO
Port E data
“1” when reset
Port E function selection
“1” when reset
2 pins
–8–
High level
CXP85452/85460
Pin
Circuit format
Port F
PF0/PWM0
to
PF3/PWM3
When reset
PWM
AAAAA
AAAAA
AAAAA
Port F data
∗
“1” when reset
Port F selection
4 pins
Large current 12mA
SCL, SDA
∗
I2C output enable
AAAAA
AAAAA
AAAAA
AAAAA
A
Port F data
6 pins
EXLC
XLC
Schmitt input
SCL, SDA
(I2C circuit)
BUS SW
To internal I2C pins
∗ Large current 12mA
AAAA
AAAA
AA
AA
R, G, B, I, YS, YM
Output polarity
“0” when reset
Hi-Z
Writing data to output polarity
register brings output to active
AA
A
AAA
AA
AA
AA AA
EXLC
XLC
2 pins
Hi-Z
IP
“1” when reset
“0” when reset
R
G
B
I
YS
YM
AA
PWM
Port F function selection
4 pins
Hi-Z
∗ 12V voltage drive
“0” when reset
Port F
PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1
AA
IP
IP
–9–
Oscillator control
Oscillation
halted
OSD display clock
CXP85452/85460
Pin
EXTAL
XTAL
Circuit format
AA
A
AA A
AA
AA
AA
AA
When reset
• Shows the circuit composition
during oscillation.
IP
EXTAL
• Feedback resistor is removed
during STOP.
(This device does not enter
the STOP mode.)
Oscillation
XTAL
2 pins
Pull-up resistor
Mask option
RST
1 pin
Schmitt input
OP
Low level
From power-on reset circuit
(Mask option)
– 10 –
CXP85452/85460
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Symbol
Ratings
Unit
V
Remarks
Supply voltage
VDD
Input voltage
VIN
–0.3 to +7.0
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
Mid-voltage drive output voltage
VOUTP
–0.3 to +15.0
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of all output pins
IOL
15
mA
Ports excluding large current
output (value per pin)
IOLC
20
mA
Large current output port
(value per pin)∗2
Low level total output current
∑IOL
130
mA
Total of all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
1000
mW
SDIP
600
mW
QFP
V
Low level output current
PF0 to PF3 pins
∗1 VIN and VOUT should not exceed VDD + 0.3V.
∗2 The large current output port is Port D (PD) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Recommended Operating Conditions
Item
Min.
Max.
Unit
4.5
5.5
V
3.5
5.5
V
2.5
5.5
V
Guaranteed operation range for 1/16 frequency
dividing mode or SLEEP mode.
Guaranteed data hold range for STOP mode.∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
∗3
VIHEX
VDD – 0.4
VDD + 0.3
V
VIL
0
0.3VDD
V
EXTAL pin∗4
∗2
VILS
0
0.2VDD
V
∗3
VILEX
–0.3
0.4
V
EXTAL pin∗4
Operating temperature Topr
–20
+75
°C
Supply voltage
High level
input voltage
Low level
input voltage
∗1
∗2
∗3
∗4
Symbol
(Vss = 0V reference)
VDD
Remarks
Guaranteed operation range for 1/2 and 1/4
frequency dividing modes.
This device does not enter the STOP mode.
PA, PB, PC, PE2 to PE5, SCL0, SCL1, SDA0, SDA1 pins
INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, HSYNC, VSYNC, RST pins
Specifies only during external clock input.
– 11 –
CXP85452/85460
DC Characteristics
Item
High level
output voltage
Low level
output voltage
(Ta = –20 to +75°C, Vss = 0V reference)
Symbol
VOH
VOL
IIHE
Input current
Pin
Condition
PA to PD, PE6, PE7, VDD = 4.5V, IOH = –0.5mA
R, G, B, I, YS, YM
VDD = 4.5V, IOH = –1.2mA
Min.
Typ.
Max.
Unit
4.0
V
3.5
V
PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA
R, G, B, I, YS, YM,
PF0 to PF3, RST∗1 VDD = 4.5V, IOL = 3.6mA
0.4
V
0.6
V
PD, PF
VDD = 4.5V, IOL = 12.0mA
1.5
V
PF4 to PF7
(SCL0, SCL1,
SDA0, SDA1)
VDD = 4.5V, IOL = 3.0mA
0.4
V
VDD = 4.5V, IOL = 4.0mA
0.6
V
EXTAL
IIHL
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
–1.5
–400
µA
IILR
RST∗2
VDD = 5.5V, VIL = 0.4V
I/O leakage current
IIZ
PA to PE, HSYNC,
VSYNC, R, G, B, I,
YS, YM, RST∗2
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
Open drain output
leakage current
(N-ch Tr off)
PF0 to PF3
VDD = 5.5V, VOH = 12.0V
50
µA
ILOH
PF4 to PF7
VDD = 5.5V, VOH = 5.5V
10
µA
SCL0: SCL1
SDA0: SDA1
VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V
120
Ω
I2C bus switch
connection impedance RBS
(Output Tr off)
IDD
Supply current
IDDSL
VDD∗3
CIN
18
30
mA
SLEEP mode
VDD = 5.5V,
8MHz crystal oscillation
(C1 = C2 = 22pF)
0.9
3
mA
—
—
µA
10
20
pF
STOP mode∗4
VDD = 5.5V,
termination of 8MHz
oscillation
IDDST
Input capacitance
1/2 frequency dividing
operation mode
VDD = 5.5V,
8MHz crystal oscillation
(C1 = C2 = 22pF)
PA to PD,
PE0 to PE5, SCL,
SDA, EXLC,
EXTAL, RST
1MHz clock
0V for non-measurement pins
—
∗1 Specifies RST pin only when the power-on reset circuit is selected with mask option.
∗2 For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current
when non-resistor is selected.
∗3 When all output pins open. Specifies only when the OSD oscillation is halted.
∗4 This device does not enter the stop mode.
– 12 –
CXP85452/85460
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
9
MHz
System clock frequency
fC
XTAL
EXTAL
Fig. 1, Fig. 2
3.5
System clock input
pulse width
tXL,
tXH
EXTAL
Fig. 1, Fig. 2
External clock drive
50
System clock
rise and fall times
tCR,
tCF
tEH,
tEL
tER,
tEF
EXTAL
Fig 1, Fig 2
External clock drive
EC
Fig. 3
EC
Fig. 3
Event count input
clock pulse width
Event count input clock
rise and fall times
ns
200
tsys + 50∗1
ns
ns
20
ms
∗1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits
(CPU clock selection).
tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
AAAAA AAAAA
AAAAA AAAAA
AAAAA AAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
External clock
EXTAL
XTAL
C2
XTAL
OPEN
Fig. 3. Event count clock timing
0.8VDD
EC
0.2VDD
tEH
tEF
– 13 –
tEL
tER
CXP85452/85460
(2) Serial transfer
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
tKCY
SCK
SCK
high and low level widths
tKH
tKL
SCK
SI input set-up time
(for SCK ↑)
tSIK
SI
SI hold time
(for SCK ↑)
tKSI
SI
SCK ↓ → SO delay time
tKSO
SO
SCK cycle time
Condition
Min.
Input mode
Max.
1000
ns
8000/fc
ns
400
ns
4000/fc – 50
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Output mode
SCK input mode
SCK output mode
SCK input mode
200
ns
SCK output mode
100
ns
Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
Fig. 4. Serial transfer timing
tKCY
tKL
tKH
0.8VDD
SCK
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI
Unit
0.2VDD
tKSO
0.8VDD
SO
Output data
0.2VDD
– 14 –
CXP85452/85460
(3) A/D converter characteristics
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Analog input voltage
VIAN
Pin
Condition
Min.
Ta = 25°C
VDD = 5.0V
Vss = 0V
Typ.
–50
10
70
mV
4910
4970
5030
mV
160/fADC∗3
12/fADC∗3
AN0 to AN3
0
µs
µs
VDD
V
Fig. 5. Definitions for A/D converter terms
FFH
FEH
Digital conversion value
∗1 VZT: Digital conversion values change between 00H←→01H.
∗2 VFT: Digital conversion values change between 0EH←→0FH.
∗3 fADC indicates the below values due to the contents of bit 6
(CKS) of the A/D control registor (ADC: 00F6H) and the bits 7
(PCK1) and 6 (PCK0) of the clock control registor (CLC: 00FEH)
CKS
Linearity error
0 (φ/2 selection)
1 (φ selection)
00 (φ = fEX/2)
fADC = fC/2
fADC = fC
01 (φ = fEX/4)
fADC = fC/4
fADC = fC/2
11 (φ = fEX/16)
fADC = fC/16
fADC = fC/8
PCK1, 0
01H
00H
VZT
VFT
Analog input
– 15 –
CXP85452/85460
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
tIH
tIL
tRSL
External interruption
high and low level widths
Reset input low level width
Pin
Condition
Min.
INT0 to
INT2
RST
Max.
Unit
1
µs
8/fc
µs
Fig. 6. Interruption input timing
tIH
tIL
0.8VDD
INT0 to INT2
(falling edge)
0.2VDD
Fig. 7. RST input timing
tRSL
RST
0.2VDD
(5) Power-on reset
Power-on reset∗1
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
tR
tOFF
Power supply rise time
Power supply cutt-off time
Pin
VDD
Condition
Power-on reset
Min.
Max.
Unit
0.05
50
ms
1
Repeated power-on reset
ms
∗1 Specifies only when power-on reset function is selected.
Fig. 8. Power-on reset
4.5V
VDD
0.2V
0.2V
tOFF
tR
Take care when turning on power.
– 16 –
CXP85452/85460
(6) I2C bus timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
0
100
kHz
SCL clock frequency
fSLC
SCL
Bus-free time before starting transfer
tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO
SDA, SCL
4.7
µs
SDA, SCL
4.0
µs
SCL
4.7
µs
SCL
4.0
µs
SDA, SCL
µs
SDA, SCL
4.7
0∗1
SDA, SCL
250
ns
Hold time for starting transfer
Clock low level width
Clock high level width
Set-up time for repeated transfers
Data hold time
Data set-up time
SDA, SCL rise time
SDA, SCL fall time
Set-up time for transfer completion
µs
SDA, SCL
1
µs
SDA, SCL
300
ns
SDA, SCL
4.7
µs
∗1 For the data hold time, the SCL rise time (300ns Max.) is not considered so that 300ns should be exceeded.
Fig. 9. I2C bus transfer data timing
SDA
tBUF
tR
tHD; STA
tF
SCL
tHD; STA
P
S
tSU; STA
tLOW
tHD; DAT
tHIGH
St
tSU; DAT
tSU; STO
P
Fig. 10. I2C device recommended circuit
I2C
device
RS
I2C
device
RS RS
RS RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• A pull-up resistor (Rp) must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike
noise caused by CRT flashover.
– 17 –
CXP85452/85460
(7) OSD timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Pin
Symbol
Condiiton
Min.
Max.
Unit
EXLC
XLC
Fig. 12
4
7∗1
14∗2
MHz
OSD clock frequency
fOSC
HSYNC pulse width
tHWD
tVWD
HSYNC
Fig. 11
1.2
HSYNC
Fig. 11
1
HSYNC afterwrite
rise and fall times
tHCG
HSYNC
Fig. 11
200
ns
VSYNC beforewrite
rise and fall times
tVCG
VSYNC
Fig. 11
1.0
µs
VSYNC pulse width
µs
H∗3
∗1 Oscillation clock at 4MHz operation
∗2 Oscillation clock at 8MHz operation
∗3 H indicates 1HSYNC period.
Fig. 11. OSD timing
tHCG
tHWD
0.8VDD
HSYNC
For OSD I/O polarity register
(OPOL: 01FAH)
bit 7 at “0”
0.2VDD
tVCG
tVWD
0.8VDD
VSYNC
For OSD I/O polarity register
(OPOL: 01FAH)
bit 6 at “0”
0.2VDD
Fig. 12. LC oscillation circuit connection
EXLC
XLC
L
C1
R∗1
C2
∗1 The series resistor for XLC is used to reduce the frequency of occurrence of the undesired radiation.
– 18 –
CXP85452/85460
Appendix
Fig. 13. SPC700 Series recommended oscillation circuit
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
(i)
EXTAL
(ii)
EXTAL
XTAL
XTAL
Rd
Rd
C2
C1
C1 C2
Manufacturer
MURATA MFG
CO., LTD.
Model
fc (MHz)
CSA4.00MG
4.00
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CST4.00MGW∗1
CST4.19MGW∗1
C1 (pF)
C2 (pF)
Rd (Ω)
Circuit
Example
(i)
30
30
0∗2
4.00
(ii)
4.19
CST8.00MTW∗1
8.00
4.00
RIVER ELETEC
CO., LTD.
HC-49/U03
4.19
12
12
0∗2
(i)
27
27
0∗2
(i)
8.00
4.00
KINSEKI LTD.
HC-49/U(-S)
4.19
8.00
∗1 These models have the on-chip grounding capacitors (C1 and C2).
∗2 The series resistor for XTAL can reduce the effect of the noise caused by the electrostatic discharge.
Mask Option Table
Item
Inclusion
Reset pin pull-up resistor
Non-existent
Existent
Power-on reset circuit
Non-existent
Existent
– 19 –
CXP85452/85460
Fig. 14. Characteristics curves
IDD vs. fc (VDD = 5V, Ta = 25°C, Typical)
IDD vs. VDD (fc = 8MHz, Ta = 25°C, Typical)
20
1
2 frequency mode
1
frequency mode 18
4
1
16 frequency mode
1
2
frequency mode
1
4
frequency mode
16
SLEEP mode
1
IDD – Supply current [mA]
14
12
10
8
6
0.1
2
3
4
5
6
4
1 frequency mode
16
VDD – Supply voltage [V]
2
SLEEP mode
0
1
5
10
fc – System clock [MHz]
Parameter Curve for OSD Oscillator L vs. C
(Analytically calculated value)
100
5.0MHz
L – Inductance [µH]
IDD – Supply current [mA]
10
6.5MHz
10
13.0MHz
fOSC =
1
2π√ LC
C = C1 // C2
0
50
C1, C2 – Capacitance [pF]
– 20 –
100
CXP85452/85460
Package Outline
Unit: mm
+ 0.1
0.05
0.25 –
64PIN SDIP (PLASTIC) 750mil
+ 0.4
57.6 – 0.1
64
19.05
+ 0.3
17.1 – 0.1
33
1
0° to 15°
32
3 MIN
0.5 MIN
+ 0.4
4.75 – 0.1
1.778
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY / PHENOL RESIN
SONY CODE
SDIP-64P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SDIP064-P-0750-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
8.6g
JEDEC CODE
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
64
20
1
16.3
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
+ 0.2
0.1 – 0.05
0.8 ± 0.2
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
1.0
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP–64P–L01
LEAD TREATMENT
EIAJ CODE
∗ QFP064–P–1420
LEAD MATERIAL
SOLDER/PALLADIUM
PLATING
COPPER /42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
– 21 –