ILX531A 5150-pixel CCD Linear Sensor (B/W) Description The ILX531A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 400 DPI, and A4-size documents at a density of 600 DPI at high speed. VDD φ2-ODD φ1-ODD 16 NC 8 15 φ2-EVEN 9 14 GND 13 φ1-EVEN 12 VDD 7 VDD 10 φROG 11 5150 φROG VDD GND φLH-ODD φ2-ODD φ1-ODD 11 10 14 3 8 9 φROG pulse generator CCD analog shift register Read out gate CCD analog shift register Read out gate 12 13 15 17 19 20 VDD VDD φ2-EVEN φ1-EVEN AAA AAA φRS-ODD 17 GND φCLP-ODD VOUT-EVEN GND 18 2 5 VGG 6 1 VOUT-ODD 4 VDD Output amplifier 19 5 4 VOUT-ODD GND VGG 6 20 φLH-EVEN Output amplifier φLH-ODD 3 AAA AAAAA A AAA AA A AA A AAAAAA 21 φRS-EVEN VOUT-EVEN 18 2 22 φCLP-EVEN 21 φRS-ODD 1 22 1 φCLP-EVEN φRS-EVEN φLH-EVEN VDD φCLP-ODD D25 D26 Pin Configuration (Top View) V °C °C D74 S1 S2 15 –10 to +60 –30 to +80 S5149 S5150 D75 Absolute Maximum Ratings • Supply voltage VDD • Operating temperature • Storage temperature Block Diagram D94 Features • Number of effective pixels: 5150 pixels • Pixel size: 7µm × 7µm (7µm pitch) • Clamp circuit are on-chip • Signal output phase of two-output simultaneous-output (alternate-output is available) • Ultra high sensitivity/Ultra low lag • Maximum data rate: 40MHz • Single 12V power supply • Input clock pulse: CMOS 5V drive • Package: 22 pin Plastic DIP (400mil) 22 pin DIP (Plastic) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97X25B97-PS ILX531A Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 φCLP-ODD Clock pulse input (odd pixel) 12 VDD 12V power supply 2 φRS-ODD Clock pulse input (odd pixel) 13 φ1-EVEN Clock pulse input (even pixel) 3 φLH-ODD Clock pulse input (odd pixel) 14 GND GND 4 GND GND 15 φ2-EVEN Clock pulse input (even pixel) 5 VOUT-ODD Signal out (odd pixel) 16 NC NC 6 VGG Output circuit gate bias 17 VDD 12V power supply 7 GND GND 18 VOUT-EVEN Signal out (even pixel) 8 φ2-ODD Clock pulse input (odd pixel) 19 VDD 12V power supply 9 φ1-ODD Clock pulse input (odd pixel) 20 φLH-EVEN Clock pulse input (even pixel) 10 VDD 12V power supply 21 φRS-EVEN Clock pulse input (even pixel) 11 φROG Readout gate clock pulse input 22 φCLP-EVEN Clock pulse input (even pixel) Recommended Supply Voltage Item Min. Typ. Max. Unit VDD 11.4 12 12.6 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Cφ1, Cφ2 — 400 — pF CφLH — 10 — pF CφRS — 10 — pF Input capacity of φCLP∗1 CφCLP — 10 — pF Input capacity of φROG CφROG — 10 — pF Input capacity of φ1∗1, φ2∗1 Input capacity of φLH∗1 Input capacity of φRS∗1 ∗1 It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD, φRS-EVEN as φRS, φCLP-ODD, φCLP-EVEN as φCLP. Clock Frequency Item Symbol Min. Typ. Max. Unit φ1, φ2, φLH, φRS, φCLP fφ1, fφ2, fφLH, fφRS, fφCLP — 1 20 MHz Data rate — 2 40 MHz Min. Typ. Max. Unit High level 4.75 5.0 5.25 V Low level — 0 0.1 V fφR Input Clock Pulse Voltage Condition Item φ1, φ2, φLH, φRS, φCLP, φROG pulse voltage –2– ILX531A Electrooptical Characteristics (Note 1) (Ta = 25°C, VDD = 12V, fφR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Item Symbol Min. Typ. Max. Unit Remarks Sensitivity1 R1 8.2 11 13.8 V/(lx · s) Note 2 Sensitivity2 R2 — 25.1 — V/(lx · s) Note 3 Sensitivity nonuniformity PRNU — 4 10 % Note 4 Saturation output voltage VSAT 1.8 2.5 — V Note 5 Saturation exposure SE 0.13 0.23 — lx · s Note 6 Register imbalance RI — 1 7 % Note 7 Dark voltage average VDRK — 0.3 2.0 mV Note 8 Dark signal nonuniformity DSNU — 0.6 5.0 mV Note 9 Image lag IL — 0.02 — % Note 10 Supply current IVDD — 30 60 mA — Total transfer efficiency TTE 92 98 — % — Output impedance ZO — 150 — Ω — Offset level VOS — 6.5 — V Note 11 Notes 1) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) W lamp (2854K) 4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT = 500mV (Typ.) PRNU = (VMAX – VMIN) /2 VAVE × 100 [%] Where the 5150 pixels are divided into blocks of even and odd pixels, respectively. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 5) Use below the minimum value of the saturation output voltage. 6) Saturation exposure is defined as follows. SE = VSAT/R1 7) RI is defined as indicated bellow. VOUT = 500mV (Typ.) RI = | VODD-AVE – VEVEN-AVE | × 100 [%] VODD-AVE + VEVEN-AVE 2 ( ) Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE. 8) Optical signal accumulated time τ int stands at 10ms. 9) The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms. –3– ILX531A 10) VOUT = 500 mV (Typ.) 11) VOS is defined as indicated bellow. VOUT AA AAA AAA AA AAAAA VOS GND –4– –5– VOUT-EVEN VOUT-ODD φCLP-ODD φCLP-EVEN 0 AAAAAAAA A AA AAAAAA AA D27 D28 D25 D26 D23 D24 D5 D6 D3 D4 D1 D2 1-line output period (5244 pixels) Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles. Dummy signal (74 pixels) Optical black (48 pixels) D69 D70 5 D71 D72 0 D73 D74 5 S1 S2 φRS-ODD φRS-EVEN S3 S4 0 S5145 S5146 5 S5147 S5148 φ2-ODD φ2-EVEN S5149 S5150 0 D75 D76 5 D77 D78 φ1-ODD φ1-EVEN φLH-ODD φLH-EVEN 1 D79 D80 0 2 D81 D82 5 3 D83 D84 φROG D93 D94 Clock Timing Chart 1 (simultaneous output) ILX531A 2622 ILX531A Clock Timing Chart 2 t5 t4 φROG t2 t6 φ1 φLH t7 t3 t1 φ2 Clock Timing Chart 3 t7 t6 φ1 φLH φ2 t10 t11 t9 φRS t8 t14 t15 t13 φCLP t12 AAAAAAAAA AAAAAAAAA t16 VOUT t17 AA AA Clock timing of φ1, φ2, φLH, φRS, φCLP and VOUT at odd or even are the same as timing chart 3 in the case of alternate output. –6– ILX531A Clock Timing Chart 4 Cross point φ1 and φ2 φ1 5V 1.5V (Min.) 1.5V (Min.) 2.0V (Min.) 0.5V (Min.) φ2 0V Cross point φLH and φ2 φ2 5V φLH 0V –7– 0 0 5 5 0 5 0 5 D83 D81 D79 D77 D75 S5149 S5147 S5145 S3 S1 D73 D70 D71 D69 D28 D26 D27 D24 D25 D23 1-line output period (5244 pixels) Optical black (48 pixels) Dummy signal (74 pixels) AAAAA AA A A AA AA AA AA A A AA AAA AA A AA D93 3 D6 2 D5 D4 1 D3 D2 D1 Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles. ∗ Alternate output is available by making φ1-EVEN, φ2-EVEN, φLH-EVEN, φRS-EVEN, φCLP-EVEN delayed to φ1-ODD, φ2-ODD, φLH-ODD, φRS-ODD, φCLP-ODD for half a cycle. VOUT-EVEN φCLP-EVEN φRS-EVEN VOUT-ODD φCLP-ODD φRS-ODD 0 5 D72 φ2-EVEN D74 5 φ1-EVEN φLH-EVEN 0 S2 0 S4 5 S5146 φ2-ODD S5148 0 S5150 5 D76 φ1-ODD φLH-ODD D78 0 D80 5 D82 –8– D84 φROG 2622 D94 Clock Timing Chart 5 (alternate output∗) ILX531A ILX531A Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 — ns φROG pulse high level period t2 600 1000 — ns φROG, φ1 pulse timing t3 400 1000 — ns φROG pulse rise time t4 0 5 10 ns φROG pulse fall time t5 0 5 10 ns φ1 pulse rise time/φ2 pulse fall time t6 0 20 60 ns φ1 pulse fall time/φ2 pulse rise time t7 0 20 60 ns φRS pulse high level period t8 10 — ns φRS, φCLP pulse timing t9 10 200∗1 200∗1 — ns φRS pulse rise time t10 0 10 30 ns φRS pulse fall time t11 0 10 30 ns φCLP pulse high level period t12 10 200∗1 — ns φCLP, φLH pulse timing t13 5 50∗1 — ns φCLP pulse rise time t14 0 10 30 ns φCLP pulse fall time t15 0 10 30 ns t16 — 8 — ns t17 — 15 — ns Signal output delay time ∗1 These timing is the recommended condition under fφ1 = 1MHz. –9– – 10 – φRS ∗ Data rate fφR = 2MHz. φCLP 100Ω φLH 100Ω 2Ω 2 φCLP-EVEN φCLP-ODD 100Ω φRS-EVEN φRS-ODD 1 GND 6 VOUT-ODD 5 5.1kΩ 7 VGG Tr1 GND 2Ω φ2 φ1 9 10 φROG 11 IC1 47µF/16V IC1 : 74AC04 Tr1 : 2SC2785 0.1µF 12V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. VOUT-ODD IC1 4 100Ω φLH-EVEN φLH-ODD 0.1µF VDD 8 VOUT-EVEN 3 18 12 17 VDD 19 13 16 NC 20 14 15 φ2-EVEN 21 φ2-ODD VOUT-EVEN GND φ1-ODD VDD Tr1 φ1-EVEN 22 100Ω 5.1kΩ VDD φROG Application Circuit ∗ (simultaneous output) ILX531A ILX531A Example of Representative Characteristics Spectral sensitivity characteristics (Standard characteristics) 1.0 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 500 600 700 800 Wavelength [nm] Dark signal output temperature characteristics (Standard characteristics) 900 1000 Integration time output voltage characteristics (Standard characteristics) 10 Output voltage rate Output voltage rate 5 1 0.5 0.1 0 10 20 30 40 50 Ta – Ambient temperature [°C] 1 0.5 0.1 60 Offset level vs. VDD characteristics (Standard characteristics) 1 ∆VOS ∆Ta Ta = 25°C VOS – Offset level [V] VOS – Offset level [V] 10 8 6 4 –2mV/°C 8 6 4 0.6 2 0 11.4 10 Offset level vs. Temperature characteristics (Standard characteristics) 10 ∆VOS ∆VDD 5 τ int – integration time [ms] 2 12.0 VDD [V] 0 12.6 – 11 – 0 10 20 30 40 50 Ta – Ambient temperature [°C] 60 ILX531A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Packages The following points should be observed when handling and installing packages. a) Remain within the following limits when applying static load to the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm , , Cover glass 0.9Nm ,, ,, ,, ,, Plastic portion 39N 29N 29N Adhesive Ceramic portion (1) (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the package to crack or dust to be generated. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer. (5) Applying the metal a crash or a rub against the plastic portion. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. d) The notch of the plastic portion is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap with the notch of the plastic portion. – 12 – ILX531A 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 13 – 5.0 ± 0.3 – 14 – V H 11.12 ± 0.3 1 Plastic, Ceramic GOLD PLATING 42ALLOY 5.43g LS-B20-01(E) PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS DRAWING NUMBER 2.54 0.3 53.0 M 0.51 36.05(7µmX5150pixels) 55.7 ± 0.3 22pin DIP(400mil) No.1 Pixel 22 PACKAGE STRUCTURE 4.0 ± 0.5 Unit: mm 11 12 7.3 (AT STAND OFF) 10.16 10.0 ± 0.3 3.58 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm. 4.28 ± 0.5 0˚to 9˚ 0.25 Package Outline ILX531A