SONY ILX724K

ILX724K
2700 × 3pixel CCD Linear Sensor (Color)
For the availability of this product, please contact the sales office.
Description
The ILX724K is a reduction type CCD linear sensor
developed for color image scanner, and has shutter
function per each color. This sensor reads A4-size
documents at a density of 300 DPI.
22 pin DIP (Cer-DIP)
Features
• Number of effective pixels: 8100 pixels
(2700 pixels × 3)
• Pixel size:
8µm × 8µm (8µm pitch)
• Distance between line:
64µm (8 Lines)
• Single-sided readout
• Shutter function
• Ultra low lag / High sensitivity
• Single 12V power supply
• Input clock pulse:
CMOS 5V drive
• Number of output
3 (R, G, B)
• Package:
22 pin cer-DIP (400 mil)
9
14 φSHUT-B
2700
2700
17
5
20
8
φ1
Driver
Driver
Shutter Gate
Red
Shutter Gate
S2700
Shutter Gate
Shutter Drain
φ2
φLH
VOUT-B 21
13 φROG-B
2700
GND 11
VDD
1
B
1
G
1
R
φROG-R 10
GND
φSHUT-G
φRS
15 φ2
GND
8
4
φ1
3
16 VDD
2
7
Driver
φSHUT-R
Read Out Gate S2700
17 NC
CCD Register
6
VOUT-R 1
NC
Shutter Drain
18 NC
CCD Register Read Out Gate S2700
5
VOUT-G 22
GND
Green
19 NC
Shutter Drain
4
CCD Register Read Out Gate
φLH
Driver
AAAAAA
AA
AAAAAA
AA
AAAAAA
AA
15
16
VDD
Blue
20 VDD
D14
D15
3
D14
D15
φRS
D14
D15
21 VOUT-B
D63
S1
2
D63
S1
GND
22 VOUT-G
D63
S1
D64
1
D64
VOUT-R
D64
D75
Pin Configuration (Top View)
D75
V
°C
°C
D75
Absolute Maximum Ratings
• Supply voltage
VDD
15
• Operating temperature
–10 to +55
• Storage temperature
–30 to +80
φ2
11
GND
10 φROG-R
φSHUT-R
9 φSHUT-G
Driver
7
13 φROG-B
Driver
12 φROG-G
14 φSHUT-B
Driver
Block Diagram
12 φROG-G
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96542-ST
ILX724K
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
VOUT-R
Signal out (red)
12
φROG-G
Clock pulse input
2
GND
GND
13
φROG-B
Clock pulse input
3
φRS
Clock pulse input
14
φSHUT-B
Clock pulse input
4
φLH
Clock pulse input
15
φ2
Clock pulse input
5
GND
GND
16
VDD
12V power supply
6
NC
NC
17
NC
NC
7
φSHUT-R
Clock pulse input
18
NC
NC
8
φ1
Clock pulse input
19
NC
NC
9
φSHUT-G
Clock pulse input
20
VDD
12V power supply
10
φROG-R
Clock pulse input
21
VOUT-B
Signal out (blue)
11
GND
GND
22
VOUT-G
Signal out (green)
Recommended Supply Voltage
Item
Min.
Typ.
Max.
Unit
VDD
11.4
12
12.6
V
Clock Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacity of φ1, φ2
Cφ1, Cφ2
—
400
—
pF
Input capacity of φLH
CφLH
—
10
—
pF
Input capacity of φRS
CφRS
—
10
—
pF
CφROG
—
10
—
pF
CφSHUT
—
10
—
pF
Input capacity of φROG∗1
Input capacity of φSHUT∗1
∗1 It indicates that φROG-R, φROG-G, φROG-B as φROG, φSHUT-R, φSHUT-G, φSHUT-B as φSHUT.
Clock Frequency
Item
Symbol
φ1, φ2, φLH, φRS
Min.
Typ.
Max.
Unit
—
1
5
MHz
fφ1, fφ2, fφLH, fφRS
Input Clock Pulse Voltage Condition
Item
φ1, φ2, φLH, φRS, φROG,
φSHUT pulse voltage
Min.
Typ.
Max.
Unit
High level
4.75
5.0
5.25
V
Low level
—
0
0.1
V
–2–
ILX724K
Electrooptical Characteristics (Note 1)
Ta = 25°C, VDD = 12V, fφRS = 1MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
V/(lx · s)
Note 2
Red
RR
1.3
2.0
2.7
Green
RG
2.1
3.2
4.3
Blue
RB
1.6
2.5
3.4
Sensitivity nonuniformity
PRNU
—
4
20
%
Note 3
Saturation output voltage
VSAT
2
3.2
—
V
Note 4
Red
SER
0.74
1.6
—
Green
SEG
0.46
1
—
lx · s
Note 5
Blue
SEB
0.58
1.28
—
Dark voltage average
VDRK
—
0.3
2
mV
Note 6
Dark signal nonuniformity
DSNU
—
1.5
5
mV
Note 6
Image lag
IL
—
0.02
—
%
Note 7
Supply current
IVDD
—
26
50
mA
—
Total transfer efficiency
TTE
92
98
—
%
—
Output impedance
ZO
—
250
—
Ω
—
Offset level
VOS
—
6.5
—
V
Note 8
Dynamic range
DR
1000
10670
—
—
Note 9
Sensitivity
Saturation
exposure
Note
1) In accordance with the given electrooptical characteristics, the black level is defined as the average value
of D2, D3 to D12.
2) For the sensitivity test light is applied with a uniform intensity of illumination.
3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT-G = 500mV (Typ.)
PRNU =
(VMAX – VMIN) /2
VAVE
× 100 [%]
Where the 2700 pixels are divided into blocks of 100. The maximum output of each block is set to VMAX,
the minimum output to VMIN and the average output to VAVE.
4) Use below the minimum value of the saturation output voltage.
5) Saturation exposure is defined as follows.
SE =
VSAT
R
Where R indicates RR, RG, RB, and SE indicates SER, SEG, SEB.
6) Optical signal accumulated time τ int stands at 10ms.
7) VOUT-G = 500mV (Typ.)
VOUT
8) Vos is defined as indicated bellow.
VOUT indicates VOUT-R, VOUT-G, and VOUT-B.
9) Dynamic range is defined as follows.
DR =
VSAT
VDRK
AA
AA
AAAA
VOS
GND
When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical
signal accumulated time is in proportion to the dark voltage.
–3–
–4–
VOUT
φRS
φ2
φ1
φLH
φROG
D3
D2
3
D1
2
1
VOUT indicates VOUT-R, VOUT-G, VOUT-B.
AAAAAAA A
D62
D15
D14
D13
4
Dummy signal (63 pixels)
S2699
S2698
S2
S1
D63
1-line output period (2775 pixels)
Optical black (49 pixels)
D61
Note) The transfer pulses (φ1, φ2, φLH) must have more than 2775 cycles.
0
5
0
5
0
5
0
5
Clock Timing Chart 1
ILX724K
D75
2775
D71
D70
D65
D64
S2700
ILX724K
Clock Timing Chart 2
t4
t5
φROG
t2
t7
t6
φ1
t1
t3
φ2
Clock Timing Chart 3
t7
t6
φ1
φLH
φ2
t10
t11
t9
φRS
t8
AAAAAAAA
AAAAAAAA
AAAAAAAA
t13
VOUT
t12
–5–
AAA
AAA
AAA
–6–
0
5
0
5
0
5
0
5
4
3
1
Note) Shutter pulse must not be low level during from 2 to 2775 of φ1.
φSHUT
φRS
φ2
φ1
φLH
φROG
2
Clock Timing Chart 4 (Shutter Operation)
Integration Time
ILX724K
2775
ILX724K
Clock Pulse Recommended Timing
Item
Symbol
φROG, φ1 pulse timing
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
φROG pulse high level period
φROG, φ1 pulse timing
φROG pulse rise time
φROG pulse fall time
φ1 pulse rise time /φ2 pulse fall time
φ1 pulse fall time /φ2 pulse rise time
φRS pulse high level period
φRS, φLH pulse timing
φRS pulse rise time
φRS pulse fall time
Signal output delay time
∗1 These timing is the recommended condition under fφRS = 1MHz.
–7–
Min.
Typ.
Max.
Unit
50
100
—
ns
800
1000
—
ns
800
1000
—
ns
0
5
10
ns
0
5
10
ns
0
20
60
ns
0
20
60
ns
—
ns
—
ns
45
250∗1
250∗1
0
10
30
ns
0
10
30
ns
—
10
—
ns
—
10
—
ns
45
–8–
Tr1
47µF/16V
∗ Data rate fφRS = 1MHz
0.1µF
12V
VOUT-G
Tr1
2
1
100Ω
100Ω
φLH
4
φSHUT-R
7
6
2Ω
φ1
8
φSHUT-G
9
φROG-R
10
IC1
11
IC1
IC1: 74AC04
Tr1: 2SC2785
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
φRS
3
5
12
13
14
15
16
17
φROG-G
18
φROG-B
19
2Ω
φSHUT-B
20
Tr1
VOUT-B
φ2
21
100Ω
5.1kΩ
22
5.1kΩ
100Ω
100Ω
VOUT-R
5.1kΩ
VOUT-G
VOUT-R
VOUT-B
GND
VDD
φRS
NC
φLH
NC
GND
NC
NC
VDD
φSHUT-R
φ2
φ1
φSHUT-B
φSHUT-G
φROG-B
φROG-R
φROG-G
GND
Application Circuit∗
ILX724K
ILX724K
Example of Representative Characteristics (VDD = 12V, Ta = 25°C)
Spectral sensitivity characteristics (Standard characteristics)
1
Relative sensitivity
0.8
0.6
0.4
0.2
0
400
450
500
550
600
650
700
Wavelength [nm]
Dark signal output temperature characteristics
(Standard characteristics)
Integration time output voltage characteristics
(Standard characteristics)
10
Output voltage rate
Output voltage rate
5
1
0.5
0.1
1
0.5
0.1
0
10
20
30
40
50
60
1
5
10
Ta – Ambient temperature [°C]
τ int – Integration time [ms]
Offset level vs. VDD characteristics
(Standard characteristics)
Offset level vs. temperature characteristics
(Standard characteristics)
12
12
Ta = 25°C
10
VOS – Offset level [V]
VOS – Offset level [V]
10
8
6
∆VOS
∆VDD
4
0.3
2
0
11.4
8
6
∆VOS
∆Ta
4
–0.5mV/°C
2
0
12
12.6
0
VDD [V]
10
20
30
40
50
Ta – Ambient temperature [°C]
–9–
60
ILX724K
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Cer-DIP Packages
The following points should be observed when handling and installing cer-DIP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:
(1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of
the glass portion.)
(2) Shearing strength: 29N/surface
(3) Tensile strength: 29N/surface
(4) Torsional strength: 0.9Nm
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
AAAA
AAAA
AAAA
AAAA
AAAA AAAA AAAA AAAA
Upper ceramic layer
39N
lower ceramic layer
(1)
Low-melting glass
29N
29N
(2)
(3)
0.9Nm
(4)
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic
layers are shielded by low-melting glass,
(1) Applying repetitive bending stress to the external leads.
(2) Applying heat to the external leads for an extended period of time with soldering iron.
(3) Rapid cooling or heating.
(4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as
tweezers.
(5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass.
Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric
desoldering tool, ground the controller. For the control system, use a zero cross type.
– 10 –
ILX724K
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch
the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
– 11 –
5.0 ± 0.5
– 12 –
1
V
22
H
6.53 ± 0.8
21.6 (8µm × 2700Pixels)
2.54
Cer-DIP
TIN PLATING
42 ALLOY
3.0g
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
30.6
No.1 Pixel (Green)
PACKAGE STRUCTURE
4.0 ± 0.5
32.0 ± 0.5
11
12
0.51
9.0
2.7
10.0 ± 0.5
0.3
M
0° to 9°
0.25
(AT STAND OFF)
10.16
2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm.
Package Outline
3.5 ± 0.5
22pin DIP (400mil)
ILX724K
Unit: mm