ILX569K 5340-pixel × 6 line CCD Linear Sensor (Color) Description The ILX569K is a reduction type CCD linear sensor developed for color image scanner. This sensor reads A4-size documents at a density of 600 DPI and 1200 DPI. 22 pin DIP (Plastic) Sensor Line Features • Number of effective pixels: 32040 pixels (5340 pixels × 6) • Pixel size: 4µm × 4µm (4µm pitch) • Distance between main line: 48µm (12 lines) • Distance between main line and sub line: 8µm (2 lines) Common Features • Single-sided readout • Ultra low lag • Single 12V power supply • Maximum data rate: 8MHz/Color • Input clock pulse: CMOS 5V drive • Number of output: 3 (R, G, B) • Package: 22 pin Plastic-DIP (400mil) Absolute Maximum Ratings • Supply voltage VDD 15 –10 to +55 • Operating temperature V °C Sensor Configuration Pin Configuration (Top View) 1 VDD 3 20 φRS VOUT-R 4 19 GND VOUT-B 5 18 VOUT-G NC 6 NC 7 NC 8 15 φ1 NC 9 14 φ2 B (main) 5340 B (sub) 5340 G (main) 5340 R (main) R (sub) G (sub) 5340 5340 φROG-R 11 5340 φROG-G 10 1 21 φ4 1 2 1 φ3 1 22 φL2 1 1 1 φL1 3 2 1 17 NC 5 4 3 2 7 8 6 5 4 Blue 7 Green 8 6 Blue 48µm 16 NC Green 48µm 13 φROG-B 12 NC 4µm 1 3 5 Red 8µm 7 4µm 4µm 2 4 6 8 Red 4µm Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01750A27 Block Diagram S5340 Main Line (Green) D75 Readout Gate S3 CCD Register S2 Readout Gate D106 D106' Driver 13 φROG-B Driver 10 φROG-G Driver 11 φROG-R D106 Sub Line (Blue) D75' S5340 D75 S5340' S2 S3 S3' S2' D74 S1 D74' S1' Main Line (Blue) CCD Register D74 S1 D31 14 S5340 Main Line (Red) D75 S3 Readout Gate S2 CCD Register D106' D106 D75' S5340' S3' S2' D74' S1' Readout Gate CCD Register 20 φRS 2 21 1 22 φ3 φ4 φL1 φL2 D106' D75' Sub Line (Red) S5340' S3' S2' 4 D74' S1' VOUT-R Sub Line (Green) CCD Register D74 S1 D31 D31' VOUT-G 18 D31' –2– D31 D31' 5 φ2 3 Readout Gate CCD Register VOUT-B VDD Readout Gate 19 15 GND φ1 ILX569K ILX569K Pin Description Pin No. Symbol Pin No. Description Symbol Description 1 φL1 Clock pulse input 12 NC NC 2 φ3 Clock pulse input 13 φROG-B Clock pulse input 3 VDD 12V power supply 14 φ2 Clock pulse input 4 VOUT-R Signal output (red) 15 φ1 Clock pulse input 5 VOUT-B Signal output (blue) 16 NC NC 6 NC NC 17 NC NC 7 NC NC 18 VOUT-G Signal output (green) 8 NC NC 19 GND GND 9 NC NC 20 φRS Clock pulse input 10 φROG-G Clock pulse input 21 φ4 Clock pulse input 11 φROG-R Clock pulse input 22 φL2 Clock pulse input Recommended Supply Voltage Item VDD Min. Typ. Max. Unit 11.4 12 12.6 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φ1, φ2 Cφ1, Cφ2 — 1500 — pF Input capacity of φRS CφRS — 10 — pF Input capacity of φROG CφROG — 10 — pF Input capacity of φ3, φ4, φL1, φL2 CφL1, CφL2, Cφ3, Cφ4 — 20 — pF Clock Frequency Item Symbol Min. Typ. Max. Unit φ1, φ2, φL1, φL2 fφ1, fφ2, fφL1, fφL2 — 0.5 8 MHz φ3, φ4, φRS fφ3, fφ4, fφRS — 1 8 MHz Min. Typ. Max. Unit High level 4.75 5.0 5.25 V Low level — 0 0.1 V Input Clock Pulse Voltage Condition Item φ1, φ2, φRS, φROG, φL1, φL2, φ3, φ4 pulse voltage –3– ILX569K Electrooptical Characteristics (Note 1) (Ta = 25°C, VDD = 12V, fφRS = 1MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Item Symbol Min. Typ. Max. Unit Remarks Red RR 1.3 1.8 2.3 Green RG 1.2 1.7 2.2 V/(lx · s) Note 2 Blue RB 0.8 1.2 1.6 Sensitivity nonuniformity PRNU — 4 20 % Note 3 Saturation output voltage VSAT 1.8 2.0 — V Note 4 Red SER — 1 — Green SEG — 1 — lx · s Note 5 Blue SEB — 1.64 — Dark voltage average VDRK — 0.1 1.6 mV Dark signal nonuniformity DSNU — 0.5 3.2 mV Image lag IL — 0.02 — % Note 7 Supply current IVDD — 30 45 mA Note 8 Total transfer efficiency TTE 92 98 — % Output impedance ZO — 360 — Ω Offset level VOS — 5.7 — V Sensitivity Saturation exposure Note 6 Note 9 Notes: 1. In accordance with the given electrooptical characteristics, the black level of 1200 DPI is defined as the average value of D32, D33 to D73. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT = 500mV (typ.) PRNU = (VMAX – VMIN)/2 × 100 [%] VAVE 4. Use below the minimum value of the saturation output voltage. 5. Saturation exposure is defined as follows. SE = 6. 7. 8. 9. VSAT R Where R indicates RR, RG, RB and SE indicates SER, SEG, SEB. Optical signal accumulated time τ int stands at 4ms. VOUT-G = 500mV (typ.) Supply current means the total current of this device. Vos is defined as indicated bellow. VOUT indicates VOUT-R, VOUT-G, and VOUT-B. VOUT VOS GND –4– Clock Timing Chart 1 φROG 1200 DPI 5 φ1, φL1 φ2, φL2 2 5 1 0 0 5 φ3 4 3 2 5 1 0 0 φ4 5 0 5 D106' D82' D82 D81' D81 D80' D80 D79' D79 D78' D75' D75 S5340' S5340 S5339' S1' S1 D74' D74 D32' D32 D31' D31 D2 VOUT D1' 0 D1 –5– φRS Optical black (42 pixels × 2) Dummy signal (74 pixels × 2) Effective pixels signal (5340 pixels × 2) Dummy signal (32 pixels × 2) 1-line output period (5446 pixels × 2) ILX569K Note) The transfer pulses (φ1, φ2) must have more than 5446 cycles. The transfer pulses (φ3, φ4) must have more than 10892 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. Clock Timing Chart 2 φROG 600 DPI 5 4 0 5 0 D87 D86 S10680 S10679 S2 S1 D85 D84 D83 D44 D43 0V D1 –6– φL1 5 D42 φRS 0 D3 φ2, φ4, φL2 5 D2 φ1, φ3 3 1 2 0 VOUT Optical black (42 pixels) Dummy signal (85 pixels) Effective pixels signal (5340 pixels) Dummy signal (more than 80 clocks) 1-line output period (5505 pixels) ILX569K Note) The transfer pulses (φ1, φ2) must have more than 5505 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. ILX569K Clock Timing Chart 3 t5 t4 φROG t2 t6 φ1 t7 t1 t3 φ2 t6 t7 ClockTiming Chart 4 t7 t6 t6 t7 t9 t8 t8 t9 φ1 φ2 φL1 φL2 t15 t11 t10 φ3 φ4 t10 t11 t12 t13 t16 φRS t14 t17 VOUT t18 Sub Line Main Line –7– ILX569K Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 — ns φROG pulse high level period t2 5000 6000 — ns φROG pulse high level period t3 1200 1500 — ns φROG pulse rise time t4 0 5 10 ns φROG pulse fall time t5 0 5 10 ns φ1 pulse rise time/φ2 pulse fall time t6 0 50 80 ns φ1 pulse fall time/φ2 pulse rise time t7 0 50 80 ns φL1 pulse rise time/φL2 pulse fall time t8 0 10 30 ns φL1 pulse fall time/φL2 pulse rise time t9 0 10 30 ns φ3 pulse rise time/φ4 pulse fall time t10 0 10 30 ns φ3 pulse fall time/φ4 pulse rise time t11 0 10 30 ns φRS pulse rise time t12 0 10 30 ns φRS pulse fall time t13 0 30 ns φRS pulse high level period t14 60 10 120∗1 — ns φL1, φL2 and φ3 pulse timing t15 0 — ns φRS, φ3 pulse timing t16 60 10 250∗1 — ns t17 — 40 — ns t18 — 20 — ns Signal output delay time ∗1 These timing data is the recommended condition under fφRS = 1MHz. –8– ILX569K Application Circuit∗1 <IC1> φ4 φL2 φRS Tr1 IC2 φ1 φ2 IC1 IC1 VOUT-G 100Ω 2Ω 100Ω 100Ω 3kΩ 2Ω 13 VOUT-G NC NC φ1 φ2 φROG-B NC NC NC NC NC φROG-G φROG-R 12 VOUT-B 14 GND 15 VOUT-R 16 φRS 17 VDD 18 φ4 19 φ3 20 φL2 12V 21 100Ω 2Ω φL1 22 0.1µF φROG-B 1 2 3 4 5 6 7 8 9 10 11 47µF/ 16V 100Ω 100Ω 3kΩ 2Ω 100Ω VOUT-R Tr1 IC2 IC2 3kΩ 100Ω φROG-G φROG-R VOUT-B φL1 100Ω φ3 Tr1 IC1: 74HC04 × 3pcs IC2: 74HC04 Tr1: 2SA1175 ∗1 Data rate fφRS = 1MHz Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– ILX569K Example of Representative Characteristics Spectral sensitivity characteristics (Standard characteristics) 1.0 R 0.9 0.8 Relative sensitivity 0.7 G B 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wavelength [nm] – 10 – 800 900 1000 ILX569K Notes on Handling 1. Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2. Notes on handling CCD packages The following points should be observed when handling and installing packages. a) Remain within the following limits when applying a static load to the package. (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Cover glass Plastic portion 39N Ceramic portion (1) Adhesive 29N 29N (2) (3) 0.9Nm (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the packege to crack or dust to be generated. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer. (5) Applying the metal a crash or a rub against the plastic portion. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3. Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnance causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero-cross type. – 11 – ILX569K 4. Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5. Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 12 – Package Outline Unit: mm 22pin DIP (400mil) 6.2 ± 0.3 0˚ to 9˚ 32.0 ± 0.3 21.360 (5340Pixels) 12 V No.1Pixel (Blue Main) 10.16 10.0 ± 0.3 5.0 ± 0.3 22 H 11 0.25 1 ( 2.9 ) 2.8 ± 0.5 2.1 4.0 ± 0.5 – 13 – 2.54 0.51 1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. PACKAGE STRUCTURE Plastic,Ceramic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 2.21g DRAWING NUMBER LS-D18(E) M ILX569K Sony Corporation PACKAGE MATERIAL 0.3