ILX533K 2700 pixel × 3 line CCD Linear Sensor (Color) For the availability of this product, please contact the sales office. Description The ILX533K is a reduction type CCD linear sensor developed for color image scanner. The distance between lines is only 4 line (32µm). This sensor reads A4-size documents at a density of 300DPI. 16 NC NC 8 15 NC NC 9 14 φ2 Blue 1 Driver 13 φROG-R 12 φROG-G S2700 S2700 Clamp Pulse Generator A A A A A A AA AA VOUT-G 3 VOUT-R 2 4 VDD B 2700 2700 VOUT-B 20 1 1 2700 Clamp Clamp 13 φROG-R Clamp G D14 D15 R D63 S1 φ1 10 φ1 7 10 NC 1 17 NC φRS 6 21 NC GND 18 NC Driver 5 Read Out Gate NC CCD Register 19 NC Red 4 Read Out Gate VDD CCD Register 20 VOUT-B Green 3 φROG-B 11 Driver 11 φROG-B Driver 14 φ2 S2700 VOUT-G Read Out Gate 21 GND CCD Register 2 D14 D15 VOUT-R 22 GND S1 1 D63 φRS D14 Pin Configuration (Top View) D15 V °C °C S1 Absolute Maximum Ratings 15 • Supply voltage VDD • Operating temperature –10 to +55 • Storage temperature –30 to +80 Block Diagram D63 Features • Number of effective pixels: 8100 pixels (2700 pixels × 3) • Pixel size: 8µm × 8µm (8µm pitch) • Distance between line: 32µm (4 Lines) • Number of output 3 (R, G, B) • Single-sided readout • Clamp circuit are on-chip • Ultra high sensitivity/Ultra low lag • Single 12V power supply • Maximum data rate: 9MHz (3MHz × 3) • Input Clock Pulse: CMOS 5V drive • Package: 22 pin cer-DIP (400 mil) 22 pin DIP (Cer-DIP) 12 φROG-G Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97406B79-PS ILX533K Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 φRS Clock pulse input 12 φROG-G Clock pulse input 2 VOUT-R Signal out (red) 13 φROG-R Clock pulse input 3 VOUT-G Signal out (green) 14 φ2 Clock pulse input 4 VDD 12V power supply 15 NC NC 5 NC NC 16 NC NC 6 NC NC 17 NC NC 7 NC NC 18 NC NC 8 NC NC 19 NC NC 9 NC NC 20 VOUT-B Signal out (blue) 10 φ1 Clock pulse input 21 GND GND 11 φROG-B Clock pulse input 22 GND GND Recommended Supply Voltage Item Min. Typ. Max. Unit VDD 11.4 12 12.6 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φ1, φ2 Cφ1, Cφ2 — 400 — pF Input capacity of φRS CφRS — 10 — pF Input capacity of φROG∗1 CφROG — 10 — pF ∗1 It indicates that φROG-R, φROG-G, φROG-B as φROG. Clock Frequency Item Symbol φ1, φ2, φRS fφ1, fφ2, fφRS Min. Typ. Max. Unit — 1 3 MHz Input Clock Pulse Voltage Condition Item φ1, φ2, φRS, φROG pulse voltage Min. Typ. Max. Unit High level 4.75 5.0 5.25 V Low level — 0 0.1 V –2– ILX533K Electrooptical Characteristics (Note 1) Ta = 25°C, VDD = 12V, fφRS = 1MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm) Item Symbol Min. Typ. Max. Unit Remarks V/(lx · s) Note 2 Red RR 6.2 9.5 12.8 Green RG 12.3 19 25.6 Blue RB 7.5 11.5 15.5 Sensitivity nonuniformity PRNU — 4 20 % Note 3 Saturation output voltage VSAT 2.0 2.5 — V Note 4 Red SER 0.15 0.26 — Green SEG 0.10 0.13 — lx · s Note 5 Blue SEB 0.12 0.21 — Dark voltage average VDRK — 2 5 mV Note 6 Dark signal nonuniformity DSNU — 4 12 mV Note 6 Image lag IL — 0.02 — % Note 7 Supply current IVDD — 30 50 mA — Total transfer efficiency TTE 92 98 — % — Output impedance ZO — 300 — Ω — Offset level VOS — 6.3 — V Note 8 Sensitivity Saturation exposure Note 1) In accordance with the given electrooptical characteristics, the black level is defined as the average value of D2, D3 to D12. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT-G = 500mV (Typ.) PRNU = (VMAX – VMIN) /2 VAVE × 100 [%] Where the 2700 pixels are divided into blocks of 100. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4) Use below the minimum value of the saturation output voltage. 5) Saturation exposure is defined as follows. SE = VSAT R Where R indicates RR, RG, RB, and SE indicates SER, SEG, SEB. 6) Optical signal accumulated time τ int stands at 5ms. 7) VOUT-G = 500mV (Typ.) VOUT 8) Vos is defined as the right side. VOUT indicates VOUT-R, VOUT-G, and VOUT-B. AA AA AAAA VOS GND –3– VOUT φRS φ2 φ1 φROG 0 5 0 5 0 5 0 5 AAAAAA D62 D61 D15 D14 –4– D13 4 D3 D2 3 D1 2 1 S2 S1 D63 1-line output period Noto) The transfer pulses (φ1, φ2) must have more than 2770 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. Dummy signal (63 pixels) Optical black (49 pixels) 2770 D70 Clock Timing Chart 1 ILX533K D65 D64 S2700 S2699 S2698 ILX533K Clock Timing Chart 2 t4 t5 φROG t2 t6 t7 φ1 t1 t3 φ2 Clock Timing Chart 3 t7 t6 φ1 φ2 t14 t10 t11 t9 φRS t8 t13 VOUT AAAAAAAA AAAAAAAA AAAAAAAA t12 –5– AAA AAA AAA ILX533K Clock Pulse Recommended Timing Symbol Item Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 — ns φROG pulse high level period t2 800 1000 — ns φROG, φ1 pulse timing t3 800 1000 — ns φROG pulse rise time t4 0 5 10 ns φROG pulse fall time t5 0 5 10 ns φ1 pulse rise time/φ2 pulse fall time t6 0 20 60 ns φ1 pulse fall time/φ2 pulse rise time t7 0 20 60 ns φRS pulse high level period t8 50 — ns φRS, φ1 pulse timing 1 t9 80 250∗1 250∗1 — ns φRS pulse rise time t10 0 10 30 ns φRS pulse fall time t11 0 10 30 ns t12 — 70 — ns t13 — 10 — ns t14 50 250∗1 — ns Signal output delay time φRS, φ1/φ2 pulse timing 2 ∗1 These timing is the recommended condition under fφRS = 1MHz. –6– 0.1µF 47µF/16V IC1 ∗ Data rate fφRS = 1MHz 12V φRS VOUT-R 5.1kΩ 100Ω Tr1 2 1 5.1kΩ VOUT-G 100Ω 4 7 6 8 9 2Ω φ1 10 φROG-B 11 IC1 IC1 IC1: 74AC04 Tr1: 2SC2785 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Tr1 3 5 12 13 14 15 16 17 18 19 20 φROG-G 21 2Ω φROG-R 22 100Ω Tr1 VOUT-B φ2 GND 5.1kΩ GND φRS VOUT-B VOUT-R NC VOUT-G NC VDD NC NC NC NC –7– NC NC NC φ2 NC φROG-R φ1 φROG-G φROG-B Application Circuit∗ ILX533K ILX533K Example of Representative Characteristics (VDD = 12V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 1 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 450 500 550 600 650 700 Wavelength [nm] Dark signal output temperature characteristics (Standard characteristics) Integration time output voltage characteristics (Standard characteristics) 10 Output voltage rate Output voltage rate 5 1 0.5 0.1 1 0.5 0.1 0 10 20 30 40 50 60 1 5 10 Ta – Ambient temperature [°C] τ int – Integration time [ms] Offset level vs. VDD characteristics (Standard characteristics) Offset level vs. temperature characteristics (Standard characteristics) 12 12 Ta = 25°C 10 VOS – Offset level [V] VOS – Offset level [V] 10 8 6 ∆VOS ∆VDD 4 0.6 2 0 11.4 8 6 ∆VOS ∆Ta 4 +0.5mV/°C 2 0 12 12.6 0 VDD [V] 10 20 30 40 50 Ta – Ambient temperature [°C] –8– 60 ILX533K Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Upper ceramic layer 39N lower ceramic layer (1) Low-melting glass 29N 29N (2) (3) 0.9Nm (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. –9– ILX533K 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 10 – 5.0 ± 0.5 – 11 – 1 V 22 H 5.8 ± 0.8 21.6 (8µm × 2700Pixels) 32.0 ± 0.5 2.54 Cer-DIP TIN PLATING 42 ALLOY 3.0g PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 30.6 No.1 Pixel (Green) PACKAGE STRUCTURE 4.0 ± 0.5 11 12 0.51 22pin DIP (400mil) 9.0 2.7 Unit: mm 10.0 ± 0.5 0.3 3.4 ± 0.5 Package Outline M 0° to 9° 0.25 (AT STAND OFF) 10.16 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm. ILX533K