ILX734LA 10500 × 3 pixel CCD Linear Sensor (Color) For the availability of this product, please contact the sales office. Description The ILX734LA is a reduction type CCD linear sensor developped for color image scanner, and has shutter function per each color. This sensor reads A4-size documents at a density of 1200 DPI. 7 50 φ2 φROG-R 26 25 Read Out Gate Green 7 Shutter Drain φ1 Driver Driver Driver Driver Driver Driver Read Out Gate CCD Register Blue Shutter Drain 5 53 GND 22 φSHUT 24 φSHUT 33 φSHUT 31 32 φ2 34 φ2 50 φLH VDD 1 1 1 D14 D15 B D14 D15 D63 S1 R D63 S1 G D64 S10500 φSHUT-R 22 6 VOUT-R 2 29 NC VOUT-G 55 VOUT-B 54 30 NC GND 31 φROG-G 4 GND 26 φRS 32 φROG-B 10500 φROG-R 25 10500 33 φSHUT-B 10500 φSHUT-G 24 3 34 φ2 GND 35 VDD φ1 23 NC 28 35 23 φ1 φ1 51 NC Read Out Gate 6 CCD Register GND Shutter Gate 52 NC Red 5 Shutter Drain φLH CCD Register 53 VDD Shutter Gate 4 Shutter Gate φRS D14 D15 54 VOUT-B D63 S1 3 D64 GND S10500 55 VOUT-G D64 2 S10500 VOUT-R 56 NC D83 1 D83 NC D83 Pin Configuration (Top View) NC 27 V °C °C VDD Absolute Maximum Ratings • Supply voltage VDD 15 • Operating temperature –10 to +55 • Storage temperature –30 to +80 Block Diagram φROG-B φROG-G Features • Number of effective pixels: 31500 pixels (10500 pixels × 3) • Pixel size: 8µm × 8µm (8µm pitch) • Distance between line: 64µm (8 lines) • Single-sided readout • Shutter function • Ultra low lag/High sensitivity • Single 12V power supply • Input Clock Pulse: CMOS 5V drive • Number of output 3 (R, G, B) • Package: 56 pin SDIP (400 mil) 56 pin SDIP (Cer-DIP) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99216-PS ILX734LA Pin Description (Pins other than below are defined as NC.) Pin No. Symbol Pin No. Description Symbol Description 1 NC NC 31 φROG-G Clock pulse input 2 VOUT-R Signal out (red) 32 φROG-B Clock pulse input 3 GND GND 33 φSHUT-B Clock pulse input 4 φRS Clock pulse input 34 φ2 Clock pulse input 5 φLH Clock pulse input 35 VDD 12V power supply 6 GND GND 50 φ2 Clock pulse input 7 φ1 Clock pulse input 51 NC NC 22 φSHUT-R Clock pulse input 52 NC NC 23 φ1 Clock pulse input 53 VDD 12V power supply 24 φSHUT-G Clock pulse input 54 VOUT-B Signal out (blue) 25 φROG-R Clock pulse input 55 VOUT-G Signal out (green) 26 GND GND 56 NC NC Recommended Supply Voltage Item VDD Min. Typ. Max. Unit 11.4 12 12.6 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φ1, φ2 Cφ1, Cφ2 — 1600 — pF Input capacity of φLH CφLH — 10 — pF Input capacity of φRS CφRS — 10 — pF — 10 — pF Input capacity of φROG, φSHUT∗1 CφROG, CφSHUT ∗1 It indicates that φROG-R, φROG-G, φROG-B as φROG, φSHUT-R, φSHUT-G, φSHUT-B as φSHUT. Clock Frequency Item Min. Typ. Max. Unit — 1 5 MHz Min. Typ. Max. Unit High level 4.75 5.0 5.25 V Low level — 0 0.1 V Symbol φ1, φ2, φLH, φRS fφ1, fφ2, fφLH, fφRS Input Clock Pulse Voltage Condition Item φ1, φ2, φLH, φRS, φROG, φSHUT pulse voltage –2– ILX734LA Electrooptical Characteristics (Note 1) (Ta = 25°C, VDD = 12V, fφRS = 1MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Item Symbol Min. Typ. Max. Unit Remarks Red RR 1.3 2.0 2.7 Green RG 2.1 3.2 4.3 V/(lx · s) Note 2 Blue RB 1.6 2.5 3.4 Sensitivity nonuniformity PRNU — 6 20 % Note 3 Saturation output voltage VSAT 2 3.2 — V Note 4 Red SER 0.74 1.6 — Green SEG 0.46 1 — lx · s Note 5 Blue SEB 0.58 1.28 — Dark voltage average VDRK — 0.3 2.2 mV Note 6 Dark signal nonuniformity DSNU — 1.5 5.5 mV Note 6 Image lag IL — 0.02 — % Note 7 Supply current IVDD — 26 50 mA — Total transfer efficiency TTE 92 95 — % — Output impedance Zo — 250 — Ω — Offset level VOS — 6.5 — V Note 8 Dynamic range DR 1000 10670 — — Note 9 Sensitivity Saturation exposure Notes) 1. In accordance with the given electrooptical characteristics, the black level is defined as the average value of D2, D3 to D12. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT-G = 500mV (Typ.) (VMAX – VMIN)/2 PRNU = × 100 [%] VAVE Where the 10500 pixels are divided into blocks of 100. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4. Use below the minimum value of the saturation output voltage. 5. Saturation exposure is defined as follows. SE = VSAT/R ,, Where R indicates RR, RG, RB, and SE indicates SER, SEG, SEB. 6. Optical signal accumulated time τ int stands at 11ms. 7. VOUT-G = 500mV (Typ.) VOUT 8. Vos is defined as indicated bellow. VOUT indicates VOUT-R, VOUT-G, and VOUT-B. VOS 9. Dynamic range is defined as follows. DR = VSAT/VDRK GND When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage. –3– –4– 0 5 0 5 0 5 0 5 D62 D15 D14 D13 4 Dummy signal (63 pixels) S64 S10500 S1 D63 1-line output period (10583 pixels) Optical black (49 pixels) , D61 D3 D2 3 D1 2 1 Note) The transfer pulses (φ1, φ2, φLH) must have more than 10583 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. VOUT φRS φ2 φ1 φLH φROG Clock Timing Chart 1 ILX734LA D83 10583 D79 D78 D73 D72 S71 ILX734LA Clock Timing Chart 2 t4 t5 φROG t2 t6 t7 φ1 t1 t3 φ2 Clock Timing Chart 3 t7 t6 φ1 φLH φ2 t10 t11 t9 φRS t8 , , , t13 t12 VOUT –5– –6– 0 5 0 5 0 5 0 5 4 3 1 Note) Shutter pulse must not be low level during from 2 to 10583 of φ1. Integration time can be controlled by changing the timing φSHUT fall. φSHUT φRS φ2 φ1 φLH φROG 2 Clock Timing Chart 4 (Shutter Operation) Integration time ILX734LA 10583 ILX734LA Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 — ns φROG pulse high level period t2 1200 3000 — ns φROG, φ1 pulse timing t3 1200 3000 — ns φROG pulse rise time t4 0 5 10 ns φROG pulse fall time t5 0 5 10 ns φ1 pulse rise time/φ2 pulse fall time t6 0 20 60 ns φ1 pulse fall time/φ2 pulse rise time t7 0 60 ns φRS pulse high level period t8 45 20 250∗1 — ns — ns φRS, φLH pulse timing t9 45 250∗1 φRS pulse rise time t10 0 10 30 ns φRS pulse fall time t11 0 10 30 ns t12 — 10 — ns t13 — 10 — ns Signal output delay time ∗1 These timing data are the recommended condition under fφRS = 1MHz. –7– –8– Tr1 φLH 100Ω φRS 100Ω 5 6 50 7 35 34 2Ω 23 24 25 IC1 26 29 30 32 31 33 φSHUT-R φ1 φSHUT-G φROG-R 22 2Ω IC1 27 Data rate fφRS = 1MHz. In the case of fφRS = 5MHz, 3 pieces of 74AC04 are recommended to use for φ1 and φ2 driver. VOUT-R 5.1kΩ 47µF/ 100Ω 16V 1 4 NC 3 VOUT-G VOUT-R 2 55 51 54 VOUT-B GND 56 52 53 VDD φRS 100Ω NC φLH 100Ω Tr1 φSHUT-B φSHUT-G Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ∗1 12V Tr1 φROG-B φROG-R VOUT-B NC GND NC φ2 φ1 φ2 φ1 VDD φSHUT-R φ2 φSHUT-B φROG-B φROG-G φROG-G GND 5.1kΩ NC IC1: 74AC04 Tr1: 2SC2785 28 NC 5.1kΩ NC NC VOUT-G 0.1µF Application Circuit∗1 ILX734LA ILX734LA Example of Representative Characteristics (VDD = 12V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 1 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 450 500 550 600 650 700 Wavelength [nm] Dark signal output temperature characteristics (Standard characteristics) Integration time output voltage characteristics (Standard characteristics) 10 Output voltage rate Output voltage rate 5 1 0.5 0.1 0 10 20 30 40 0.5 0.1 60 50 1 1 5 10 Ta – Ambient temperature [°C] τ int – Integration time [ms] Offset level vs. VDD characteristics (Standard characteristics) Offset level vs. temperature characteristics (Standard characteristics) 12 12 Ta = 25°C 10 Vos – Offset level [V] Vos – Offset level [V] 10 8 6 4 ∆Vos ∆VDD 6 ∆Vos ∆Ta –0.5mV/°C 4 0.3 2 0 11.4 8 2 12.0 0 12.6 VDD [V] 0 10 20 30 40 50 Ta – Ambient temperature [°C] –9– 60 ILX734LA Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm , , , , Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N 0.9Nm (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. – 10 – ILX734LA 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 11 – 2.0 ~ – 12 – 3.0 5.0 ~ 1.27 V 43 Cer-DIP TIN PLATING 42ALLOY 13.5g LS-E4(E) LEAD TREATMENT LEAD MATERIAL PACKAGE MASS DRAWING NUMBER A' 14 113.0 ± 1.0 29.21 97.0 110.0 29.21 84.0 ( 8µm X 10500 Pixels ) No.1 Pixel (Green) PACKAGE MATERIAL 1 H 56 15.0 ± 0.8 PACKAGE STRUCTURE 7.0 A 5.0 ± 0.8 4.0 ± 0.5 56Pin DIP ( 400mil ) 0.46 28 29 ~ 3.0 (AT STAND OFF) 10.16 B 4. The notch of the package must not be used for reference of fixing. 3. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 2. The height from the bottom “B” to the effective image area is 2.4 ± 0.30mm. 1. The point “A” of the package is the horizontal reference. The two points “A'” of the package are the vertical reference. A' 15 42 10.0 ± 1.0 4.4 ± 0.5 Unit: mm 8.8 3.6 0˚ to 9˚ 0.25 Package Outline ILX734LA