TUSB6015 SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 TUSB6015 USB 2.0 High Speed Peripheral Controller Data Sheet FEATURES DESCRIPTION The TUSB6015 is a USB 2.0 HS Peripheral Controller designed for seamless interface to an external Host processor through the NOR FLASH-like interface. USB 2.0 High-Speed (HS) Compliant Peripheral Controller Core USB-IF TID # 40630005 Integrated USB 2.0 PHY NOR FLASH - Like External Host Interface DP/DM lines are high impedance when the device is not powered Six physical endpoints Each endpoint is configurable as IN or OUT with dedicated 1K buffer NOR Flash Interface Access modes: Asynchronous 16-bit single access Asynchronous 32-bit single access Asynchronous 16x16 burst access w/ DMA Synchronous 16x16 burst access with DMA (Max GPMC clock is 65 MHz) The NOR FLASH-like interface is a 16-bit, multiplexed address/data, interface with support for synchronous burst and single asynchronous read/write access. Configuration registers are accessible via the asynchronous chip select only; the End Point FIFO’s are accessible via both the synchronous and asynchronous chip selects. The device also has eight user configurable general purpose I/0 interface pins. The GPIO can be configured as an interrupt or wakeup source. Some GPIO have secondary NOR-flash DMA Request functionality. The device is fully compliant with the Universal Serial Bus Specification Rev. 2.0. Interrupt on DP/DM line state change for CEA-936-A detect VBUS MAX Voltage rating will be 6V for USB Charging RoHS Complaint 80 Terminal BGA MICROSTAR JUNIOR Package The ESD protection level is 2KV HBM (JESD22A114D), 500V CDM (JESD22-C101C). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appear at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2008, Texas Instruments Incorporated WWW.TI.COM 1 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Ordering Information 1 PACKAGED DEVICES TUSB6015IZQE 3 TUSB6015IZQER• PACKAGE2 MARKING ZQE TUSB6015I ZQE TUSB6015I 1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 3 The tape and reel option is available for TUSB6015IZQE by adding an R suffix. 2 WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Device Block Diagram WWW.TI.COM 3 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Electrical Characteristics Absolute Maximum Ratings1 3.3V Supply Voltage, VDDA3P3...................................................................................................-0.5 V to 4.2 V 1.8V Supply Voltage VDD18.........................................................................................................-0.5 V to 2.1 V 1.5V Supply Voltage, VDD15, VDDD1P5, VDDCM1P5, VDDA1P5.............................................-0.5 V to 2.1 V 2 USB VBUS Supply Voltage ............................................................................................................ 0 V to 6.0 V 3 Input voltage, VI, 3.3V USB .................................................................................... -0.5 V to VDDA3P3 + 0.5 V Output voltage, VO, 3.3V USB.................................................................................. -0.5 V to VDDA3P3 + 0.5 V Input clamp current, IIK ........................................................................................................................... ±20 mA Output clamp current, IOK ........................................................................................................................ ±20 mA Storage temperature range, Tstg ...............................................................................................-65°C to 150°C Recommended Operating Conditions PARAMETER VDDA3P3 Supply voltage for PHY Analog MIN TYP MAX UNIT 3 3.3 3.6 V VDD18 Supply voltage for Digital I/O 1.62 1.8 1.98 V VDD15 VDDD1P5 VDDCM1P5 VDDA1P5 Supply voltage for Digital Core Supply voltage for PHY Digital Supply voltage for PHY Common Module Supply voltage for PHY Analog 1.35 1.5 1.65 V TA Operating Temperature -40 85 °C TUSB6015I (Industrial grade) 1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. 2 VBUS can tolerate 6V for the lifetime of the device. It can handle 6.5V for 36 hours. 3 TUSB6015 complies with short circuit withstand and AC stress conditions as described in Chapter 7.1.1 of the USB 2.0 specification. 4 WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Electrical Characteristics for the Digital I/O TA = -30°C - 85°C, VDD18 = 1.8 V ±10%, VSS = 0 V (Unless otherwise noted) TEST CONDITIONS PARAMETER VI MIN TYP MAX UNIT 0 VDD18 V 0 VDD18 V Input voltage Output voltage LVCMOS LVCMOS VIH High–level input voltage LVCMOS 0.7 x VDD18 VDD18 V VIL Low–level input voltage LVCMOS 0 0.3 x VDD18 V VOH High–level output voltage LVCMOS IOH = 8mA LVCMOS open–drain IOL = 4mA 0.22 x VDD18 IOL = 8mA 0.22 x VDD18 VO VOL Low–level output LVCMOS voltage LVCMOS (1.5V_SWEN, 3.3V_SWEN only) 0.8 × VDD18 IOL = 100uA V 10 V mV IIH High–level input current LVCMOS VI = VI max ±1 uA IIL Low–level input current LVCMOS VI = VI min ±1 uA IOZ Output leakage current (high–Z) VI = VI max or VSS ±20 uA Ci Input Capacitance (1.8V NOR Interface) 2.43 pF tr, tf Input rise/fall time 25 ns 0 WWW.TI.COM 5 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Vbus - Electrical Characteristics for the Integrated USB 2.0 Transceiver, TA = -30°C - 85°C,VDD15 = 1.5v±10%, VDD18 = 1.8V ±10%, VDDA1P5 = 1.5 V ±10%, VDDA3P3 = 3.3 ±10%,VDDD1P5 = 1.5 V ±10%, VDDCM1P5 = 1.5 ±10%, VSS = 0 V (unless otherwise noted)† PARAMETER MIN TYP MAX UNIT Input Levels Vbus Input Impedance 360 690 kΩ Vbus Valid Comparator 4.4 4.75 V 11 uA Vbus leakage current (when device is powered off) †Characterization only. Limits approved by design. 6 WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 DP and DM - Electrical Characteristics for the Integrated USB 2.0 Transceiver TA = -30°C - 85°C,VDD15 = 1.5v±10%, VDD18 = 1.8V ±10%, VDDA1P5 = 1.5 V ±10%, VDDA3P3 = 3.3 ±10%,VDDD1P5 = 1.5, V ±10%, VDDCM1P5 = 1.5 ±10%, VSS = 0 V (unless otherwise noted)† PARAMETER MIN TYP MAX UNIT Input Levels for Full Speed VDI VCM Full–speed differential input threshold 0.2 Input (was differential) common mode range 0.8 2.5 V 150 mV V Input Levels for High Speed V(HSSQ) High–speed squelch detection threshold (differential signal amplitude) 100 VDI High–speed differential input threshold voltage 100 CHSLOAD Capacitance to ground on each line mV 5.5 pF 0 0.3 V 3.6 V Output Levels for Full Speed VOL Low–level output voltage VOH High–level output voltage (driven) 2.8 VO(SE1) Output voltage on SE1 0.8 VO(CRS) Output signal crossover voltage 1.3 2 V V Output Levels for High Speed V(HSOI) High–speed idle level -10 10 mV V(HSOH) High–speed data signaling high 360 440 mV V(HSOL) High–speed data signaling low -10 10 mV VID(CHIRPJ) Chirp J level (differential voltage) 700 1100 mV VID(CHIRPK) Chirp K level (differential voltage) -900 -500 mV Driver Characteristics (Full Speed) tr Full–speed rise time 4 20 ns tf Full–speed fall time 4 20 ns 90% 110% t(RFM) Full–speed rise/fall time matching Driver Characteristics (High Speed) tr Rise time (10%-90%) 500 tf Fall time (10%-90%) 500 ro(HSDRV) Driver output resistance (serves as a high–speed termination) 40.5 49.5 t(FRFM) Differential rise and fall time matching 90% 111.11% 479.76 480.24 Mb/s 2.0 V ps ps Ω Clock Timings t(HSDRAT) High–speed data rate Single-Ended Receiver VIT+ Positive–going input threshold voltage VIT- Negative–going input threshold voltage 0.8 Hysteresis voltage 200 Vhys WWW.TI.COM V 500 mV 7 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 DP and DM - Electrical Characteristics for the Integrated USB 2.0 Transceiver (CONT’D) INPUT LEAKAGE TEST CONDITION DP/DM Measurement taken with pull-up/dn disabled and device in idle mode DP/DM Voltage = 0 – VDDA3.3 DP/DM Measurement taken with pull-up/dn disabled and device in active mode DP/DM Voltage = 2V †Characterization only. Limits approved by design. 1 Typical DP/DM Input Leakage with pull-up/dn disabled and device in active mode 8 WWW.TI.COM MIN TYP -1.3 See 1 Chart MAX UNIT 1.3 uA 1.3 uA TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Power Sequencing Guidelines Power-On Reset The system reset function ensures an orderly start-up sequence for the TUSB6015. There is a one active low external system reset input (RSTn). The reset initializes the Power/Reset/Clock Manager (PRCM) module, which in turn generates all the internal resets to initialize USB 2.0 PHY Macro and synchronous logic in the core. While reset is asserted (active low), the dual functional pin is sampled to determine device configuration after reset. Since TUSB6015 relies on a dual function pin to configure the device during reset, the reset must be sufficiently long for (external) marginal pull-up/pull-down to achieve the intended levels. Reset pulse duration should be at least three times actual RC constant time (with typical 22 kOhm marginal pull-up resistor with 50 pF load, reset pulse should be at least 3.3 µs). All functional pins remain in same state even after RSTn is de-asserted and stay in that state until internal core reset is cleared. The internal core reset is held for 16 system clock cycles following low-to-high RSTn transition. Upon power-on reset, the following must be determined for proper device initialization: System reference clock source Device uses dual-mode pin to determine initial clock input setup. Dual function pin is latched during the reset. After the reset this terminal assumes the normal functionality. External Pin Function GPIO6 Reference Clock Frequency Select CLK_24_SEL CLKIN_19_2_24 Frequency Select Description Determines the reference clock pin 0 – 38.4 MHz (CLKIN_38_4 pin is used) 1 – 19.2 MHz (CLKIN_19_2_24 pin is used) Determines the reference frequency of the CLKIN_19_2_24 pin 0 – RSVD 1 – 19.2 MHz If GPIO6 is low at reset, this pin will have no effect on clock selection. Upon exiting reset, the USB 2.0 PHY is not in the suspend state and the system clock (60 MHz) is enabled and free running. The USB 2.0 HS Peripheral Controller Core powers up and a session is not enabled. With session not enabled, all the USB 2.0 HS Peripheral Controller Core State Machine’s are in the idle state. After reset is de-asserted, the device asserts the DevReady interrupt to the External Host to indicate that it is ready to be programmed. The host reads the NOR Flash Interrupt Source register and decides how to proceed based on the device’s current status. WWW.TI.COM 9 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 System Power-Up Sequence 10 WWW.TI.COM TUSB6015 SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Input Supply Current TA = 25°C VDDA3.3 = 3.3V +/- 10%, VSS = 0V PARAMETER TEST CONDITIONS TYP 1 Idle IDD Input supply current 2 No Bus Activity 3 Active (Transmit / Receive) 4 Reset UNIT 16.5 uA 3.7 mA 3.6 mA 2.7 mA TYP UNIT 0.26 uA 157.0 uA 350.0 uA 1.8 mA TYP UNIT 2.0 uA 56.5 mA 58.0 mA 29.2 mA VDD1.87 = 1.8V +/- 10%, VSS = 0V PARAMETER TEST CONDITIONS 1 Idle IDD Input supply current 2 No Bus Activity 3 Active (Transmit / Receive) 4 Reset Cumulative VDD1.5 = 1.5V +/- 10%, VSS = 0V (VDD1.5, VDDD1.5, VDDCM1.5, VDDA1.5) PARAMETER TEST CONDITIONS 1 Idle IDD Input supply current 2 No Bus Activity 3 Active (Transmit / Receive) 4 Reset 1 DevIdle bit set in Device PRCM Management Register, USB cable unplugged. Normal operation with no packets being transferred on the USB, except SOF every 125 µs. 3 Bulk IN and OUT on one End Point. Packet size is 512 bytes. 4 TUSB6015 RSTn asserted. 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appear at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2008, Texas Instruments Incorporated WWW.TI.COM 11 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Input Clock Requirements CLKIN 19.2 MHz Recommended Operating Conditions PARAMETER VALUE Nominal Clock Frequency (GPIO6 = high @ reset) (CLK_24_SEL = high @ reset) 19.20 MHz Frequency Accuracy +/- 100 ppm Maximum Rise/Fall Time 5ns (10% to 90%) Input Clock Type Square Wave Duty Cycle 45% - 55% Input Capacitance Loading 4pF Jitter 118 ps CLKIN 38.4 MHz Recommended Operating Conditions PARAMETER VALUE Nominal Clock Frequency (GPIO6 = low @ reset) 38.40 MHz Frequency Accuracy +/- 100 ppm Input Clock Type Sinusoid Duty Cycle 45% - 55% Input Common Mode Voltage VCM (VCM) 1 V +/- 100 mV Vp-p 200 mV – 800 mV Input Capacitance Loading 5 pF Rin 180 kOhms Jitter 100 ps (peak-to-peak) 12 WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Timing Diagrams Asynchronous Read Access PARAMETER t_acsnh_acsnl t_scsnh_acsnl t_add_advn_h t_acsnl_advn_s t_add_advn_s t_advn_oen t_advn t_rd_acc t_acsn_rdy t_acsn_rdy_z t_oen_data_z t_rdy_data MIN Delay time, ACSn high to ACSn low Delay time, SCSn high to ACSn low Address Hold to ADVn high ACSn low Setup to ADVn high Address Setup to ADVn high Sampled Address to OEn low ADVn low pulse OEn low to RDY high (16-bit Register Access) st OEn low to RDY high (32-bit Register Access) 1 16-bit nd OEn low to RDY high (32-bit Register Access) 2 16-bit st OEn low to RDY high (FIFO Access, with DMAREQ) 1 16-bit nd OEn low to RDY high (FIFO Access, with DMAREQ) 2 16-bit ACSn low to RDY low ACSn high to RDY high-Z OEn high to Data high-Z Delay time, RDY high to data valid WWW.TI.COM 8 8 0.8 18 18 1 7 6 5 2 3 3 -1 MAX UNIT 8 7 4 4 4 7 7 8 6 ns ns ns ns ns ns ns Sys Clk Sys Clk Sys Clk Sys Clk Sys Clk ns ns ns ns 13 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Asynchronous Write Access PARAMETER t_acsnh_ascnl t_scsnh_ascnl t_add_advn_h t_acsnl_advn_s t_add_advn_s t_advn t_advn_wen t_wr_acc t_acsn_rdy t_acsn_rdy_z t_wen_datav 14 MIN Delay time, ACSn high to ACSn low Delay time, SCSn high to ACSn low Address Hold to ADVn high ACSn low Setup to ADVn high Address Setup to ADVn high ADVn low pulse ADVn to WEn low WEn low to RDY high (16-bit Register Access) st WEn low to RDY high (32-bit Register Access) 1 16-bit nd WEn low to RDY high (32-bit Register Access) 2 16-bit st WEn low to RDY high (FIFO Access, with DMAREQ) 1 16-bit nd WEn low to RDY high (FIFO Access, with DMAREQ) 2 16-bit ACSn low to RDY low ACSn high to RDY high-Z Delay time, WEn low to Data valid WWW.TI.COM 8 8 0.8 18 18 7 1 3 2 3 3 3 MAX UNIT 5 4 7 4 4 7 7 1-5ns ns ns ns ns ns ns ns Sys Clk Sys Clk Sys Clk Sys Clk Sys Clk ns ns Sys Clk TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Synchronous Burst Read Access Notes: RDY going low is asynchronous to t_scsn_rdy. Going high, it is synchronous to CLK. Read Data output and RDY going high are synchronous to CLK. Valid Data Time programmable through Device Wait Count Register. Wait Count is not used for non-DMA synchronous reads. PARAMETER MIN MAX UNIT t_clk t_scsnh_scsnl t_acsnh_scsnl t_scsn t_scs_off t_rdata t_rdy t_advn t_advn_oen t_oen_off t_oen t_rd_acc t_add_advn_h t_scsnl_advn_s t_add_advn_s t_scsn_rdy t_scsn_rdy_z t_oen_data_z Cycle Time (max 67.5 MHz) Delay time, SCSn high to SCSn low Delay time, ACSn high to SCSn low Delay time, SCSn low to first rising edge of CLK CLK to SCSn high Read data output delay RDY output delay ADVn low pulse ADVn high to OEn low CLK to OEn high OEn setup to CLK high OEn hold time Valid Data Time (with DMAREQ) Addr Hold time to ADVn high SCSn low Setup to ADVn high Address Setup to ADVn high SCSn low to RDY valid low SCSn high to RDY high-Z OEn high to Data high-Z 14.8 8 8 3ns 4 2.2 2.2 7 3 4 3.75 0 1 1 0.8 12 12 1+3ns 9.2 8.2 2 32 7 7 8 ns ns ns CLK ns ns Ns Ns Ns Ns Ns CLK Ns Ns Ns ns ns ns 1 Device Wait Count Register = 0 or 1. Device Wait Count Register = 31. 2 WWW.TI.COM 15 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Synchronous Burst Write Access Note: RDY going low is asynchronous to t_scsn_rdy. Going high, it is synchronous to CLK. Valid Data Time programmable through Device Wait Count Register. For Wait Count values other than 0 or 1 (when DMAREQ is used), t_wr_acc = Wait Count + 1. PARAMETER t_clk t_scsnh_scsnl t_acsnh_scsnl t_scsn t_scs_off t_wdata_s t_wdata_h t_rdy t_add_advn_h t_scsnl_advn_s t_add_advn_s t_advn t_advn_wen t_wen_off t_wen t_wr_acc t_scsn_rdy t_scsn_rdy_z MIN Cycle Time (max 67.5 MHz) Delay time, SCSn high to SCSn low Delay time, ACSn high to SCSn low Delay time, SCSn low to first rising edge of CLK CLK to SCSn high Data setup to CLK high Data hold time CLK to RDY output delay Address Hold SCSn low Setup to ADVn high Address Setup to ADVn high ADVn low pulse ADVn high to WEn low CLK to WEn high WEn setup to CLK high WEn hold time Valid Data Time (with DMAREQ) SCSn low to RDY valid low SCSn high to RDY high-Z 1 Device Wait Count Register = 0 or 1. Device Wait Count Register = 31. 2 16 WWW.TI.COM 14.8 8 8 3ns 1+3ns 3.75 0.6 2.2 0.8 12 12 7 1+3ns 1+3ns 3.75 0 1 1 MAX 1+3ns 8.2 2 32 7 7 UNIT ns ns ns CLK Sys Clk ns ns ns ns ns ns ns CLK Sys Clk ns CLK ns ns TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Pin Descriptions TERMINAL NAME BALL TYPE I/O RESET STATE DESCRIPTION VDD15 A1 Supply - - Digital core power supply, 1.5 V VSS A2 Supply - - Ground CLKIN_19_2_24 Frequency Select at Reset CLK 24 SEL = HIGH, 19.2 MHz CLK_24_SEL A3 LVCMOS 1 Failsafe I In with Pull-up CLK 24 SEL = LOW, RSVD If GPIO6 is low at reset, this pin will have no effect on clock selection. CLKIN_38_4 A4 CLKIN_19_2_24 A5 LVCMOS 1 Failsafe LVCMOS 1 Failsafe I In System Clock In. Connect directly to ground if not used. I In System Clock In. Connect directly to ground if not used. VSS A6 Supply - - Ground VDD18 A7 Supply - - IO Power Supply, 1.8 V OEn A8 I In with Pull-up VDD15 A9 Supply - - Digital core power supply, 1.5 V VSSREF B1 Supply - - Ground reference for the reference circuits GPIO7 B2 I/O In with Pull-up VDD15 B3 Supply - - Digital core power supply, 1.5 V VSS B4 Supply - - Ground VDD18 B5 Supply - - IO Power Supply, 1.8 V 1 I/O In with Pull-up GPIO 2 / DMA Request 2 LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS Output Enable GPIO 7 GPIO2_DMAREQ2 B6 ADAT15 B7 LVCMOS I/O In with Pull-up Multiplexed ADDRESS.15/DATA.14 ADAT16 B8 LVCMOS I/O In with Pull-up Multiplexed ADDRESS.16/DATA.15 VSS B9 Supply - - Ground VDDA3P3 C1 Supply - - 3.3V Analog Supply R1 C2 Bias I - High precision external resistor used for calibration. (R1 value: 10.7 K +/- 1%) GPIO4_DMAREQ4 C4 I/O In with Pull-up VDD15 C5 - - I In with Pull-up Address Valid I/O In with Pull-up Multiplexed ADDRESS.12/DATA.11 I/O In with Pull-up Multiplexed ADDRESS.14/DATA.13 ADVn C6 ADAT12 C7 ADAT14 C8 Failsafe LVCMOS 1 Failsafe Supply LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe WWW.TI.COM GPIO 4 / DMA Request 4 Digital core power supply, 1.5 V 17 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 18 LVCMOS In with Pull-up NOR Interface Clock I/O - USB Differential Pair - - 1.5V PLL Supply Supply - - 1.5V PLL Ground LVCMOS I - Test Mode. Under normal operation this signal should be tied directly to GND. I/O In with Pull-up GPIO 1 I In with Pull-up Write Enable I/O In with Pull-up Multiplexed ADDRESS.13/DATA.12 I/O In with Pull-up Multiplexed ADDRESS.11/DATA.10 Supply - - Digital core power supply, 1.5 V Supply - - 1.5V Analog Ground E2 USB I/O - USB Differential Pair E3 Supply - - 1.5V Analog Supply VSSA3P3 E4 Supply - - 3.3V Analog Ground VSS E5 Supply - - Ground ADAT2 E6 I/O In with Pull-up Multiplexed ADDRESS.2/DATA.1 GPIO5_DMAREQ5 E7 I/O In with Pull-up GPIO 5 / DMA Request 5 GPIO3_DMAREQ3 E8 I/O In with Pull-up GPIO 3 / DMA Request 3 VSS E9 Supply - - Ground VDDD1P5 F1 Supply - - 1.5V Digital Supply ID F2 USB I - Should be left floating as a USB device. VBUS F3 USB I - USB VBUS VSSD1P5 F4 Supply - - 1.5V Digital Ground GPIO6 F5 I/O In with Pull-up CLK C9 DP D1 USB VDDCM1P5 D2 Supply VSSCM1P5 D3 TEST D4 GPIO1 D5 WEn D6 ADAT13 D7 ADAT11 D8 VDD15 D9 VSSA1P5 E1 DM VDDA1P5 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS I GPIO 6 / Input Clock Source Select at reset. GPIO6 = HIGH, 19.2/24 MHz GPIO6 = LOW, 38.4 MHz I/O In with Pull-up Multiplexed ADDRESS.1/DATA.0 I/O In with Pull-up Multiplexed ADDRESS.10/DATA.9 I/O In with Pull-up Multiplexed ADDRESS.9/DATA.8 - In with Pull-up Digital core power supply, 1.5 V ADAT1 F6 ADAT10 F7 ADAT9 F8 VDD15 F9 VSS G1 Supply - - Ground 1.5V_SWEN G2 LVCMOS O 0 Switch Enable for 1.5V supply for Vbat/Vbus 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe Supply WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Switch, if applicable 1 Failsafe 3.3V_SWEN G3 ACSn G4 ADAT3 G5 ADAT4 G6 RDY G7 SCSn G8 VSS G9 LVCMOS Switch Enable for 3.3V supply for Vbat/Vbus Switch, if applicable O 0 I In with Pull-up Asynchronous Chip Select I/O In with Pull-up Multiplexed ADDRESS.3/DATA.2 I/O In with Pull-up Multiplexed ADDRESS.4/DATA.3 LVCMOS tri-state O high z LVCMOS I In with Pull-up Supply - - I In with Pull-up O 0 5V Charge Pump Enable, if applicable O 0 Use for external power supply low power mode when idle, if applicable I/O In with Pull-up GPIO 0 I/O In with Pull-up Multiplexed ADDRESS.5/DATA.4 I/O In with Pull-up Multiplexed ADDRESS.6/DATA.5 I/O In with Pull-up Multiplexed ADDRESS.7/DATA.6 I/O In with Pull-up Multiplexed ADDRESS.8/DATA.7 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS Ready Synchronous Chip Select Ground RSTn H1 CPEN H2 SLEEP H3 GPIO0 H4 ADAT5 H5 ADAT6 H6 ADAT7 H7 ADAT8 H8 VDD18 H9 Supply - - IO Power Supply, 1.8 V VDD18 J1 Supply - - IO Power Supply, 1.8 V VSS J2 Supply - - Ground VDD15 J3 Supply - - Digital core power supply, 1.5 V VSS J4 Supply - - Ground O 1 DMA Request 1 - - IO Power Supply, 1.8 V O 1 DMA Request 0 - - Ground O 1 Interrupt DMAREQ1 J5 VDD18 J6 DMAREQ0 J7 VSS J8 INT J9 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe LVCMOS 1 Failsafe Supply LVCMOS 1 Failsafe Supply LVCMOS 1 Failsafe Reset Active Low 1 Failsafe means that the signal can toggle when VDD18 is not present without damaging the device. WWW.TI.COM 19 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 External Components USB PHY Voltage and Current Bias Resistor Pin: R1 This signal must connect to a precision external resistance to set the internal operating reference currents and cable driver output currents. A resistance of 10.7 k• ± 1% (temperature coefficient ±100ppm/°C) is necessary to meet requirements set forth in the Universal Serial Bus Revision 2.0 specification. The side of the resistor not connected to the R1 signal should connect through a low impedance path to the circuit board ground plane. USB PHY Voltage and Current Reference Ground: VSSREF This signal is the reference ground for the voltage and current reference circuitry internal to the Data/Port macro. This signal must connect to the low impedance circuit board ground plane. USB PHY Power Connections: VDDCM1P5, VDDA1P5, VDDD1P5, VDDA3P3 Decoupling capacitors are required to suppress high-frequency switching noise and stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the chip. This minimizes the inductance of the circuit board wiring and interconnects. The USB 2.0 PHY Macro has two power rails, 1.5V (VDDCM1P5, VDDD1P5, VDDA1P5) and 3.3V (VDDA3P3). Each power connection has its own associated ground connection, 1.5V (VSSCM1P5, VSSD1P5, VSSA1P5) and 3.3V (VSSA3P3). Each supply is isolated from the others to provide noise isolation. A combination of high-frequency capacitors near each terminal is suggested, such as paralleled 1uF, 0.01uF, and 0.001uF capacitors. A lower frequency 10uF filter capacitor is also recommended. A series inductor on the analog supplies is also recommended. All ground pins must connect through a low impedance path to the circuit board ground plane. All grounds can be connected to each other. • VDDCM1P5 (Common Module 1.5V Supply) - (1) 1µf , (1) 0.1µf, 0.01µf, (1) 0.001µf, (1) 10µf • VSSCM1P5 (Common Module Ground) • VDDD1P5 (Digital 1.5V Supply) - (1) 0.1µf, (1) 0.001µf, (1) 10µf • VSSD1P5 (Digital 1.5V Ground) • VDDA1P5 (Analog 1.5V Supply) - (1) 0.1µf, (1) 0.001µf, (1) 10µf, with a series inductor between the main supply and the device, the caps between the inductor and the device. • VSSA1P5 (Analog 1.5V Ground) • VDDA3P3 (Analog 3.3V Supply) - (1) 0.1µf, (1) 0.001µf, (1) 10µf, with a series inductor between the main supply and the device, the caps between the inductor and the device. • VDDA3P3 (Analog 3.3V Ground) 20 WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Digital Power Connections: VDD18, VDD15 The digital portion of the TUSB6015 has two power rails, 1.5V (VDD15) and 1.8V (VDD18). There is one digital ground connection (VSS). Each supply is isolated from the others to provide noise isolation. A combination of high-frequency capacitors near each terminal is suggested, such as paralleled 0.01uF and 0.001uF capacitors. A lower frequency 10uF filter capacitor is also recommended. All ground pins must connect through a low impedance path to the circuit board ground plane. All grounds can be connected to each other. • VDD15 (Digital Core Voltage 1.5V Supply) - (5) 0.1µf, (5) 0.001µf, (1) 10µf • VDD18 (Digital IO Voltage 1.8V Supply) - (5) 0.1µf, (5) 0.001µf, (1) 10µf • VSS (Digital Ground) WWW.TI.COM 21 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 Mechanical Characteristics TUSB6015 uses an 80-pin u*BGA package. The lead-free solder ball composition is Sn/Ag1.2Cu0.5 The substrate plating on the die side where the die bonds to is NiAu, The substrate finish on the bottom side where the solder balls attach to is bare Cu. ZQE (S-PBGA-N80) 22 Plastic Ball Grid Array WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Reflow Conditions WWW.TI.COM 23 TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 12, 2008 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com Applications Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright © 2005, Texas Instruments Incorporated 24 WWW.TI.COM TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 WWW.TI.COM 25 PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) TUSB6015IZQE ACTIVE BGA MI CROSTA R JUNI OR ZQE 80 360 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TUSB6015IZQER ACTIVE BGA MI CROSTA R JUNI OR ZQE 80 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 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TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee® Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2008, Texas Instruments Incorporated