HV57908 8 MHz, 64-Channel Serial To Parallel Converter With Push-Pull Outputs Ordering Information Package Options Device 80 Lead Quad Ceramic Gullwing 80 Lead Quad Plastic Gullwing 80 Lead Quad Ceramic Gullwing (MIL-STD-883 Processed*) Die HV57908DG HV57908PG RBHV57908DG HV57908X HV57908 *For Hi-Rel process flows, please refer to page 5-3 in the Databook. Features General Description ❏ Processed with HVCMOS® technology The HV579 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for electroluminescent displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. ❏ 5V CMOS logic ❏ Output voltages up to 80V ❏ Low power level shifting ❏ 8MHz data rate The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. HVout1 is connected to the first stage of the shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT 64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE (latch enable) input is high. The data in the latches is stored when LE is low. ❏ Latched data outputs ❏ Forward and reverse shifting options (DIR pin) ❏ Diode to VPP allows efficient power recovery ❏ Outputs may be hot switched ❏ Hi-Rel processing available Absolute Maximum Ratings Supply voltage, VDD1 -0.5V to +7.5V Output voltage, VPP -0.5V to +90V Logic input levels -0.3V to VDD +0.3V Ground current 2 1.5A Continuous total power dissipation 3 Operating temperature range Plastic Ceramic Plastic Ceramic Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds 1200mW 1900mW -40°C to 85°C -55°C to 125°C -65°C to +150°C 260°C Notes: 1. All voltages are referenced to GND. 2. Limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic. 11/12/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV57908 Electrical Characteristics (over recommended operating conditions unless noted, T =-40°C to +85°C) A DC Characteristics Symbol Max Units IDD VDD supply current Parameter Min 15 mA VDD = VDD max fCLK = 8MHz IPP High voltage supply current 100 µA Outputs high 100 µA Outputs low IDDQ Quiescent VDD supply current 100 µA All VIN = VDD VOH High-level output V IO= -15mA, VPP = 80V VOL Low-level output HVOUT 65 Data out VDD - 0.5 HVOUT Data out Conditions V IO= -100µA 7 V IO = 12mA, VPP = 80V 0.5 V IO= 100µA IIH High-level logic input current 1 µA VIH = VDD IIL Low-level logic input current -1 µA VIL = 0V High voltage clamp diode 1 V IOC = 1mA VOC AC Characteristics (TA = 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points]) Symbol Parameter Min Max Units fCLK Clock frequency 8 MHz tWL,tWH Clock width high or low 62 ns tSU Data set-up time before clock rises 10 ns tH Data hold time after clock rises 15 ns tON, tOFF Time from latch enable to HVOUT tDHL Conditions 500 ns CL = 15pF Delay time clock to data high to low 70 ns CL = 15pF tDLH Delay time clock to data low to high 70 ns CL = 15pF tDLE* Delay time clock to LE low to high 25 ns tWLE Width of LE pulse 25 ns tSLE LE set-up time before clock rises 0 ns * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize). Recommended Operating Conditions Symbol Parameter Min Max Units 4.5 5.5 V 8 80 V VDD Logic supply voltage VPP Output voltage VIH High-level input voltage VDD -0.5 VIL Low-level input voltage 0 fCLK Clock frequency TA Operating free-air temperature V 0.5 V 8 MHz Plastic -40 +85 Ceramic -55 +125 Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. 2 °C HV57908 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input HVOUT GND GND GND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms VIH Data Input 50% Data Valid 50% VIL tSU CLK 50% tf tH 90% 50% 50% tWL tr VIH 10% 10% tWH 90% 50% VIL VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL LE VIH 50% 50% VOL tDLE tWLE tSLE 90% 10% HVOUT w/ S/R LOW VOH VOL tOFF HVOUT w/ S/R HIGH 10% tON 3 90% VOH VOL HV57908 Functional Block Diagram POL BL LE VPP DIOA HVOUT1 Clock HVOUT2 DIR 64-bit Static Shift Register • • • 60 Additional Outputs • • • HVOUT63 64 Latches HVOUT64 DIOB Function Table Inputs Outputs Function Data CLK LE BL POL DIR All O/P High X X X L L X Shift Reg HV Outputs H All O/P Low X X X L H X L O/P Normal X X X H H X No inversion O/P Inverted X X X H L X Inversion L ↑ H H H X L L H Data Falls Through (Latches Transparent) Data Out ↑ H H H X H H L ↑ H H L X L H H H H L X H L L H H X * Stored Data Data Stored X ↑ X Latches Loaded X X L H L X * Inversion of Stored Data DIOA ↑ X X X H Qn→ Qn +1 - DIOB DIOB ↑ X X X L Qn→ Qn -1 - DIOA I/O Relation Note: * = dependent on previous stage’s state. 4 HV57908 Pin Configurations Package Outline HV579 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function HVOUT 24/41 HVOUT 23/42 HVOUT 22/43 HVOUT 21/44 HVOUT 20/45 HVOUT 19/46 HVOUT 18/47 HVOUT 17/48 HVOUT 16/49 HVOUT 15/50 HVOUT 14/51 HVOUT 13/52 HVOUT 12/53 HVOUT 11/54 HVOUT 10/55 HVOUT 9/56 HVOUT 8/57 HVOUT 7/58 HVOUT 6/59 HVOUT 5/60 HVOUT 4/61 HVOUT 3/62 HVOUT 2/63 HVOUT 1/64 DIOA N/C N/C N/C LE CLK BL VDD DIR GND POL N/C N/C N/C DIOB VPP 41 64 80-pin Gullwing Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function HVOUT 64/1 HVOUT 63/2 HVOUT 62/3 HVOUT 61/4 HVOUT 60/5 HVOUT 59/6 HVOUT 58/7 HVOUT 57/8 HVOUT 56/9 HVOUT 55/10 HVOUT 54/11 HVOUT 53/12 HVOUT 52/13 HVOUT 51/14 HVOUT 50/15 HVOUT 49/16 HVOUT 48/17 HVOUT 47/18 HVOUT 46/19 HVOUT 45/20 HVOUT 44/21 HVOUT 43/22 HVOUT 42/23 HVOUT 41/24 HVOUT 40/25 HVOUT 39/26 HVOUT 38/27 HVOUT 37/28 HVOUT 36/29 HVOUT 35/30 HVOUT 34/31 HVOUT 33/32 HVOUT 32/33 HVOUT 31/34 HVOUT 30/35 HVOUT 29/36 HVOUT 28/37 HVOUT 27/38 HVOUT 26/39 HVOUT 25/40 40 65 Index 25 80 24 1 top view 80-pin Gullwing Package H OUT 32 H OUT 33 DIR = H; CW (H OUT1 → H OUT 64) DIR = L; CCW (H OUT 64 → H OUT1) • • DIR = H DIR = L • • SR • • • • • • H OUT 2 H OUT 63 H OUT 1 H OUT 64 Pin 25 DIOA 39 DIOB Note: Pin designation for DIR = H/L. Example: For DIR = H, pin 41 is HVOUT 64. For DIR = L, pin 41 is HVOUT 1. 11/12/01 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 5 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com