HV514 HV514 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs Features General Description ❏ HVCMOS‚ technology The HV514 is a low voltage serial to high voltage parallel converter with 8 high voltage push-pull outputs. This device has been designed to drive small capacitve loads such as piezoelectric transducers. It can also be used in any application requiring multiple high voltage outputs, medium current sourcing and sinking capabilities. ❏ Operating output voltage of 250V ❏ Low power level shifting from 5V to 250V ❏ Shift clock speed 8MHz @ VDD=5V ❏ 8 latch data outputs The device consists of an 8-bit shift register, dual 8-bit latches, and control logic to latch data, and control blanking of the outputs. Data is shifted through the shift register on the rising transition of the clock. A data output buffer is provided for cascading devices. Operation of the shift register is not affected by the /LE, SEL, or the /BL inputs. Transfer of data from the shift register to the latch occurs when the /LE is high. Shift register data is shifted to the 8-bit Data Latch when SEL is high; and shift register data is shifted to the 8-bit Polarity Latch when SEL is low. The data is held in the output latches whenever /LE is low. ❏ Output blanking ❏ CMOS compatible inputs ❏ Programmable POL latch Applications ❏ Piezoelectric transducer driver ❏ Weaving applications The high voltage output state is primarily dependent on the value in the polarity latch. If the blank, /BL, is low, the output condition is the result of a 1 being exclusively-NOR’ed with the polarity latch value. If /BL is high, the output condition is the result of the data latch being exclusively-NOR’ed with the polarity latch. ❏ Braille ❏ Printers ❏ MEMs ❏ Displays All outputs with have a break-before-make circuitry to reduce cross-over current during output state changes. Top Block Diagram Note: /LE, SEL, and /BL have internal 20k-ohm pull-up resistors. VDD 8 Level translator 8 Output control 8 2 x 8-bit latch HVOUT1 8-bit shift register DIN CLK DOUT VPP • • • • • • HVOUT8 GND LE* BL* SEL 01/19/04 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV514 DC Electrical Characteristics (Over operating supply voltages unless otherwise noted) Symbol Parameter Min Ty p Max Units 4 mA Conditions IDD VDD supply current IDDQ Quiescent VDD supply current IPP VPP supply current 10 0 µA VPP=250V, fOUT=300Hz, no load IPPQ Quiescent VPP supply current 10 0 µA VPP=240V, outputs static IIH High-level logic input current 10 µA VIH=VDD II L Low-level logic input current IDPP Dynamic IPP VOH High-level output VOL Low-level output 0.1 2 .0 -1 0 -3 5 0 0 .1 HVOUT 140 Data out mA µA mA V VDD-1V HVOUT 60 Data out 1.0 V fCLK=8MHz, LE*=LOW All VIN=VDD All VIN=0V VIL=0V VIL=0V, for inputs w/pull-up resistors fOUT=100kHz, no load VPP =200V, IHVOUT=-20mA IDOUT=-0.1mA VDD =4.5V, IHVOUT=20mA IDOUT=0.1mA AC Electrical Characteristics (Over operating supply voltages unless otherwise noted) Symbol Parameter Min fCLK Clock frequency fOUT Output switching frequency (SOA limited) Ty p 0 Max Units 8 MH z 300 Hz tW Clock width high and low 62 ns tSU Data setup time before clock rises 15 ns tH Data hold time after clock rises 30 ns tWLE Width of latch enable pulse 80 ns tDLE /LE delay time after rising edge of clock 35 ns tSLE /LE setup time before rising edge of clock 40 ns tOR, tOF Conditions CL=50nF, VPP=200V Rise/fall time of HVOUT 1000 µs td ON/OFF Delay time for output to start rise/fall 500 ns tDHL Delay time clock to DOUT high to low 110 ns CL=15pF tDLH Delay time clock to DOUT low to high 110 ns CL=15pF 5 ns TR, tF All logic inputs Absolute Maximum Ratings* CL=100nF, VPP=200V Ordering Information Supply Voltage, VDD -0.5V to 6V Device Part Number Package Die Supply Voltage, VPP 275V HV514 HV514WG 20 Lead SOW HV514X Logic input levels Ground current High voltage supply current Continuous total power dissipation Operating temperature range Storage temperature range -0.5V to VDD+0.5V 0.3A 0.25A 750mW -40?C to +85?C -65?C +150?C * All voltages are referenced to device ground. 2 HV514 Operating Supply Voltages Symbol Parameter Min Typ Max Units 5.0 5.5 V VDD Logic supply voltage 4.5 VPP High voltage supply 50 250 V VIH High-level input voltage VDD-0.9 VDD V VIL Low-level input voltage 0 0.9 V TA Operating free-air temperature -40 +85 °C Conditions Note 1 Notes: 1. Below minimum VPP the output may not switch. 2. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. Input and Output Equivalent Circuits VDD VDD 20kΩ VPP * Data Out Input GND GND Logic Inputs HVOUT HVGND Logic Data Output * BL, SEL, LE Note: There is an internal output resistor for the high voltage output pin for SOA protection 3 High Voltage Outputs HV514 Switching Waveforms VIH 50% Data Input Data Valid 50% VIL tH tSU VIH CLK 50% 50% 50% 50% tWL VIL tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL LE VIH 50% 50% VOL tWLE tDLE tSLE VOH 90% 10% HVOUT w/ S/R LOW tdOFF HVOUT w/ S/R HIGH VOL tR 10% tdON VOH 90% VOL tF /BL, /LE, and SEL hav internal 20kΩ pull-up resistors. Functional Block Diagram BL CLK DOUT 8-bit SHIFT REGISTER HVOUT1 D1 SR1 DIN • • • • • D8 SR8 8-bit DATA LATCH • • • • • LE P1 • • • • • P8 8-bit POLARITY LATCH • • • • • • • • • • • • • • • • • • • • • • • • • L/T • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • HVOUT8 L/T LE SEL LE Note: BL, SEL, and LE have internal 20kΩ pull-up resistors. 4 • • • • • • • • • • • • • • • • • • • • HV514 Function Table Inputs Outputs Function Data Load S/R CLK /LE SEL /BL H or L Latch HV Output Action 1 2....16 Data Out H or L *…* * *…* * *…* * Shift Reg 1 2....16 X X H H H or L *…* To data * *…* * X X H L H or L *…* To polarity * *…* * Hold latch data X X L * *…* * *…* * *…* * Blank Output X X X X L * *…* * *…* 1 (XNOR ) POL * Active Output X X X X H * *…* * *…* Data (XNOR ) POL * Transfer S/R to Latch /BL Latched Information HV Output Data Polarity L X L L L X H H H L L L H H L H H L H H H H H L Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition • = dependent on previous stage’s satte before the last CLK or last LE* high. 5 HV514 Pin Configuration Package Outline Pin Function 1 20 1 CLK 2 19 2 LE 3 18 3 DIN 4 17 4 LGND 5 16 5 HVGND 6 15 6 HVGND 7 HVout1 7 14 8 HVout2 8 13 9 HVout3 9 12 10 HVout4 10 11 11 HVout5 12 HVout6 13 HVout7 14 HVout8 15 VPP 16 VPP 17 VDD 18 DOUT 19 BL 20 SEL 20-Lead SOW Package (WG) WIde Body 01/19/04 ©2004 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 6 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 • FAX: (408) 222-4895 www.supertex.com