TK83854 HIGH POWER FACTOR PREREGULATOR FEATURES FEATURES (CONT.) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Control Boost PWM to 0.99 Power Factor Limit Line Current Distortion to < 5% Worldwide Operation without Switches Feed-Forward Line Regulation Low Noise Sensitivity Pin Compatible with UC2854, and UC3854 (Licensed Source) Low Start-Up Supply Current Fixed-Frequency PWM Drive Low-Offset Analog Multiplier/Divider 1 Amp Totem-Pole Gate Driver Precision Voltage Reference DESCRIPTION The TK83854 family of integrated circuits provide active power factor correction for power systems that otherwise would draw non-sinusoidal current from sinusoidal power lines. These parts implement all the control functions necessary to build a power supply preregulator capable of optimally using available power-line current while minimizing line-current distortion. To do this, the TK83854 contains a voltage amplifier, a precision analog multiplier/ divider, a current amplifier, and a fixed-frequency PWM. In addition, the TK83854 contains a power MOSFET gate driver, 7.5 V reference, line anticipator, load-enable comparator, low supply detector, and overcurrent comparator. circuitry that supplies power to this device, the TK83854 family features low start-up supply current. These devices are available in 16-pin plastic dual in-line (DIP) and 16-pin surface mount (SOP) packages. TK83854 54 838 GTDRV GND SOP-16 PKLMT CAOUT VCC ISENSE SS CT MULTOUT The TK83854 family uses average current-mode control to accomplish fixed-frequency current control with stability and low distortion. Unlike peak current-mode control, average current control accurately maintains sinusoidal line current without slope compensation. RSET IAC 3854 8 VSENSE VAOUT ENA VRMS Vref DIP-16 The TK83854's high reference voltage and high oscillator amplitude minimize noise sensitivity while fast PWM elements permit chopping frequencies above 200 kHz. The TK83854 can be used in systems with line voltages that vary from 75 to 275 V and with line frequencies across the 50 Hz to 400 Hz range. To reduce the burden on the BLOCK DIAGRAM VAOUT MULTOUT CAOUT PKLMT Vref VCC VCC IC POWER 7-5 V REF 16/10 V RUN ENA GTDRV 2.5/2.25 V ORDERING INFORMATION IM = AB C 7.5 V Tape/Reel Code Package Code B IAC VRMS 15 V A VSENSE TK83854 14 µA X2 R R C Q S SS RUN Extended Temp. Range OSC 1 PACKAGE CODE TEMP. RANGE (OPTIONAL) TAPE/REEL CODE D: DIP-16 M: SOP-16 I: -40 TO +85 C TL: Tape Left MG: Magazine January 1999 TOKO, Inc. ISENSE CT RSET GND Page 1 TK83854 ABSOLUTE MAXIMUM RATINGS Supply Voltage ......................................................... 35 V Power Dissipation TK83854D (Note 1) ..................... 1 W Power Dissipation TK83854M (Note 2) .............. 750 mW GTDRV Current (Continuous) ................................. 0.5 A GTDRV Current (50% Duty Cycle) .......................... 1.5 A Input Voltage (VSENSE, VRMS) .................................... 11 V Input Voltage (ENA, ISENSE, MULTOUT) .................. 11 V Input Voltage (PKLMT) ............................................... 5 V Input Voltage (IAC, RSET, PKLMT) ........................ 10 mA Storage Temperature Range ................... -55 to +150 °C Operating Temperature Range ...................... 0 to +70 °C Extended Temperature Range ................... -40 to +85 °C Junction Temperature .......................................... 150 °C Lead Soldering Temperature (10 s) ..................... 235 °C TK83854 ELECTRICAL CHARACTERISTICS Test conditions: VCC = 18 V, RSET = 15 k to GND, CT = 1.5 nF, PKLMT = 1 V, ENA = 7.5 V, VRMS = 1.5 V, IAC = 100 µA, VISENSE = 0 V, VOUT(CA) = 3.5 V, VOUT(VA) = 5 V, VSENSE = 7.5 V, No load on SS, CAOUT, VAOUT, Vref, GTDRV, TA = Operating Temperature Range, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 1.5 2.0 mA 10 16 mA ICC(OFF) Supply Current OFF ICC(ON) Supply Current ON UVLO(ON) VCC Turn-on Threshold 14.5 16.0 17.5 V UVLO(OFF) VCC Turn-off Threshold 9 10 11 V VENA Enable Threshold, Rising 2.40 2.55 2.70 V VENA(HYST) Enable Threshold Hysteresis 0.20 0.25 0.30 V IENA Enable Input Current ENA = 0 V -5.0 -0.2 5.0 µA IV(RMS) VRMS Input Current VRMS = 5 V -1.0 -0.01 1.0 µA 8 mV 500 nA ENA = 0 V VOLTAGE AMPLIFIER VOS(VA) Voltage Amp Offset Voltage VAOUT = 0 V IB(VA) VSENSE Bias Current -500 -25 AOL(VA) Voltage Amp Gain 70 100 dB ∆VOUT(VA) Voltage Amp Output Swing 0.5 to 5.8 V ISC(VA) Voltage Amp Short Circuit Current VAOUT = 0 V -30 -12 -5 mA ISS SS Current -20 -14 -6 µA 4 mV 500 nA SS = 2.5 V -8 CURRENT AMPLIFIER VOS(CA) Current Amp Offset Voltage IB(CA) ISENSE Bias Current -500 -120 AOL(CA) Current Amp Gain 80 110 dB ∆VOUT(CA) Current Amp Output Swing 0.5 to 16 V -4 Note 1: Power dissipation is 1 W when mounted as recommended. Derate at 8 mW/°C for operation above 25°C. Note 2: Power dissipation is 750 mW when mounted as recommended. Derate at 3.3 mW/°C for operation above 25°C. Gen. Note: All voltages with respect to GND (Pin 1). Gen. Note: All currents are positive into the specified terminal. Page 2 January 1999 TOKO, Inc. TK83854 TK83854 ELECTRICAL CHARACTERISTICS (CONT.) Test conditions: VCC = 18 V, RSET = 15 k to GND, CT = 1.5 nF, PKLMT = 1 V, ENA = 7.5 V, VRMS = 1.5 V, IAC = 100 µA, VISENSE = 0 V, VOUT(CA) = 3.5 V, VOUT(VA) = 5 V, VSENSE = 7.5 V, No load on SS, CAOUT, VAOUT, Vref, GTDRV, TA = Operating Temperature Range, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS -30 -12 -5 mA CURRENT AMPLIFIER ISC(CA) Current Amp Short Circuit Current V(ISENSE) Input Range, ISENSE, MULTOUT GBW Current Amp Gain-BW Product CAOUT = 0 V -0.3 to 2.5 V TA = 25 ° C (Note 3) 400 800 kHz Iref = 0 mA, TA = 25 ° C 7.4 7.5 7.6 V Iref = 0 mA, Over Temp. 7.35 7.50 7.65 V REFERENCE Vref Reference Voltage ∆Vref(LOAD) Vref Load Regulation -10 mA < Iref < 0 mA -15 5 15 mV ∆Vref(LINE) Vref Line Regulation 15 V < VCC < 35 V -10 2 10 mV Iref(SC) Vref Short Circuit Current Vref = 0 V -50 -28 -12 mA 10 mV PEAK LIMIT VOS(PL) PKLMT Offset Voltage -10 IB(PL) PKLMT Input Current PKLMT = -0.1 V tD(PL) PKLMT to GTDRV Prop. Delay PKLMT falling from 50 mV to -50 mV -200 -100 µA 175 ns GATE DRIVER VG(MAX) Maximum GTDRV Output Voltage 18 V < VCC < 35 V, No Load 13.0 14.5 18.0 V VGH GTDRV Output Voltage HIGH 200 mA Source, VCC = 15 V 12.0 12.8 VGL(OFF) GTDRV Output Voltage LOW, OFF 50 mA Sink, VCC = 0 V 0.9 1.5 V 200 mA Sink 1.0 2.2 V VGL GTDRV Output Voltage LOW, 10 mA Sink 0. 1 0.4 V IG(PK) Peak GTDRV Current 10 nF Load 1.0 A tR(G) / tF(G) GTDRV Rise/Fall Time 1 nF Load 35 ns DMAX GTDRV Maximum Duty Cycle CAOUT = 7 V 95 % V Note 3: Guaranteed by design; not 100% tested. Gen Note: ENA input is internally clamped to approximately 14 V. January 1999 TOKO, Inc. Page 3 TK83854 TK83854 ELECTRICAL CHARACTERISTICS (CONT.) Test conditions: VCC = 18 V, RSET = 15 k to GND, CT = 1.5 nF, PKLMT = 1 V, ENA = 7.5 V, VRMS = 1.5 V, IAC = 100 µA, VISENSE = 0 V, VOUT(CA) = 3.5 V, VOUT(VA) = 5 V, VSENSE = 7.5 V, No load on SS, CAOUT, VAOUT, Vref, GTDRV, TA = Operating Temperature Range, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LIMITED) IAC = 100 µA, RSET = 10 k -220 -200 -180 µA Multiplier Output Current Zero IAC = 0 µA, RSET = 15 k -2.0 -0.2 2.0 µA Multiplier Output Current (RSET IAC = 450 µA, RSET = 15 k, VRMS = 1 V, VA = 6 V -280 -255 -220 µA IAC = 50 µA, VRMS = 2 V, VA = 4 V -50 -42 -33 µA IAC = 100 µA, VRMS = 2 V, VA = 2 V -38 -27 -12 µA IAC = 200 µA, VRMS = 2 V, VA = 4 V -165 -150 -105 µA IAC = 300 µA, VRMS = 1 V, VA = 2 V -250 -225 -150 µA IAC = 100 µA, VRMS = 1 V, VA = 2 V -95 -80 -60 µA MULTIPLIER IOM(IAC) IOM(ZC) IOM(SET) I OM K Multiplier Output Current (IAC LIMITED) Multiplier Output Current Multiplier Gain Current (Note 4) -1.0 V OSCILLATOR RSET = 15 k 46 55 62 kHz RSET = 8.2 k 86 102 118 kHz CT Ramp Peak-to-Peak Amplitude 4. 9 5.4 5.9 V CT Ramp Valley Voltage 0.8 1.1 1.3 V fOSC Oscillator Frequency VRP VRV Note 4: Multiplier gain constant (K) is defined by IOM = [K x IIAC x (VOUT(VA) - 1)] / VRMS2. Page 4 January 1999 TOKO, Inc. TK83854 TEST CIRCUIT GND PKLMT 0.1 nF 0.39 nF GTDRV PKLMT VCC CAOUT CT NC 1.0 nF VCC 1.0 nF NC 0.01 nF ISENSE CAOUT 10 k 100 MULT 10 k IM = (AB) / C 10 nF IAC IAC MULTOUT NC 10 k VAOUT SS 7.5 V B A 8.2 k RSET 10 k 15 k VSENSE C VAOUT ENA V RMS Vref 100 ENA NC 10 k 10 k 10 µF 10 nF 0.1 µF VRMS TYPICAL PERFORMANCE CHARACTERISTICS 120 PHASE MARGIN 100 80 60 40 20 OPEN LOOP GAIN 0 -20 0.1 1 10 100 1000 10000 VOLTAGE AMPLIFIER GAIN AND PHASE vs. FREQUENCY 120 100 PHASE MARGIN 100 95 80 60 40 20 -20 0.1 70 1 10 100 1000 10000 0 10 100 FREQUENCY (kHz) RSET (kΩ) MULTIPLIER OUTPUT vs. VOLTAGE ON MULTIPLIER OSCILLATOR FREQUENCY VS. RSET AND CT GATE DRIVE RISE AND FALL TIMES vs. LOAD CAPACITANCE 700 MULTOUT = 2 V MULTOUT = 3 V 200 100 200 pF 500 pF 10 1 nF 2 nF 200 400 IAC (µA) January 1999 TOKO, Inc. 600 800 1 1 10 nF tR(G) / tF(G) (ns) MULTOUT = 1 V FREQUENCY (kHz) 100 pF MULTOUT = 0 V MULTOUT (µA) 80 75 1000 0 85 OPEN LOOP GAIN 0 VAOUT = 5 V V(rms) = 2 V 400 90 FREQUENCY (kHz) 600 0 GATE DRIVE MAXIMUM DUTY CYCLE vs. RSET DUTY CYCLE (%) CURRENT AMPLIFIER GAIN AND PHASE vs. FREQUENCY AOL(VA) (dB)AND PHASE MARGIN ( ) AOL(CA) (dB)AND PHASE MARGIN ( ) TA = TJ = 25 °C FALL TIME 500 RISE TIME 300 100 5 nF 3 nF 10 RSET (kΩ) 100 0 .01 .02 .03 .04 .05 CLOAD (µF) Page 5 TK83854 TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) TA = TJ = 25 °C VAOUT = 5 V 150 VAOUT = 3 V 100 VAOUT = 2 V 120 VAOUT = 5 V VAOUT = 4 V 80 VAOUT = 3 V VAOUT = 2 V VAOUT = 1.25 V 0 100 200 300 IAC (µA) Page 6 400 500 100 VAOUT = 5 V VAOUT = 3 V 60 40 50 0 MULTIPLIER OUTPUT vs. MULTIPLIER INPUT (MULTOUT = 0 V) 140 V(rms) = 5 V MULT OUT (µA) 200 MULTIPLIER OUTPUT vs. MULTIPLIER INPUT (MULTOUT = 0 V) 160 V(rms) = 4 V MULT OUT (µA) MULT OUT (µA) MULTIPLIER OUTPUT vs. MULTIPLIER INPUT (MULTOUT = 0 V) 300 V(rms) = 3 V 250 0 VAOUT = 1.25 V 20 VAOUT = 1.25 V 0 100 200 300 IAC (µA) 400 500 0 100 200 300 400 500 IAC (µA) January 1999 TOKO, Inc. TK83854 PIN DESCRIPTION GROUND PIN (GND) All voltages are measured with respect to GND. VCC and Vref should be bypassed directly to GND with a 0.1 µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to GND should also be as short and as direct as possible. PEAK LIMIT (PKLMT) The threshold for PKLMT is GND. Connect this input to the negative voltage on the current sense resistor as shown in Figure 1. Use a resistor to Vref to offset the negative current sense signal up to GND. CURRENT AMPLIFIER OUTPUT (CAOUT) This is the output of a wide-bandwidth op-amp that senses line current and commands the Pulse Width Modulator (PWM) to force the correct current. This output can swing close to GND, allowing the PWM to force zero duty cycle when necessary. The current amplifier will remain active even if the IC is disabled. CURRENT SENSE MINUS (ISENSE) This is the inverting input to the current amplifier. This input and the non-inverting input MULTOUT remain functional down to and below GND. Care should be taken to avoid taking these inputs below –0.5 V, because they are protected with diodes to GND. MULTIPLIER OUTPUT AND CURRENT SENSE PLUS (MULTOUT) The output of the analog multiplier and the non-inverting input of the current amplifier are connected together at MULTOUT. The cautions about taking ISENSE below –0.5 V also apply to MULTOUT. As the multiplier output is a current, this is a high impedance input similar to ISENSE, so the current amplifier can be configured as a differential amplifier to reject GND noise. Figure 1 shows an example of using the current amplifier differentially. be used for sensing instantaneous line voltage. The nominal voltage on IAC is 6 V, so in addition to a resistor from IAC to rectified line, connect a resistor from IAC to Vref. If the resistor to Vref is one-fourth of the value of the resistor to the rectifier, then the 6 V offset will be cancelled, and the line current will have minimal crossover distortion. VOLTAGE AMPLIFIER OUTPUT (VAOUT) This is the output of the op-amp that regulates output voltage. Like the current amplifier, the voltage amplifier will also stay active even if the IC is disabled with either ENA or VCC. This means that large feedback capacitors across the amplifier will stay charged through momentary disable cycles. Voltage amplifier output levels below ~1 V will inhibit multiplier output. RMS LINE VOLTAGE (V(rms)) The output of a boost PWM is proportional to the input voltage, so when the line voltage into a low-bandwidth boost PWM voltage regulator changes, the output will change immediately and slowly recover to the regulated level. For these devices, the V(rms) input compensates for line voltage changes if it is connected to a voltage proportional to the RMS input line voltage. For best control, the VRMS voltage should stay between 1.5 V and 3.5 V. VOLTAGE REFERENCE OUTPUT (Vref) Vref is the output of an accurate 7.5 V voltage reference. This output is capable of delivering 10 mA to peripheral circuitry and is internally short circuit current limited. Vref is disabled and will remain at 0 V when VCC is low or when ENA is low. Bypass Vref to GND with a 0.1 µF or larger ceramic capacitor for best stability. ENABLE (ENA) ENA is a logic input that will enable the PWM output, voltage reference, and oscillator. ENA also will release the soft start clamp, allowing SS to rise. When unused, connect ENA to a +5 V supply or pull ENA high with a 22 k resistor. The ENA pin is not intended to be used as a high-speed shutdown to the GTDRV output. INPUT AC CURRENT (IAC) This input to the analog multiplier is a current. The multiplier is tailored for very low distortion from this current input (IAC to MULTOUT), so this is the only multiplier input that should January 1999 TOKO, Inc. Page 7 TK83854 PIN DESCRIPTION (CONT.) VOLTAGE AMPLIFIER INVERTING OUTPUT (VSENSE) This is normally connected to a feedback network and to the boost converter output through a divider network. interaction between the gate impedance and the GTDRV output driver that might cause the GTDRV output to overshoot excessively. Some overshoot of the GTDRV output is always expected when driving a capacitive load. OSCILLATOR CHARGING CURRENT AND MULTIPLIER LIMIT SET (RSET) A resistor from RSET to ground will program oscillator charging current and maximum multiplier output. Multiplier output current will not exceed 3.75 V divided by the resistor from RSET to ground. SOFT-START (SS) SS will remain at GND as long as the IC is disabled or VCC is too low. SS will pull up to over 8 V by an internal 14 µA current source when both VCC becomes valid and the IC is enabled. SS will act as the reference input to the voltage amplifier if SS is below Vref. With a large capacitor from SS to GND, the reference to the voltage regulating amplifier will rise slowly, and increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS will quickly discharge to ground and disable the PWM. OSCILLATOR TIMING CAPACITOR (CT ) A capacitor from CT to GND will set the PWM oscillator frequency according to this relationship: fOSC = 1.25 / (RSET x CT) POSITIVE SUPPLY VOLTAGE (VCC) Connect VCC to a stable source of at least 20 mA above 17 V for normal operation. Also bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate GTDRV signals, these devices will be inhibited unless VCC exceeds the upper undervoltage lockout threshold and remains above the lower threshold. GATE DRIVER (GTDRV) The output of the PWM is a totem pole MOSFET gate driver on GTDRV. This output is internally clamped to 15 V so the IC can be operated with VCC as high as 35 V. Use a series gate resistor of at least 5 ohms to prevent Page 8 January 1999 TOKO, Inc. TK83854 APPLICATION INFORMATION A 250 W PREREGULATOR Soft-Start (SS) Figure 1 shows a typical application of the TK83854 as a preregulator with high power factor and efficiency. The assembly consists of two distinct parts, the control circuit centering on the TK83854 and the power section. The voltage at Pin 13 (SS) can reduce the reference voltage used by the error amplifier to regulate the output DC voltage. With Pin 13 open, the reference voltage is typically 7.5 V. An internal current source delivers approximately 14 µA from Pin 13. Thus, a capacitor connected between that pin and GND will charge linearly from zero to 7.5 V in 0.54 x C seconds, with C expressed in microfarads. The power section is a "boost" converter, with the inductor operating in the continuous mode. In this mode, the duty cycle is dependent on the ratio between input and output voltages. Also, the input current has low switching frequency ripple, which means that the line noise is low. Furthermore, the output voltage must be higher than the peak value of the highest expected AC line voltage, and all components must be rated accordingly. In the control section, the TK83854 provides PWM pulses to the power MOSFET gate (GTDRV, Pin 16). The duty cycle of this output is simultaneously controlled by four separate inputs to the chip: INPUT VSENSE IAC ISENSE /MULTOUT VRMS PIN # 11 6 4/5 8 FUNCTION Output DC Voltage Line Voltage Waveform Line Current RMS Line Voltage Additional controls of an auxiliary nature are provided. They are intended to protect the switching power MOSFET from certain transient conditions, as follows: INPUT ENA SS PKLMT PIN # 10 13 2 FUNCTION Start-up Delay Soft Start Maximum Current Limit PROTECTION INPUTS Enable (ENA) The ENA input must reach 2.5 V before the V ref and GTDRV outputs are enabled. This provides a means to shut down the gate in case of trouble, or to add a time delay at power up. A hysteresis gap of 200 mV is provided at this terminal to prevent erratic operation. Undervoltage protection is provided directly at Pin 15, where the on/off thresholds are 16 V and 10 V, respectively. January 1999 TOKO, Inc. Peak Current Limit (PKLMT) Use Pin 2 to establish the highest value of current to be controlled by the power MOSFET. With the resistor divider values shown in Figure 1, the 0.0 V threshold at Pin 2 is reached when the voltage drop across the 0.25 Ω current sense resistor is 7.5 V x 1.6 k / 10 k = 1.2 V, corresponding to 4.8 A. A bypass capacitor from Pin 2 to ground is recommended to filter out very high frequency noise. CONTROL INPUTS Output DC Voltage Sense (VSENSE) The threshold voltage for the VSENSE input is 7.5 V and the input bias current is typically -10 nA. The values shown in Figure 1 are for an output voltage of 400 VDC. In this circuit, the voltage amplifier operates with a constant low frequency gain for minimum output excursions. The 0.047 µF feedback capacitor places a 15 Hz pole in the voltage loop that prevents 120 Hz ripple from propagating to the output current. Line Waveform (IAC) In order to force the line current waveshape to follow the line voltage, a sample of the power line voltage waveform is introduced at Pin 6. This signal is multiplied by the output of the voltage amplifier in the internal multiplier to generate a reference signal for the current control loop. This input is not a voltage, but a current (hence IAC). It is set up by the 220 k and 910 k resistive divider (see Figure 1). The voltage at pin 6 is internally held at 6 V, and the two resistors are chosen so that the current flowing into pin 6 varies from zero (at each zero crossing) to about 400 µA at the peak of the waveshape. The following formulas were Page 9 TK83854 APPLICATION INFORMATION (CONT.) used to calculate these resistors: RIAC = VPK(MAX) / 400 E - 6 With RSET = 15 k: IOM(MAX) = -3.75 V / 15 k = -250 µA = (260 VAC x 2 ) / 400 µA = 910 k RREF = RIAC / 4 = 220 k where VPK is the peak line voltage. It is also important to note that the multiplier output current will never exceed twice IAC. With the 3.9 k resistor from MULTOUT to the 0.25 Ω current sense resistor, the maximum current in the current sense resistor will be: Line Current (ISENSE/MULTOUT ) The voltage drop across the 0.25 Ω current-sense resistor is applied to Pins 4 and 5 as shown. The current-sense amplifier also operates with high low-frequency gain, but unlike the voltage amplifier, it is set up to give the currentcontrol loop a very wide bandwidth. This enables the line current to follow the line voltage as closely as possible. In the present example, this amplifier has a zero at about 500 Hz, and a gain of about 18 dB thereafter. RMS Line Voltage (VRMS) IRCS(MAX) = (-IOM(MAX) x 3.9 k) / 0.25 Ω = -3.9 A Having selected RSET, the current sense resistor, and the resistor from MULTOUT to the current sense resistor, calculate CT for the desired PWM oscillator frequency from the equation: CT = 1.25 / (f OSC x RSET) An important feature of the TK83854 preregulator is that it can operate with a three-to-one range of input line voltages, covering everything from low line in Japan (85 VAC) to high line in Europe (255 VAC). This is done using line feedforward, which keeps the input power constant with varying input voltage (assuming constant load power). To do this, the multiplier divides the line current by the square of the rms value of the line voltage. The voltage applied to Pin 8, proportional to the average of the rectified line voltage (and proportional to the RMS value), is squared in the TK83854, and then used as a divisor by the multiplier block. The multiplier output, at Pin 5, is a current that increases with the current at Pin 6 and the voltage at Pin 7, and decreases with the square of the voltage at pin 8. PWM Frequency The PWM oscillator frequency in Figure 1 is 100 kHz. This value is determined by CT at Pin 14 and RSET at Pin 12. RSET should be chosen first because it affects the maximum value of IOM according to the equation: IOM(MAX) = -3.75 V / RSET This effectively sets a maximum PWM-controlled current. Page 10 January 1999 TOKO, Inc. TK83854 APPLICATION INFORMATION (CONT.) D9 BR 1KBU8J F1 6A ~ C1 0.47 µF ~ TH1 KC015L D2 MUR860 Q1 IRF840 1N5406 + C5 0.47 µF L1 1 mH R1 Q2 Q3 ZVN4206A D5 1N4148 D3 20 D13 1N4148 R2 3.9 K R7 C14 0.1 µF C15 680 pF C13 D7 68 pF 1N5817 240 K C17 0.1 µF R4 1.6 K D12 MUR110 C3 270 pF R6 24 K D8 1N5817 C6 0.047 µF R20 3K C4 1 µF R29 10 K D10 1N4737 R27 16 V VAOUT VCC R8 910 K IC POWER MULTOUT 7-5 V REF ISENSE RUN ENA 2.5 V R12 27 K R28 220 K VCC Vref PKLMT 8.2 M R13 75 K VOUT 385 VDC R16 TIP50GE D11 MUR110 1N4746A R25 910 K R18 10 K R3 3.9 K R22 30 K R23 470 K 24 K R17 511 K C2 330 µF 0.25 R21 + D4 1N5821 AB IM = C 7.5 V VSENSE 15 V A GTDRV IAC B VRMS R9 91 K SS 14 µA X2 R R S C ILIMIT Q RUN R10 20 K OSC + C12 0.1 µF C16 1 µF C7 0.47 µF C9 220 µF C10 0.01 µF CT C11 1000 pF RSET GND 1 R14 15 k FIGURE 1: 250 W PREREGULATOR January 1999 TOKO, Inc. Page 11 TK83854 PACKAGE OUTLINE 0.76 Marking Information 1.7 SOP-16 9 e1 9.53 16 7.5 TK83854 e Marking 83854 1.27 Recommended Mount Pad 1 8 e 0.1 1.27 0 ~ 10 0.25 0.12 Ç l +0.15 -0.05 +0.15 -0.05 0.4 0.7 0 ~ 0.3 2.3 2.8 max 10.3 Dimensions are shown in millimeters Tolerance: x.x = ± 0.2 mm (unless otherwise specified) + 0.3 10.3 Marking 16 9 1 8 6.35 DIP-16 Country of Origin Lot Number + 0.3 4.2 + 0.3 3.2 0.5 min 3.3 19.05 e 2.54 0.5 +0.15 -0.05 0.25 e1 0.25 M 15 7.62 0~ Dimensions are shown in millimeters Tolerance: x.x = ± 0.2 mm (unless otherwise specified) Toko America, Inc. Headquarters 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 TOKO AMERICA REGIONAL OFFICES Midwest Regional Office Toko America, Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 Western Regional Office Toko America, Inc. 2480 North First Street , Suite 260 San Jose, CA 95131 Tel: (408) 432-8281 Fax: (408) 943-9790 Eastern Regional Office Toko America, Inc. 107 Mill Plain Road Danbury, CT 06811 Tel: (203) 748-6871 Fax: (203) 797-1223 Semiconductor Technical Support Toko Design Center 4755 Forge Road Colorado Springs, CO 80907 Tel: (719) 528-2200 Fax: (719) 528-2375 Visit our Internet site at http://www.tokoam.com The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc. Page 12 © 1999 Toko, Inc. All Rights Reserved January 1999 TOKO, Inc. IC-167-TK83854 0798O0.0K Printed in the USA