UCC1857 UCC2857 UCC3857 Isolated Boost PFC Preregulator Controller PRELIMINARY FEATURES DESCRIPTION • PFC With Isolation, VO < VIN The UCC3857 provides all of the control functions necessary for an Isolated Boost PFC Converter. These converters have the advantage of transformer isolation between primary and secondary, as well as an output bus voltage that is lower than the input voltage. By providing both power factor correction and down conversion in a single power processing stage, the UCC3857 is ideal for applications which require high efficiency, integration, and performance. • Single Power Stage • Zero Current Switched IGBT • Programmable ZCS Time • Corrects PF to >0.99 • Fixed Frequency, Average Current Control The UCC3857 brings together the control functions and drivers necessary to generate overlapping drive signals for external IGBT switches, and provides a separate output to drive an external power MOSFET which provides zero current switching (ZCS) for both the IGBTs. Full programmability is provided for the MOSFET driver delay time with an external RC network. ZCS for the IGBT switches alleviates the undesirable turn off losses typically associated with these devices. This allows for higher switching frequencies, smaller magnetic components and higher efficiency. The power factor correction (PFC) portion of the UCC3857 employs the familiar average current control scheme used in previous Unitrode controllers. Internal circuitry changes, however, have simplified the design of the PFC section and improved performance. • Improved RMS Feedforward • Soft Start • 9V to 18V Supply V Range • 20-Pin DW, N, J, and L Packages (continued) TYPICAL APPLICATION CIRCUIT + T1 CF RECTIFIED AC INPUT BIAS SUPPLY QA Q1 VOUT Q2 – RS REF FEEDBACK CKT ZC OPTO RAC 13 3 7 PKLMT MOUT 1 2 10 8 CA– 4 CAO VIN VD IAC CRMS UCC3857 VA– ZV REF 15 11 VAO 5 VREF MOSDRV 14 IGDRV1 16 IGDRV2 18 DELAY 12 SS RT CT PGND AGND 20 19 20 17 6 REF UDG-98065 02/99 UCC1857 UCC2857 UCC3857 ABSOLUTE MAXIMUM RATINGS DESCRIPTION (continued) Input Supply Voltage (VIN, VD) . . . . . . . . . . . . . . . . . . . . . . 18V General Analog/Logic Inputs (CRMS, MOUT, CA–, VA–, CT, RT, PKLMT) (Maximum Forced Voltage). . . . . . . . . . . . . . . . –0.3V to 5V IAC (Maximum Forced Current) . . . . . . . . . . . . . . . . . . . 300µA Reference Output Current . . . . . . . . . . . . . . . Internally Limited Output Current (MOSDRV, IGDRV1, IGDRV2) Pulsed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . −55°C to +150°C Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . +300°C Controller improvements include an internal 6 bit A-D converter for RMS input line voltage detection, a zero load power circuit, and significantly lower quiescent operating current. The A-D converter eliminates an external 2 pole low pass filter for RMS detection. This simplifies the converter design, eliminates 2nd harmonic ripple from the feedforward component, and provides an approximate 6 times improvement in input line transient response. The zero load power comparator prevents energy transfer during open load conditions without compromising power factor at light loads. Low startup and operating currents which are achieved through the use of Unitrode's BCDMOS process simplify the auxiliary bootstrap supply design. Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of the specified terminal. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 s. Consult Packaging Section of Databook for thermal limitations and considerations of packages. Additional features include: under voltage lockout for reliable off-line startup, a programmable over current shutdown, an auxiliary shutdown port, a precision 7.5V reference, a high amplitude oscillator ramp for improved noise immunity, softstart, and a low offset analog square, multiple and divide circuit. Like previous Unitrode PFC controllers, worldwide operation without range switches is easily implemented. CONNECTION DIAGRAMS DIL-20, SOIC- 20 (Top View) J, N and DW Packages IAC 1 PLCC-20 (Top View) L Package 20 CT IAC CRMS MOUT CRMS 2 19 RT MOUT 3 18 IGDRV2 VIN 4 17 PGND VREF 5 16 IGDRV1 AGND 6 15 VD CA– 7 14 MOSDRV CAO 8 13 PKLMT SS 9 12 DELAY VA– 10 11 VAO CT RT 3 1 20 19 VIN 4 18 IGDRV2 VREF 5 17 PGND AGND 6 16 IGDRV1 CA– 7 15 VD CAO 8 14 MOSDRV 9 SS VA– 2 2 10 11 12 13 PKLMT DELAY VAO UCC1857 UCC2857 UCC3857 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0°C to 70°C for the UCC3857, –40°C to +85°C for the UCC2857, and –55°C to +125°C for the UCC1857, VVIN, VVD = 12V, RT = 19.2K, CT = 680pF. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Supply Supply Current, Active No Load on Outputs, VVD = VVIN 3.5 5 mA Supply Current, Startup No Load on Outputs, VVD = VVIN 60 TBD µA VIN UVLO Threshold 13.75 15.5 V 3 3.75 TBD V TJ = 25°C, IREF = 1mA 7.387 7.5 7.613 V Over Temperature, UCC3857 7.368 7.5 7.631 V Over Temperature, UCC1857, UCC2857 7.313 7.5 7.687 V UVLO Threshold Hysteresis Reference Output Voltage (VVREF) Load Regulation IREF = 1mA to 10mA 2 10 mV Line Regulation VVIN = VVD = 12V to 16V 2 15 mV Short Circuit Current VVREF = 0V –55 –30 mA 0 3 mV Current Amplifier Input Offset Voltage (Note 1) Input Bias Current (Note 1) –3 Input Offset Current (Note 1) 25 nA CMRR VCM = 0V to 1.5V, VCAO = 3V 80 dB –50 nA AVOL VCM = 0V, VCAO = 2V to 5V 65 85 dB VOH Load on CAO = 50µA, VMOUT = 1V, VCA– = 0V 6 7 V VOL Load on CAO = 50µA, VMOUT = 0V, VCA– = 1V Maximum Output Current Source : VCA– = 0V, VMOUT = 1V, VCAO = 3V Gain Bandwidth Product 0.2 V –150 µA Sink : VCA– = 1V, VMOUT = 0V, VCAO = 3V 5 30 fIN = 100kHz, 10mV p – p 3 5 2.9 3 50 mA MHz Voltage Amplifier Input Voltage Measured on VVA–, VVAO = 3V Input Bias Current Measured on VVA–, VVAO = 3V –50 nA AVOL VVAO = 1V to 5V 75 dB VOH Load on VVAO= –50µA, VVA–= 2.8V VOL Load on VVAO= 50µA, VVA–= 3.2V Maximum Output Current Source: VVA– = 2.8V, VVAO = 3V Sink: VVA– = 3.2V, VVAO= 3V 5.3 3.1 V 5.55 5.7 V 0.1 0.45 V –20 –12 –5 mA 5 20 30 mA 42.5 50 57.5 kHz 40 50 60 kHz Oscillator Initial Accuracy TJ = 25°C Voltage Stability VVIN = 12V to 18V 1 CT Ramp Peak-Valley Amplitude 4 CT Ramp Valley Voltage 4.5 % 5 V 1.5 V 10 V Output Drivers VOH IL = –100mA 9 VOL IL = 100mA 0.1 0.5 V Rise Time CLOAD = 1nF 25 TBD ns Fall Time CLOAD = 1nF 10 TBD ns 2 2.4 µs Trailing Edge Delay Delay Time RD = 12k, CD = 200pF, VVAO = 4V 3 1.6 UCC1857 UCC2857 UCC3857 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0°C to 70°C for the UCC3857, –40°C to +85°C for the UCC2857, and –55°C to +125°C for the UCC1857, VVIN, VVD = 12V, RT = 19.2K, CT = 680pF. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Soft Start Charge Current Shutdown Comparator Threshold µA 10 Measured on SS 0 0.4 V Multiplier Output Current, IAC Limited IAC = 100µA, VVAO = 5.5V, VCRMS = 0V Output Current, Power Limited IAC = 100µA, VVAO = 5.5V, VCRMS = 1V Output Current, Zero IAC = 0 µA –200 –2 Gain Constant µA –200 0 2.5 2 µA 1/V Zero Power, Peak Current Zero Power Comparator Threshold Measured on VAO Peak Current Limit Comparator Threshold Measured on PKLMT 0.5 V 0 V Note 1: Common mode voltages = 0V, VCAO = 3V PIN DESCRIPTIONS IAC: A resistor is connected to the rectified AC input line voltage from IAC. This provides the internal multiplier and the RMS detector with instantaneous line voltage information. AGND: Reference point of the internal reference and all thresholds, as well as the return for the remainder of the device except for the output drivers. CA–: Inverting input of the inner current loop error amplifier. IGDRV1: Driver output for one of the two external IGBT power switches. CAO: Output of the inner current loop error amplifier. This output can swing between approximately 0.2V and 6V. It is one of the inputs to the PWM comparator. IGDRV2: Driver output for one of the two external IGBT power switches. VAO: This is the output of the voltage loop error amplifier. It is internally clamped to approximately 5.6V by the UCC3857 and can swing as low as approximately 0.1V. Voltages below 0.5V on VAO will disable the MOSDRV output and force the IGDRV1 and IGDRV2 outputs to a zero overlap condition. MOSDRV: Driver output for the external power MOSFET switch. CRMS: A capacitor is connected between CRMS and ground to average the AC line voltage over a half cycle. CRMS is internally connected to the RMS detection circuitry. PKLMT: Inverting input of the peak current limit comparator. The threshold for this comparator is nominally set to 0V. The peak limit comparator terminates the MOSDRV, IGDRV1 and IGDRV2 outputs when tripped. CT: A capacitor (low ESR, ESL) is tied between CT and ground to set the ramp generator switching frequency in conjunction with RT. The ramp generator frequency is approximately given by: PGND: Return for all high level currents, internally tied to the output driver stages of the UCC3857. f SW ≈ MOUT: Output of the analog multiply and divide circuit. The output current from MOUT is fed into a resistor to the return leg of the input bridge. The resultant waveform forms the sine reference for the current error amplifier. RT: A resistor, RT is tied between RT and ground to set the charging current for the internal ramp generator. The UCC3857 provides a temperature compensated 3.0V at RT. The oscillator charging current is therefore: 3.0V/RT. Current out of RT should be limited to 250µA for best performance. 0.67 . RT • CT DELAY: A resistor to VREF and a capacitor to AGND are connected to DELAY to set the overlap delay time for the MOSDRV output stage. The overlap delay function can be disabled by removing the capacitor to AGND. VA–: This is the feedback input for the outer voltage control loop. An external opto isolator circuit provides the 4 UCC1857 UCC2857 UCC3857 PIN DESCRIPTIONS (continued) output voltage regulation information to VA– across the isolation barrier. VIN can be isolated from each other with an RC lowpass filter for better supply noise rejection. SS: A capacitor is connected between SS and GND to provide the UCC3857 soft start feature. The voltage on VAO, is clamped to approximately the same voltage as SS. An internal 10µA (nominal) current source is provided by the UCC3857 to charge the soft start capacitor. VIN: Input voltage supply to the UCC3857. This voltage must be limited to less than 18VDC. The UCC3857 is enabled when the voltage on VIN exceeds 13.75V (nominal). VREF: Output of the precision 7.5V reference. A 0.01µF to 0.1µF low ESR, ESL bypass capacitor is recommended between VREF and AGND for best performance. VD: Positive supply rail for the three output driver stages. The voltage applied to VD must be limited to less than 18VDC. VD should be bypassed to PGND with a 0.1µF to 1.0µF low ESR, ESL capacitor for best results. VD and VCT (PIN 20) & VCAO (PIN 8) CLOCK (INTERNAL) TOGGLE F/F Q (INTERNAL) IGDRV1 (PIN 16) IGDRV2 (PIN 18) TD1 MOSDRV (PIN 14) UDG-98217 Figure 1. Typical control circuit timing diagram. APPLICATION INFORMATION UCC3857 is designed to provide a solution for single stage power factor correction and step-down or step-up function, using an isolated boost converter. The Typical Application Circuit shows the implementation of a typical isolated boost converter using IGBTs as main switches in push-pull configuration and using a MOSFET as an auxiliary switch to accomplish soft-switching of IGBTs. Many variations of this implementation are possible including bridge-type circuits. The presense of low frequency ripple on the output makes this approach practical for distributed bus applications. It will not provide the highly regulated low ripple outputs typically required by logic level supplies. The circuit shown in the Typical Application Circuit provides several advantages over a more conventional approach of deriving a DC bus voltage from AC line with power factor correction. The conventional approach uses two power conversion stages and has higher cost and complexity. With the use of UCC3857, the dual functionality of power factor correction and voltage step-down is combined into a single stage. The power stage comprises a current-fed push-pull converter where the ON times of the push-pull switches (Q1 and Q2) are overlapped to provide effective duty cycle of a conventional PWM boost converter. When only one switch is on, the power is transferred to the output 5 UCC1857 UCC2857 UCC3857 APPLICATION INFORMATION (continued) BLOCK DIAGRAM VIN 4 1 CRMS 2 RMS DETECT AND CONDITIONING X ÷ X VOLTAGE AMP VA– MOUT CAO DELAY VD 5 3 8 12 15 7.5V REF UVLO 13.75V / 10V IAC VREF ENBL REF GOOD TRAILING EDGE DELAY PWM COMP CURRENT AMP MULT PEAK LIMIT COMP R ZERO POWER R 10 3.0V S 0.5V Q TOGGLE F/F Q SD 1.0V ALWAYS ON 11 CA– 7 SD IGDRV1 18 IGDRV2 VD DRIVER SD OSCILLATOR VAO 16 VD DRIVER 9 ENBL MOSDRV Q PWM LATCH 10µA SS 14 DRIVER R 17 PGND 6 13 19 20 PKLMT RT CT AGND UDG-98218 through the transformer and the output rectifier. It can be seen that the¸÷ operation on the primary side of the circuit is that of a boost converter and UCC3857 provides input current programming using average current mode control to achieve unity power factor. The transformer turns ratio can be used to get the required level of output voltage (higher or lower than the peak line voltage). The transformer also provides galvanic isolation for the output voltage. (TD1) effectively adds to the boost inductor charge period. The voltage stress of the MOSFET is half the stress of the IGBTs under normal operating conditions. However, QA can see much higher voltage stress under start-up and short circuit conditions as the converter operates in a flyback mode then. For different operating requirements or constraints (e.g. single North American line operation), the choice of switching components may be different (e.g. MOSFETs for Q1 and Q2 and no QA) as the voltage stress is different. In that case, UCC3857 can still be used without using the MOSDRV output. Power stage optimization involves design and selection of components to meet the performance and cost objectives. These include the power switches, transformer and inductor design. Transformer design is very critical in this topology. The push-pull transformer must have minimal leakage inductance between the primary and secondary windings. Similarly, the leakage between the two primary windings must be minimized. In practice, it is hard to achieve both targets without using sophisticated construction techniques such as interleaving, use of foils etc. In many cases, it may be beneficial to use a planar transformer to achieve these objectives. The effects of higher leakage inductance include higher voltage stresses, ringing, power losses and loss of available duty cycle. The high voltage levels make it difficult to design effective snubber circuits for this leakage induced ringing. The choice of IGBTs is based on their advantage over MOSFETs at higher voltages. For universal line operation, the voltage stress on the push-pull switches can approach 1000V. However, the slow turn-off of IGBTs can contribute high switching losses and the use of MOSFET (QA) helps turn the IGBTs off with zero voltage across them (ZCS turn-off). This is accomplished by keeping QA on (beyond the turn-off of Q1 or Q2 – see Fig. 1 for waveforms) to allow the inductor current to divert from IGBT to MOSFET while the IGBT is turning off and still maintain zero volts. The MOSFET delay time 6 UCC1857 UCC2857 UCC3857 APPLICATION INFORMATION (cont.) error amplifier output. Unlike prior techniques of RMS voltage sensing, UCC3857 employs a patent pending technique to simplify the RMS voltage generation and eliminate performance degradation caused by the previous techniques. With the novel technique (shown in Fig. 3), need for external 2-pole filter for VRMS generation is eliminated. Instead, the IAC current is mirrored and used to charge an external capacitor (CCRMS) during a half cycle. The voltage on CRMS takes the integrated sinusoidal shape and is given by equation 2. At the end of the half-cycle, CRMS voltage is held and converted into a 6-bit digital word for further processing in the ACU. CCRMS is discharged and readied for integration during next half cycle. The design of the boost inductor is very similar to the conventional boost converter. However, as shown in the Typical Application Circuit, an additional winding connected to the output through a diode is required on the boost inductor. This winding must have the same turns ratio as the transformer and meet the isolation requirements. This winding is required to provide a discharge path for the inductor energy when the push-pull switches are both off. During start-up, when the output voltage is zero, the converter can see very high inrush currents. The overcurrent protection circuit of UCC3857 will shut down all the outputs when the set threshold is crossed. At that instance, the boost inductor auxiliary winding directs the energy to the output. This is a preferred manner of bringing the output voltage up to prevent the main switches from handling the high levels of inrush current. However, when the auxiliary winding is transferring the power to the output, the voltage stress across QA becomes input voltage plus the reflected output voltage–higher than its steady state value of reflected output voltage. The advantage of this method is that the second harmonic ripple on the VRMS signal is virtually eliminated. Such second harmonic ripple is unavoidable with the limited roll-off of a conventional 2-pole filter and results in 3rd harmonic distortion in the input current signal. The dynamic response to the input line variations is also improved as a new VRMS signal is generated every cycle. Chip Bias Supply and Start-up VCRMS = UCC3857 is implemented using Unitrode’s BCDMOS process which allows minimization of the start-up (60 A typical) and operating (3.5mA typical) supply currents. It results in significantly lower power consumption in the trickle charge resistor used to start-up the IC. VCRMS ( pk ) = The oscillator of UCC3857 is designed to have a wide ramp amplitude (4.5V p–p) for higher noise immunity. The CT pin has the sawtooth waveshape and during the discharge time of CT, a clock pulse is generated. During the discharge period, the effective internal impedance to GND is 600 . Based on this, the discharge time is given by 831•CT. As shown in the waveforms of Fig. 1, the internal clock pulse width is equal to the discharge time and that sets the minimum dead time between IGDRV1 and IGDRV2. The clock frequency is given by 1 1 ≈ (1.5 • RT + 831 ) • CT (1.5 • RT • CT ) I AC ( pk ) ω • CCRMS (2) (2a) For proper operation, IAC(pk) should be selected to be 100 A at peak line voltage. For universal input voltage with peak value of 265 VAC, this means RAC = 3.6M. The noise sensitivity of the IC requires a small bypass capacitor for high frequency noise filtering. The value of this capacitor should be limited to 220nF maximum. The VCRMS value should be approximately 1V at the peak of low line (80 VAC) to minimize any digitization errors. The peak value of VCRMS at high line then becomes 3.5V. The desired CCRMS can be calculated from equation 2 to be 75nF for 60Hz line. Oscillator Set-up f SW = I AC ( pk ) (1 − cos ωt ) 2 • ω • CCRMS The multiplier output current is given by equation (3) with K = 0.33. (1) IMULT = The IGDRV1 and IGDRV2 outputs are switched at half the clock frequency while MOSDRV is switched at the clock frequency. (VVAO – 0 .5 ) • I AC • K VCRMS (3) 2 The multiplier peak current is limited to 200 A and the selected values for IAC and VCRMS should ensure that the current is within this range. Another limitation of the multiplier is that IMULT can not exceed two times the IAC current, limiting the minimum voltage on VCRMS. Reference Signal (IMULT) generation Like the UC3854 series, the UCC3857 has an analog computation unit (ACU) which generates a reference current signal for the current error amplifier. The inputs to the ACU are signals proportional to instantaneous line voltage, input voltage RMS information and the voltage The discrete nature of the RMS voltage feedforward means that there are regions of operation where the in7 UCC1857 UCC2857 UCC3857 APPLICATION INFORMATION (cont.) RAC IAC 1 A B VAO A•B C C CRMS 2 CCRMS A D 6 BIT WORD MULTI DAC REGISTER (X2) Figure 3. Novel RMS voltage generation scheme. put voltage changes, but the VRMS value fed into the multiplier does not change. The voltage error amplifier compensates for this by changing its output to maintain the required multiplier output current. When the output of the ADC changes, there is a jump in the output of the error amplifier. This has minimal impact on the overall converter operation. bridge. In such instances, the feedforward effect does not take place and the controller functionality is compromised. For UCC3857, the IAC current should go below 10 A for the zero crossing detection to take place. It is recommended that the capacitor value be kept low enough for light load operation or that the alternative scheme shown in Fig. 4 be used for IAC sense. Another key consideration with the RMS voltage scheme is that it relies on the zero-crossing of the Iac signal to be effective. At very light loads and high line conditions, the rectified AC does not quite reach zero if a large capacitor is being used for filtering on the rectified side of the Gate Drive Considerations AC LINE The gate drive circuits in UCC3857 are designed for high speed driving of the power switches. Each drive circuit consists of low impedance pull-up and pull-down DMOS output stages. The UCC3857 provides separate supply and ground pins (VD and PGND) for the driver stages. These pins allow better local bypassing of the driver circuits. VD can also be used to ensure that the SOA limits of the output stages are not violated when driving high peak current levels. For this, VD can be kept as low as possible (e.g. 10V) while VIN can go higher to handle the UVLO requirements. BRIDGE RECTIFIER Current Amplifier Set-up RAC 1 IAC Once the multiplier is set-up by choosing the VRMS range, the current amplifier components can be designed. The maximum multiplier output is at low line, full load conditions. The inductor peak current also occurs at the same point. The multiplier terminating resistor can be determined using equation 4. UCC3857 Figure 4. Alternative implementation for sensing IAC. 8 UCC1857 UCC2857 UCC3857 RMULT = IL −PK • R SENSE IMULT −PK (4) with line feedforward is indicative of load power. The delay time is programmed with external components, RD and CD. The sequence of events starts when the internal CLK signal resets latch U2, causing PWMDEL to go high and the Q output to go low. CD was discharged via M1 and is held low until the internal PWM signal goes low (indicating turn-off of either of the IGBT drives). At this point M1 turns off and CD charges towards the 7.5V reference through RD. A comparator U1 compares this voltage to the voltage error amplifier output (VVAO). When the voltage on CD is greater than VVAO, the latch U2 is set causing PWMDEL to go low. PWMDEL is logically The current amplifier can be compensated using a previously presented techniques (U-134) summarized here. A simplified high frequency model for inductor current to duty cycle transfer function is given by ∧ i L Vo Gid ( s ) = = ∧ SL d (5) The gain of the current feedback path at the frequency of interest (crossover) is given by ∧ d ∧ iL = R SENSE RZ 1 • • RI V SE 7.5V REF (6) RD CLK DELAY Where VSE is the ramp amplitude (p-p) which is 4.5V for UCC3857. Combining equations. 5 and 6 yields the loop gain of the current loop and equating it to 1 at the desired crossover frequency can result in a design value for RZ. The current loop crossover frequency should be limited to about 1/3 of the switching frequency of the converter to ensure stability. See Unitrode Application Note U-140 for further information. MOSDRV 12 CD S Q PWMDEL U2 VAO CLK R Q PWM Trailing Edge Delay Figure 5. Circuit for adaptive MOSFET delay generation. As shown in the waveforms of Fig. 1, the modified isolated boost converter requires drive signals for the two main (IGBT) switches and the auxiliary (MOSFET) switch with certain timing relationships. The delay between turn-off of an IGBT and turn-off of the MOSFET can be programmed for the UCC1857. In a PFC application, the input line varies from zero to the AC peak level, resulting in a wide range of required duty ratios. A fixed delay time will induce line current distortion at the peaks of the AC line under high line and/or light load conditions. This is caused by the minimum controllable duty ratio imposed on the modulator by the fixed delay. If the minimum controllable duty ratio is fixed, the inner current loop can exhibit a limit cycle oscillation at the line peaks, inducing line current distortion. ANDed with CLK to produce the signal which commands the MOSFET driver output (MOSDRV). The delay time, TD1, is given by 7 .5 – VVAO TD 1 = – RD • CD • n 7 .5 (7) This technique reduces the overlap delay at light loads or high lines, but maintains a longer delay when the line voltage is low or the load is heavy. This by definition reduces the minimum controllable duty ratio to an acceptable level, and is programmable by the user. Reducing the delay time under light current conditions is acceptable since the IGBT current is directly proportional to load current. By providing programming flexibility with RD and CD, the delay times can be optimized for current and future classes of IGBT switches. The delay can also be set to zero by removing CD from the circuit. The UCC1857 has an adaptive MOSFET delay generator, which is directly modulated by load power demand. Referring to Fig. 5, this circuit directly varies the delay time based on the output level of the voltage error amplifier, which in an average current mode PFC converter UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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