T R I Q U I N T S E M TGF4230-EEU I C O N D U C 1.2mm Discrete HFET ● ● ● ● ● ● 1200 µm X 0.5 µm HFET T O R , I N C . 4230 Nominal Pout of 28.5- dBm at 8.5- GHz Nominal Gain of 10.0- dB at 8.5- GHz Nominal PAE of 55% at 8.5 - GHz Suitable for High-Reliability Applications 0,572 x 0,699 x 0,102 mm (0.023 x 0.028 x 0.004 in.) PHOTO ENLARGEMENT DESCRIPTION The Triquint TGF4230 - EEU is a single gate 1.2 mm Discrete GaAs Heterostructure Field Ef fect Transistor (HFET) designed for high- efficiency power applications up to 1 2- GHz in Class A and Class AB operation. Bond - pad and backside metalization is gold plated for compatibility with eutectic alloy attach methods as well as thermocompression and thermosonic wire- bonding processes. The TGF4230-EEU is readily assembled using automatic equipment. TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com TGF4230-EEU 0.3 EXAMPLE OF DC I-V CURVES VG = 0.0 to -2.25 V (0.25 V steps) TA = 25°C Drain Current (A) 0.25 0.2 0.15 0.1 0.05 0 0 1 2 3 4 5 6 7 8 9 10 Drain Voltage (V) 30 OUTPUT POWER VS. INPUT POWER F = 8.5GHz V D =8.0V I Q =50mA* T A =25°C Output Power (dBm) 28 26 24 22 20 18 16 4 6 8 10 12 14 16 18 20 22 Input Power (dBm) Note: I Q is defined as the drain current before application of RF signal at the input. 60 POWER ADDED EFFICIENCY VS. INPUT POWER F = 8.5GHz V D =8.0V I Q =50mA* T A =25°C 55 50 45 PAE (%) 40 35 30 25 20 15 10 5 4 6 8 10 12 14 16 18 20 22 Input Power (dBm) 2 TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com TGF4230-EEU 12 GAIN VS. INPUT POWER F =8.5GHz V D =8.0V I Q =50mA* T A =25°C Gain (dB) 11 10 9 8 7 4 6 8 10 12 14 16 18 20 22 Input Power (dBm) 180 DRAIN CURRENT VS. INPUT POWER F =8.5GHz V D =8.0V I Q =50mA* T A =25°C Drain Current (mA) 160 140 120 100 80 60 40 4 6 8 10 12 14 16 18 20 22 Input Power (dBm) ABSOLUTE MAXIMUM RATINGS Drain - to- source Voltage, VDS. ................................................................................................................ 12 V Gate - to- source Voltage, VGS ...................................................................................................... - 5 V to 0 V Mounting temperatur e (30 sec), TM .................................................................................................. 320 C Storage temperature range, TSTG ............................................................ ................................ - 65 to 200 C Power dissipation, PD .................................................................................. (see thermal data on next page) Operating channel temperature, T CH .............................................................. (see thermal data on next page) Ratings over base-plate temperature range T BP (unless otherwise noted) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated “RF and DC Characteristics” is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com 3 TGF4230-EEU p 300 Channel Temperature (° C) PREDICTED CHANNEL TEMPERA TURE VS. BASE TEMPERA TURE at 0.51 W and 1.02 W dissipated power 250 200 150 100 50 0.51 W (soldered to carrier) 0 0.51 W (HFET backside metal) -50 1.02 W (soldered to carrier) 1.02 W (HFET backside metal) -100 -100 -50 0 50 100 150 200 Base Temperature (° C) Case 1: Base temperature at backside of carrier (with 38 m AuSn solder attach to 0.5 mm CuMo Car rier). Case 2: Base temperature at backside of 1.2 mm HFET . p 325 HFET CHANNEL TEMPERATURE VS. MEDIAN LIFE Channel Temperature (° C) 300 275 250 225 200 175 150 125 100 1 2 3 4 5 6 7 8 9 10 11415 years Median Life (10^X Hours) 4 TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com TGF4230-EEU RF AND DC CHARACTERISTICS PARAMETER Pout GP PAE I DSS GM VP BV G S BV G D Output Power Power Gain Power Added Efficiency Drain Saturation Current Transconductance Pinch Off Voltage Breakdown Voltage Gate-Source Breakdown Voltage Gate-Drain MIN NOMINAL MAX UNIT 27.5 8 50 204 144 -2.7 -30 -30 28.5 10 55 294 198 -1.85 -22 -22 384 252 -1 -17 -17 dBm dB % mA mS V V V Pout, Gain, and P AE: Measured at 8.5 GHz, drain voltage of 8.0 V . Gate voltage is adjusted to achieve quiescent current of approximately 20% I DSS with no RF signal applied. The source is gr ounded. Input power between 18 and 19-dBm. IDSS: Saturated drain-source current. Sear ch for the maximum IDS at VGS = 0.0 V, and VDS swept between 0.5 V to 3.5 V. Note that the drain voltage at which I DSS is located and recorded as VDSP. GM: Transconductance. (I DSS - I DS1 )/ I VG1 I. I DS1 measured at VG1 = -0.25 V using the knee search technique; VDS swept between 0.5 V and VDSP to search for maximum I DS1. VP: Pinch off voltage. VGS for I DS = 0.5 mA/mm of gate width. V DS fixed at 2.0 V, VGS swept to bring I DS to 0.5 mA/mm. Sweep will stop if V P current not found beyond 0.5 V of the minimum V P specification. BVGS: Breakdown voltage, gate to source. I BD = 1.0 mA/mm of gate width. Source fixed at ground, drain not connected (floating). When 1.0mA/mm drawn at gate, V GS measured as B VGS. BVGD: Breakdown voltage, gate to drain. I BD = 1.0 mA/mm of gate width. Drain fixed at gr ound, source not connected (floating). When 1.0 mA/mm drawn at the gate, V GD measured as B VGD. LINEAR MODEL C DG R DG LG RG RD V CCS LD G D RI C DS R GS C GS R1 R2 R DS RS LS VDS = 8.0 V and 30% I DSS at T = 25°C FET Elements L G = 0.0421 nH R G = 0.43 R G S = 81700 R I = 1.21 C GS = 1.21 pF C DG = 0.1004 pF R DG = 204000 RS = 0.4 L S = 0.015 nH R DS = 98.01 CDS = 0.25325 pF R D = 0.66 L D = 0.022 nH VCCS Parameters M = 132.9 mS A=0 R1 = 1E19 R2 = 1E19 F=0 T = 5.49 pS 5 TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com TGF4230-EEU MODELED S-PARAMETERS Frequency (GHz) S 11 MAG S 21 ANG(o) MAG S 12 ANG(o) MAG S 22 ANG(o) MAG ANG(o) 0.5 0.985 -29.88 8.095 161.49 0.021 72.66 0.343 -22.22 1.0 0.959 -56.20 7.297 145.18 0.038 58.80 0.328 -41.75 1.5 0.931 -77.47 6.368 131.86 0.050 47.65 0.312 -57.46 2.0 0.908 -94.02 5.512 121.22 0.057 39.12 0.301 -69.57 2.5 0.891 -106.82 4.791 112.62 0.062 32.60 0.295 -78.80 3.0 0.880 -116.82 4.202 105.49 0.065 27.55 0.294 -85.89 3.5 0.871 -124.76 3.723 99.42 0.067 23.56 0.297 -91.41 4.0 0.865 -131.19 3.330 94.11 0.068 20.34 0.302 -95.80 4.5 0.861 -136.48 3.004 89.37 0.069 17.70 0.309 -99.38 5.0 5.5 0.858 0.856 -140.92 -144.69 2.732 2.501 85.06 81.09 0.069 0.069 15.51 0.319 -102.37 13.67 0.329 -104.94 6.0 0.855 -147.94 2.304 77.39 0.068 12.12 0.340 -107.18 6.5 0.854 -150.78 2.133 73.90 0.068 7.0 0.854 -153.29 1.984 70.59 0.067 10.82 9.72 0.352 0.364 -109.19 -111.03 7.5 8.0 0.854 0.855 -155.53 -157.54 1.852 1.736 67.43 64.40 0.066 0.065 8.80 8.05 0.377 0.390 -112.73 -114.32 8.5 9.0 9.5 0.855 0.856 0.857 -159.37 -161.04 -162.58 1.632 1.539 1.455 61.49 58.67 55.95 0.065 0.064 0.063 7.45 7.00 6.68 0.404 0.417 0.430 -115.84 -117.29 -118.68 10.0 0.858 -164.01 1.378 53.30 0.061 6.49 0.444 -120.03 10.5 11.0 11.5 12.0 0.859 0.860 0.862 0.863 -165.34 -166.58 -167.76 -168.87 1.308 1.244 1.186 1.131 50.73 48.23 45.79 43.41 0.060 0.059 0.058 0.057 6.43 6.51 6.71 7.05 0.457 0.470 0.483 0.496 -121.35 -122.63 -123.89 -125.11 12.5 0.864 -169.93 1.081 41.09 0.056 7.52 0.509 -126.32 13.0 13.5 14.0 0.866 0.867 0.869 -170.94 -171.91 -172.84 1.034 0.991 0.950 38.83 36.62 34.46 0.055 0.053 0.052 8.12 8.86 9.74 0.521 0.534 0.546 -127.51 -128.68 -129.82 VDS = 8.0 V and 30% I DSS at T = 25°C 6 TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com TGF4230-EEU 0.699 MECHANICAL DRAWING 0.601 R/C** 2 1 0.350 0.099 4 3 0.0 0.0 0.097 Units: Millimeters Thickness: 0.102 Chip size ± 0.0508 0.264 Bond Bond Bond Bond pad pad pad pad 0.471 1 2 3 4 0.572 (gate): 0.072 x 0.075 (gate): 0.075 x 0.075* (gate): 0.075 x 0.075* (drain): 0.083 x 0.077 Minimum connections to Bond Pads 1 and 4. Sources are connected to backside metalization. * Alternate gate pads used for paralleling TGF4230s or for multiple gate wir es. ** Wafer unique Row/Column data is recorded in brackets. NOTES Gate bias supplies should be designed to sink or source gate current. The magnitude and direction of the gate current is a function of bias point, load impedance, and drive level. 7 TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com