DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 16-Bit, Serial Input Multiplying Digital-to-Analog Converter FEATURES • • • • • • • • • • • • • • • ±0.5 LSB DNL 16-Bit Monotonic ±1 LSB INL Low Noise: 12 nV/√Hz Low Power: IDD = 2 µA +2.7 V to +5.5 V Analog Power Supply 2 mA Full-Scale Current ±20%, with VREF = 10 V 50-MHz Serial Interface 0.5 µs Settling Time 4-Quadrant Multiplying Reference Reference Bandwidth: 10 MHz ±10 V Reference Input Reference Dynamics: -105 THD Tiny 8-Lead 3 x 3 mm SON and 3 x 5 mm MSOP Packages Industry-Standard Pin Configuration DESCRIPTION The DAC8811 multiplying digital-to-analog converter (DAC) is designed to operate from a single 2.7-V to 5.5-V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier. A serial data interface offers high-speed, three-wire microcontroller-compatible inputs using data-in (SDI), clock (CLK), and chip-select (CS). The DAC8811 is packaged in space-saving 8-lead SON and MSOP packages. DAC8811 RFB VDD VREF D/A Converter IOUT 16 APPLICATIONS • • • • Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs CS DAC Register 16 CLK SDI Shift Register GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) PACKAGELEAD (DESIGNATOR) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC8811C ±1 ±1 MSOP-8 (DGK) -40°C to +85°C D11 DAC8811ICDGKT Tape and Reel, 250 DAC8811C ±1 ±1 MSOP-8 (DGK) -40°C to +85°C D11 DAC8811ICDGKR Tape and Reel, 2500 DAC8811C ±1 ±1 SON-8 (DRB) -40°C to +85°C D11 DAC8811ICDRBT Tape and Reel, 250 DAC8811C ±1 ±1 SON-8 (DRB) -40°C to +85°C D11 DAC8811ICDRBR Tape and Reel, 2500 DAC8811B ±2 ±1 MSOP-8 (DGK) -40°C to +85°C D11 DAC8811IBDGKT Tape and Reel, 250 DAC8811B ±2 ±1 MSOP-8 (DGK) -40°C to +85°C D11 DAC8811IBDGKR Tape and Reel, 2500 DAC8811B ±2 ±1 SON-8 (DRB) -40°C to +85°C D11 DAC8811IBDRBT Tape and Reel, 250 DAC8811B ±2 ±1 SON-8 (DRB) -40°C to +85°C D11 DAC8811IBDRBR Tape and Reel, 2500 (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) DAC8811 UNIT -0.3 to +7 V Digital input voltage to GND -0.3 to +VDD + 0.3 V V (IOUT) to GND VDD to GND -0.3 to +VDD + 0.3 V Operating temperature range -40 to +105 °C Storage temperature range -65 to +150 °C +125 °C Junction temperature range (TJ max) Power dissipation (TJ max - TA) / RΘJA Thermal impedance, RΘJA Lead temperature, soldering Vapor phase (60s) Lead temperature, soldering Infrared (15s) 55 °C/W 215 °C 220 °C ESD rating, HBM 1500 V ESD rating, CDM 1000 V (1) 2 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS VDD = +2.7 V to +5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = full operating temperature. All specifications -40°C to +85°C, unless otherwise noted. DAC8811 PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 16 Bits Relative accuracy DAC8811C ±1 LSB Relative accuracy DAC8811B ±2 LSB ±1 LSB nA Differential nonlinearity Output leakage current Data = 0000h, TA = +25°C 10 Output leakage current Data = 0000h, TA = TMAX 10 nA Full-scale gain error All ones loaded to DAC register ±4 mV ±1 Full-scale tempco ±3 ppm/°C 2 mA 50 pF OUTPUT CHARACTERISTICS (2) Output current Output capacitance Code dependent REFERENCE INPUT VREF Range -15 15 V Input resistance 5 kΩ Input capacitance 5 pF LOGIC INPUTS AND OUTPUT (2) Input low voltage VIL VDD = +2.7V Input high voltage VIH VDD = +2.7V 2.1 VIH VDD = +5V 2.4 VIL VDD = +5V Input leakage current Input capacitance 0.6 V 0.8 V V V IIL 10 µA CIL 10 pF fCLK 50 MHz INTERFACE TIMING Clock input frequency Clock pulse width high 10 ns Clock pulse width low 10 ns CS to Clock setup time 0 ns Clock to CS hold time 10 ns Data setup time 5 ns Data hold time 10 ns POWER REQUIREMENTS VDD 2.7 IDD (normal operation) Logic inputs = 0 V VDD = +4.5V to +5.5V VIH = VDD and VIL = GND VDD = +2.7V to +3.6V VIH = VDD and VIL = GND 5.5 V 5 µA 3 5 µA 1 2.5 µA AC CHARACTERISTICS Output voltage settling time 0.5 µs Reference multiplying BW VREF = 5 VPP, Data = FFFFh 10 MHz DAC glitch impulse VREF = 0 V to 10 V, Data = 7FFFh to 8000h to 7FFFh 2 nV/s Feedthrough error VOUT/VREF Data = 0000h, VREF = 100kHz -70 dB 2 nV/s Digital feedthrough (1) (2) Linearity calculated using a reduced code range of 48 to 4047; output unloaded. Specified by design and characterization; not production tested. 3 DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) VDD = +2.7 V to +5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = full operating temperature. All specifications -40°C to +85°C, unless otherwise noted. DAC8811 PARAMETER CONDITIONS MIN TYP MAX UNITS Total harmonic distortion -105 dB Output spot noise voltage 12 nV/√Hz PIN ASSIGNMENTS DGK PACKAGE (TOP VIEW) DRB PACKAGE (TOP VIEW) CLK 1 8 CS VDD SDI 2 7 VDD 6 GND RFB 3 6 GND 5 IOUT VREF 4 5 IOUT CLK 1 8 CS SDI 2 7 RFB 3 VREF 4 Table 1. TERMINAL FUNCTIONS 4 PIN NAME 1 CLK Clock input; positive edge triggered clocks data into shift register DESCRIPTION 2 SDI Serial register input; data loads directly into the shift register MSB first. Extra leading bits are ignored. 3 RFB Internal matching feedback resistor. Connect to external op amp output. 4 VREF DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code. 5 IOUT DAC current output. Connects to inverting terminal of external precision I/V op amp. 6 GND Analog and digital ground. 7 VDD Positive power supply input. Specified operating range of 2.7 V to 5.5 V. 8 CS Chip-select; active low digital input. Transfers shift register data to DAC register on rising edge. See Table 2 for operation. DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VDD = +5 V At TA = +25°C, +VDD = +5 V, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25 C 0.8 TA = +25 C 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 0 Digital Input Code 1.0 Figure 2. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 0.6 0.6 0.4 0.4 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 3. Figure 4. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = +85C 0.8 TA = +85 C 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) TA = − 40 C 0.8 DNL (LSB) INL (LSB) Figure 1. TA = − 40 C 0.8 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 5. 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 6. 5 DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE REFERENCE MULTIPLYING BANDWIDTH 6 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 −60 −66 −72 −78 −84 −90 −96 −102 −108 −114 1.6 VDD = +5.0V 1.2 Attenuation (dB) Supply Current, IDD (mA) 1.4 1.0 0.8 0.6 0.4 0.2 VDD = +2.7V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 10k 100k 1M Figure 8. DAC GLITCH DAC SETTLING TIME Code: 7FFFh to 8000h Output Voltage (5V/div) Output Voltage (50mV/div) 1k Figure 7. Figure 9. 10M Voltage Output Settling Trigger Pulse Trigger Pulse Time (0.2µs/div) 6 100 Bandwidth (Hz) Logic Input Voltage (V) Time (0.1µs/div) Figure 10. 100M DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, +VDD = +2.7V, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 0.6 0.6 0.4 0.4 0.2 0 −0.2 0 −0.2 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code 0 Figure 12. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = − 40 C 0.8 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 11. 1.0 TA = −40 C 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) 0.2 −0.4 −1.0 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code 0 Figure 14. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = +85C 0.8 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 13. 1.0 TA = +85 C 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) TA = +25 C 0.8 DNL (LSB) INL (LSB) 1.0 TA = +25 C 0.8 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 15. 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 16. 7 DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 THEORY OF OPERATION The DAC8811 is a single channel current output, 16-bit digital-to-analog converter (DAC). The architecture, illustrated in Figure 17, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the ladder is either switched to GND or the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load impedance to the external reference of 5 kΩ± 25%. The external reference voltage can vary in a range of -15 V to 15 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC8811 RFB resistor, output voltage ranges of -VREF to VREF can be generated. R R R VREF 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R RFB IOUT GND Figure 17. Equivalent R-2R DAC Circuit When using an external I/V converter and the DAC8811 RFB resistor, the DAC output voltage is given by Equation 1: V OUT VREF CODE 65536 (1) Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output impedance as seen looking into the IOUT terminal changes versus code, the external I/V converter noise gain will also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such that the amplifier offset is not modulated by the DAC IOUT terminal impedance change. External op amps with large offset voltages can produce INL errors in the transfer function of the DAC8811 due to offset modulation versus DAC code. For best linearity performance of the DAC8811, an op amp (OPA277) is recommended (Figure 18). This circuit allows VREF swinging from -10 V to +10 V. VDD U1 VDD VREF DAC8811 RFB U2 15 V IOUT _ V+ OPA277 GND + V− −15 V Figure 18. Voltage Output Configuration 8 VO DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 THEORY OF OPERATION (continued) SDI D15 D14 D13 D12 D11 D10 D9 D8 D1 D0 CLK t(DS) t(CSS) t(CH) t(DH) t(CSH) t(CL) CS Figure 19. DAC8811 Timing Diagram Table 2. Control Logic Truth Table (1) CLK CS Serial Shift Register DAC Register X H No effect Latched ↑+ L Shift register data advanced one bit Latched X H No effect Latched X ↑+ Shift register data transferred to DAC register New data loaded from serial register (1) ↑+ Positive logic transition; X = Don't care Table 3. Serial Input Register Data Format, Data Loaded MSB First Bit B15 (MSB) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 APPLICATION INFORMATION Stability Circuit For a current-to-voltage design (see Figure 20), the DAC8811 current output (IOUT) and the connection with the inverting node of the op amp should be as short as possible and according to correct PCB layout design. For each code change there is a step function. If the GBP of the op amp is limited and parasitic capacitance is excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in Figure 20. VDD C1 U1 VDD VREF VREF GND RFB IOUT − VOUT + U2 Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor Positive Voltage Output Circuit As Figure 21 illustrates, in order to generate a positive voltage output, a negative reference is input to the DAC8811. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors of the resistor. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground and a -2.5 V input to the DAC8811 with an op amp. 9 DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 APPLICATION INFORMATION (continued) VDD +2.5V Reference VOUT VIN GND VDD VREF − + RFB C1 OPA277 DAC8811 −2.5V IOUT OPA277 − + VOUT GND 0 VOUT +2.5V Figure 21. Positive Voltage Output Circuit Bipolar Output Circuit The DAC8811, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the full-scale output IOUT is the inverse of the input reference voltage at VREF. Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22, external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A 4-quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4. According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces output voltages of VOUT = -2.5 V to VOUT = +2.5 V. V OUT 32,D768 1 V REF (2) External resistance mismatching is the significant error in Figure 22. 10 k VDD VDD +2.5V (+10V) VREF 10 k C2 5 k − RFB C1 DAC8811 VOUT U4 OPA277 − IOUT GND + + U2 OPA277 −2.5V VOUT +2.5V (−10V VOUT +10V) Figure 22. Bipolar Output Circuit Programmable Current Source Circuit A DAC8811 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3: R2R3 R1 IL V REF D R3 (3) 10 DAC8811 www.ti.com SLAS411A – NOVEMBER 2004 – REVISED DECEMBER 2004 The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive ±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO, according to Equation 4: ZO R1R3R1R2 R1R2R3 R1R2R3 (4) As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a value of several pF is suggested. R2 15 k C1 10 pF R1 150 k VDD VDD VREF VREF U2 OPA277 − RFB U1 DAC8811 IOUT R3 50 R2 15 k − + VOUT + U2 OPA277 GND R3 50 k R1 150 k IL LOAD Figure 23. Programmable Bidirectional Current Source Circuit Cross-Reference The DAC8811 has an industry-standard pinout. Table 4 provides the cross-reference information. Table 4. Cross-Reference PRODUCT INL (LSB) DNL (LSB) SPECIFIED TEMPERATURE RANGE DAC8811ICDGK ±1 ±1 -40°C to +85°C DAC8811IBDGK ±2 ±1 -40°C to +85°C 8-Lead MicroSOIC MSOP-8 AD5543BRM DAC8811ICDRB ±1 ±1 -40°C to +85°C 8-Lead Small Outline SON-8 N/A DAC8811IBDRD ±2 ±1 -40°C to +85°C 8-Lead Small Outline SON-8 N/A N/A ±2 ±1 -40°C to +85°C 8-Lead SOIC SOIC-8 AD5543BR PACKAGE DESCRIPTION PACKAGE OPTION CROSSREFERENCE PART 8-Lead MicroSOIC MSOP-8 N/A 11 PACKAGE OPTION ADDENDUM www.ti.com 17-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC8811IBDGKR ACTIVE MSOP DGK 8 2500 TBD Call TI Call TI DAC8811IBDGKT ACTIVE MSOP DGK 8 250 TBD Call TI Level-1-220C-UNLIM DAC8811IBDRBR ACTIVE SON DRB 8 3000 TBD CU POST PLATE Level-1-240C-UNLIM DAC8811IBDRBT ACTIVE SON DRB 8 250 TBD CU POST PLATE Level-1-240C-UNLIM DAC8811ICDGKR ACTIVE MSOP DGK 8 2500 TBD Lead/Ball Finish MSL Peak Temp (3) Call TI Level-1-220C-UNLIM DAC8811ICDGKT ACTIVE MSOP DGK 8 250 TBD Call TI Level-1-220C-UNLIM DAC8811ICDRBR ACTIVE SON DRB 8 3000 TBD CU SNPB Level-1-240C-UNLIM DAC8811ICDRBT ACTIVE SON DRB 8 250 TBD CU SNPB Level-1-240C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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