www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 D 1 A Low-Dropout Voltage Regulator D Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, D D D D D D D PWP PACKAGE (TOP VIEW) 3.0-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions Dropout Voltage Down to 230 mV at 1 A (TPS76750) Ultralow 85 mA Typical Quiescent Current Fast Transient Response 2% Tolerance Over Specified Conditions for Fixed-Output Versions Open Drain Power-On Reset With 200-ms Delay (See TPS768xx for PG Option) 8-Pin SOIC and 20-Pin TSSOP PowerPAD (PWP) Package Thermal Shutdown Protection GND/HSINK GND/HSINK GND NC EN IN IN NC GND/HSINK GND/HSINK 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 GND/HSINK GND/HSINK NC NC RESET FB/NC OUT OUT GND/HSINK GND/HSINK NC − No internal connection D PACKAGE (TOP VIEW) description GND EN IN IN This device is designed to have a fast transient response and be stable with 10 µF low ESR capacitors. This combination provides high performance at a reasonable cost. TPS76733 DROPOUT VOLTAGE vs FREE-AIR TEMPERATURE 1 8 2 7 3 6 4 5 RESET FB/NC OUT OUT TPS76733 LOAD TRANSIENT RESPONSE 103 102 I O − Output Current − A 101 IO = 10 mA 100 10−1 IO = 0 Co = 10 µF 10−2 −60 −40 −20 0 20 40 60 ∆ VO − Change in Output Voltage − mV 100 IO = 1 A VDO − Dropout Voltage − mV 1 80 100 120 140 TA − Free-Air Temperature − °C Co = 10 µF TA = 25°C 50 0 −50 −100 1 0.5 0 0 100 200 300 400 500 600 700 800 900 1000 t − Time − µs Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. !"#$ % &'!!($ #% )'*+&#$ ,#$(- !,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1!,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- Copyright 1999 − 2004, Texas Instruments Incorporated1 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 description (continued) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 230 mV at an output current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 µA over the full range of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C. The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 20-pin PWP packages. AVAILABLE OPTIONS TJ −40°C to 125°C OUTPUT VOLTAGE (V) PACKAGED DEVICES TYP TSSOP (PWP) SOIC (D) 5.0 TPS76750Q TPS76750Q 3.3 TPS76733Q TPS76733Q 3.0 TPS76730Q TPS76730Q 2.8 TPS76728Q TPS76728Q 2.7 TPS76727Q TPS76727Q 2.5 TPS76725Q TPS76725Q 1.8 TPS76718Q TPS76718Q 1.5 TPS76715Q TPS76715Q Adjustable 1.5 V to 5.5 V TPS76701Q TPS76701Q The TPS76701 is programmable using an external resistor divider (see application information). The D and PWP packages are available taped and reeled. Add an R suffix to the device type (e.g., TPS76701QDR). TPS767xx VI 6 IN RESET 16 RESET 7 IN OUT 0.1 µF 5 EN OUT 14 VO 13 + GND Co(1) 10 µF 3 (1) See application information section for capacitor selection details. Figure 1. Typical Application Configuration (For Fixed Output Options) 2 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 functional block diagram—adjustable version IN EN RESET _ + OUT + _ 200 ms Delay Vref = 1.1834 V R1 FB/NC R2 GND External to the device functional block diagram—fixed-voltage version IN EN RESET _ + OUT + _ 200 ms Delay R1 Vref = 1.1834 V R2 GND 3 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 Terminal Functions SOIC Package TERMINAL NAME I/O NO. DESCRIPTION EN 2 I Enable input FB/NC 7 I Feedback input voltage for adjustable device (no connect for fixed options) GND 1 Regulator ground IN 3, 4 I Input voltage OUT 5, 6 O Regulated output voltage 8 O RESET output RESET PWP Package TERMINAL NAME NO. I/O DESCRIPTION EN 5 I Enable input FB/NC 15 I Feedback input voltage for adjustable device (no connect for fixed options) GND GND/HSINK 3 Regulator ground 1, 2, 9, 10, 11, 12, 19, 20 Ground/heatsink IN 6, 7 NC 4, 8, 17, 18 OUT I Input voltage No connect 13, 14 O Regulated output voltage 16 O RESET output RESET timing diagram VI Vres(1) Vres t VO VIT+(2) VIT+(2) Threshold Voltage (2) VIT− Less than 5% of the output voltage VIT−(2) t RESET Output Output Undefined ÎÎ ÎÎ ÎÎ ÎÎ 200 ms Delay 200 ms Delay ÎÎ ÎÎ ÎÎ ÎÎ Output Undefined t (1) Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. (2) VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage. 4 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)(1) Input voltage range(2), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VI + 0.3 V Maximum RESET voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE 1 − FREE-AIR TEMPERATURES PACKAGE D AIR FLOW (CFM) TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 0 568 mW 5.68 mW/°C 312 mW 227 mW 250 904 mW 9.04 mW/°C 497 mW 361 mW DISSIPATION RATING TABLE 2 − FREE-AIR TEMPERATURES PACKAGE PWP§ PWP¶ AIR FLOW (CFM) TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 0 2.9 W 23.5 mW/°C 1.9 W 1.5 W 300 4.3 W 34.6 mW/°C 2.8 W 2.2 W 0 3W 23.8 mW/°C 1.9 W 1.5 W 300 7.2 W 57.9 mW/°C 4.6 W 3.8 W (1) This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5 in × 5 in PCB, 1 oz. copper, 2 in × 2 in coverage (4 in2). (2) This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5 in × 2 in PCB, 1 oz. copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002. recommended operating conditions MIN MAX Input voltage, VI(1) 2.7 10 V Output voltage range, VO 1.2 5.5 V 0 1.0 A Output current, IO (2) UNIT Operating junction temperature, TJ (2) −40 125 °C (1) Maximum VIN = VOUT + VDO or 2.7V, whichever is greater. (2) Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. 5 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range, VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 mF (unless otherwise noted) PARAMETER TEST CONDITIONS TPS76701 Output voltage (10 µA A to 1 A load) 1.5 V ≤ VO ≤ 5.5 V, 1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C TJ = −40°C to 125°C MIN 0.98VO 2.7 V < VIN < 10 V TPS76715 2.7 V < VIN < 10 V 1.470 TPS76718 TJ = 25°C, TJ = −40°C to 125°C, 2.8 V < VIN < 10 V 2.8 V < VIN < 10 V 1.764 TPS76725 TJ = 25°C, TJ = −40°C to 125°C, 3.5 V < VIN < 10 V TPS76727 TJ = 25°C, TJ = −40°C to 125°C, 3.7 V < VIN < 10 V 2.646 TPS76728 TJ = 25°C, TJ = −40°C to 125°C, 3.8 V < VIN < 10 V 3.8 V < VIN < 10 V 2.744 TPS76730 TJ = 25°C, TJ = −40°C to 125°C, 4.0 V < VIN < 10 V 4.0 V < VIN < 10 V 2.940 TPS76733 TJ = 25°C, TJ = −40°C to 125°C, 4.3 V < VIN < 10 V TPS76750 TJ = 25°C, TJ = −40°C to 125°C, Output voltage line regulation (∆VO/VO) Output current limit VO = 0 V Standby current FB input current TPS76701 EN = VI, TJ = −40°C to 125°C 2.7 V < VI < 10 V 2.856 3.060 3.3 3.234 3.366 5.0 4.900 5.100 85 125 %/V 3 mV 55 µVrms 1.7 Power supply ripple rejection 6 2 °C 1 µA 2 µA nA 1.7 V 0.9 Co = 10 µF, A 150 Low level enable input voltage f = 1 KHz, TJ = 25°C µA A 0.01 10 FB = 1.5 V High level enable input voltage V 3.0 Thermal shutdown junction temperature TJ = 25°C, 2.7 V < VI < 10 V 2.754 2.8 1.2 EN = VI, 2.550 2.7 Load regulation Output noise voltage (TPS76718) 1.836 2.450 TJ = 25°C IO = 1 A, TJ = −40°C to 125°C VO + 1 V < VI ≤ 10 V, TJ = 25°C BW = 200 Hz to 100 kHz, IC = 1 A, Co = 10 µF, TJ = 25°C 1.530 2.5 10 µA < IO < 1 A, Quiescent current (GND current) EN = 0V 1.02VO 1.8 6.0 V < VIN < 10 V 6.0 V < VIN < 10 V UNIT 1.5 3.7 V < VIN < 10 V 4.3 V < VIN < 10 V MAX VO TJ = 25°C, TJ = −40°C to 125°C, 3.5 V < VIN < 10 V TYP 60 V dB www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range, VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 mF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Trip threshold voltage IO(RESET) = 300 µA VO decreasing Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, V(RESET) = 5 V Minimum input voltage for valid RESET Reset Leakage current MIN TYP MAX UNIT 1.1 92 V 98 %VO %VO 0.4 V 0.5 IO(RESET) = 1 mA 0.15 µA 1 RESET time-out delay 200 Input current (EN) EN = 0 V −1 EN = VI −1 0 1 µA A 1 IO = 1 A, IO = 1 A, TJ = 25°C TJ = −40°C to 125°C 500 TPS76728 TJ = 25°C TJ = −40°C to 125°C 450 TPS76730 IO = 1 A, IO = 1 A, TJ = 25°C TJ = −40°C to 125°C 350 TPS76733 IO = 1 A, IO = 1 A, TJ = 25°C TJ = −40°C to 125°C 230 TPS76750 IO = 1 A, IO = 1 A, Dropout voltage (1) ms 825 675 mV 575 380 (1) IN voltage equals VO(typ) − 100 mV; TPS76701 output voltage set to 3.3 V nominal with external resistor divider. TPS76715, TPS76718, TPS76725, and TPS76727 dropout voltage limited by input voltage range limitations (i.e., TPS76730 input voltage needs to drop to 2.9 V for purpose of this test). TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO Zo VDO Output voltage vs Output current 2, 3, 4 vs Free-air temperature 5, 6, 7 Ground current vs Free-air temperature 8, 9 Power supply ripple rejection vs Frequency 10 Output spectral noise density vs Frequency 11 Input voltage (min) vs Output voltage 12 Output impedance vs Frequency 13 Dropout voltage vs Free-air temperature Line transient response Load transient response VO 14 15, 17 16, 18 Output voltage vs Time Dropout voltage vs Input voltage Equivalent series resistance (ESR) vs Output current 19 20 22 − 25 7 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TPS76733 TPS76715 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.4985 3.2835 VI = 4.3 V TA = 25°C 3.2830 VI = 2.7 V TA = 25°C 1.4980 1.4975 VO − Output Voltage − V VO − Output Voltage − V 3.2825 1.4970 3.2820 1.4965 3.2815 1.4960 3.2810 1.4955 3.2805 1.4950 3.2800 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IO − Output Current − A 0.9 0 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 IO − Output Current − A Figure 2 Figure 3 TPS76733 TPS76725 OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE OUTPUT VOLTAGE vs OUTPUT CURRENT 3.32 2.4960 VI = 3.5 V TA = 25°C 2.4955 VI = 4.3 V 3.31 VO − Output Voltage − V VO − Output Voltage − V 2.4950 2.4945 2.4940 2.4935 3.30 3.29 IO = 1 A IO = 1 mA 3.28 3.27 2.4930 3.26 2.4925 2.4920 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 IO − Output Current − A Figure 4 8 0.8 0.9 1 3.25 −60 −40 −20 0 20 40 60 80 100 120 140 TA − Free-Air Temperature − °C Figure 5 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TPS76715 TPS76725 OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 2.515 1.515 VI = 3.5 V VI = 2.7 V 2.510 VO − Output Voltage − V 1.505 1.500 IO = 1 A IO = 1 mA 1.495 1.490 2.505 2.500 IO = 1 A 2.495 IO = 1 mA 2.490 2.485 1.485 −60 −40 −20 0 20 40 60 80 2.480 −60 −40 100 120 140 −20 0 20 40 60 80 100 120 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 6 Figure 7 TPS76733 GROUND CURRENT vs FREE-AIR TEMPERATURE 92 90 VI = 4.3 V 88 Ground Current − µ A VO − Output Voltage − V 1.510 86 84 82 IO = 1 mA 80 IO = 1 A 78 IO = 500 mA 76 74 72 −60 −40 −20 0 20 40 60 80 100 120 140 TA − Free-Air Temperature − °C Figure 8 9 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TPS76715 TPS76733 GROUND CURRENT vs FREE-AIR TEMPERATURE POWER SUPPLY RIPPLE REJECTION vs FREQUENCY 90 PSRR − Power Supply Ripple Rejection − dB 100 VI = 2.7 V Ground Current − µ A 95 90 IO = 1 A IO = 1 mA 85 IO = 500 mA 80 75 −60 −40 −20 0 20 40 60 80 VI = 4.3 V Co = 10 µF IO = 1 A TA = 25°C 80 70 60 50 40 30 20 10 0 −10 10 100 120 140 100 1k TA − Free-Air Temperature − °C Figure 9 Figure 10 TPS76733 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY Output Spectral Noise Density − µV Hz 10−5 VI = 4.3 V Co = 10 µF TA = 25°C IO = 7 mA 10−6 IO = 1 A 10−7 10−8 102 103 f − Frequency − Hz Figure 11 10 10k f − Frequency − Hz 104 105 100k 1M www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS INPUT VOLTAGE (MIN) vs OUTPUT VOLTAGE 4 IO = 1 A VI − Input Voltage (Min) − V TA = 25°C TA = 125°C 3 TA = −40°C 2.7 2 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 VO − Output Voltage − V Figure 12 TPS76733 TPS76733 OUTPUT IMPEDANCE vs FREQUENCY DROPOUT VOLTAGE vs FREE-AIR TEMPERATURE 103 0 IO = 1 A VDO − Dropout Voltage − mV Zo − Output Impedance − Ω VI = 4.3 V Co = 10 µF TA = 25°C IO = 1 mA 10−1 IO = 1 A 102 101 IO = 10 mA 100 10−1 IO = 0 Co = 10 µF 10−2 101 102 103 104 f − Frequency − kHz Figure 13 105 106 10−2 −60 −40 −20 0 20 40 60 80 100 120 140 TA − Free-Air Temperature − °C Figure 14 11 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TPS76715 TPS76715 LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE ∆ VO − Change in Output Voltage − mV VI − Input Voltage − V 100 3.7 2.7 Co = 10 µF TA = 25°C 50 0 −50 I O − Output Current − A ∆ VO − Change in Output Voltage − mV −100 10 0 −10 Co = 10 µF TA = 25°C 0 20 40 60 1 0.5 0 0 80 100 120 140 160 180 200 t − Time − µs Figure 16 TPS76733 TPS76733 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 100 ∆ VO − Change in Output Voltage − mV VI − Input Voltage − V Figure 15 Co = 10 µF TA = 25°C 5.3 I O − Output Current − A ∆ VO − Change in Output Voltage − mV 4.3 10 0 −10 0 20 40 60 80 100 120 140 160 180 200 t − Time − µs Figure 17 12 100 200 300 400 500 600 700 800 900 1000 t − Time − µs Co = 10 µF TA = 25°C 50 0 −50 −100 1 0.5 0 0 100 200 300 400 500 600 700 800 900 1000 t − Time − µs Figure 18 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TPS76733 TPS76701 OUTPUT VOLTAGE vs TIME (AT STARTUP) DROPOUT VOLTAGE vs INPUT VOLTAGE 900 IO = 1 A Co = 10 µF IO = 1 A TA = 25°C 3 800 VDO − Dropout Voltage − mV VO− Output Voltage − V 4 2 1 Enable Pulse − V 0 700 600 500 TA = 25°C 400 TA = 125°C 300 200 TA = −40°C 100 0 0 2.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t − Time − ms 0.9 1 Figure 19 VI 3 3.5 4 VI − Input Voltage − V 4.5 5 Figure 20 To Load IN OUT + EN Co GND RL ESR Figure 21. Test Circuit for Typical Regions of Stability (Figures 22 through 25) (Fixed Output Options) 13 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 ESR − Equivalent Series Resistance − Ω ESR − Equivalent Series Resistance − Ω 10 Region of Instability 1 Region of Stability VO = 3.3 V Co = 4.7 µF VI = 4.3 V TA = 25°C 0.1 0 200 400 600 800 Region of Instability VO = 3.3 V Co = 4.7 µF VI = 4.3 V TJ = 125°C 1 Region of Stability 0.1 1000 0 200 IO − Output Current − mA Figure 22 600 800 1000 Figure 23 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 10 ESR − Equivalent Series Resistance − Ω ESR − Equivalent Series Resistance − Ω 400 IO − Output Current − mA Region of Instability 1 Region of Stability VO = 3.3 V Co = 22 µF VI = 4.3 V TA = 25°C 0.1 0 200 400 600 IO − Output Current − mA Figure 24 800 1000 Region of Instability VO = 3.3 V Co = 22 µF VI = 4.3 V TJ = 125°C 1 Region of Stability 0.1 0 200 400 600 800 1000 IO − Output Current − mA Figure 25 (1) Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. 14 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 APPLICATION INFORMATION The TPS767xx family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V, 3.3 V, and 5.0 V), and an adjustable regulator, the TPS76701 (adjustable from 1.5 V to 5.5 V). device operation The TPS767xx features very low quiescent current, which remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/β). The TPS767xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS767xx quiescent current remains low even when the regulator drops out, eliminating both problems. The TPS767xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µA. If the shutdown feature is not used, EN should be tied to ground. minimum load requirements The TPS767xx family is stable even at zero load; no minimum load is required for operation. FB—pin connection (adjustable version only) The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option . The output voltage is sensed through a resistor divider network to close the loop as shown in Figure 27. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit to improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is essential. external capacitor requirements An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improves load transient response and noise rejection if the TPS767xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Like all low dropout regulators, the TPS767xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the ESR (equivalent series resistance) must be between 50 mΩ and 1.5 Ω. Capacitor values 10 µF or larger are acceptable, provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Most of the commercially available 10 µF surface-mount ceramic capacitors, including devices from Sprague and Kemet, meet the ESR requirements stated above. 15 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 APPLICATION INFORMATION external capacitor requirements (continued) TPS767xx 6 VI 7 IN RESET 5 RESET 250 kΩ IN OUT C1 0.1 µF 16 EN OUT 14 VO 13 + GND Co 10 µF 3 Figure 26. Typical Application Circuit (Fixed Versions) programming the TPS76701 adjustable LDO regulator The output voltage of the TPS76701 adjustable regulator is programmed using an external resistor divider as shown in Figure 27. The output voltage is calculated using: V O +V ǒ1 ) R1 Ǔ R2 ref (1) Where: ref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using: R1 + ǒ V V Ǔ O *1 ref R2 (2) OUTPUT VOLTAGE PROGRAMMING GUIDE TPS76701 VI 0.1 µF IN RESET 250 kΩ ≥ 1.7 V ≤ 0.9 V Reset Output EN OUT VO R1 FB / NC GND Co OUTPUT VOLTAGE R1 UNIT 2.5 V 33.2 30.1 kΩ 3.3 V 53.6 30.1 kΩ 3.6 V 61.9 30.1 kΩ 4.75 V 90.8 30.1 kΩ R2 Figure 27. TPS76701 Adjustable LDO Regulator Programming 16 R2 www.ti.com SLVS208I − MAY 1999 − REVISED JANUARY 2004 APPLICATION INFORMATION reset indicator The TPS767xx features a RESET output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as a low-battery indicator. RESET does not assert itself when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low relative to its nominal regulated value (refer to timing diagram for start-up sequence). regulator protection The TPS767xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS767xx also features internal current limiting and thermal protection. During normal operation, the TPS767xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P T max * T A + J D(max) R θJA Where: TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal SOIC and 32.6°C/W for the 20-terminal PWP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: P D ǒ Ǔ + V *V I O I O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. 17 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS76701QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76701QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76701QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76701QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76715QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76715QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) TPS76715QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76715QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76718QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76718QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76718QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76718QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76725QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76725QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76725QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76725QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76727QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76727QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76727QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76727QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76728QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76728QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76728QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76728QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76730QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76730QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76730QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76730QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76733QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76733QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76733QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS76733QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS76750QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76750QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS76750QPWP ACTIVE HTSSOP PWP 20 70 TBD CU NIPDAU Level-1-220C-UNLIM TPS76750QPWPR ACTIVE HTSSOP PWP 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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