SL2610 Wide Dynamic Range Image Reject MOPLL Data Sheet Features October 2004 • Single chip mixer/oscillator PLL combination for multi band tuner for DTT applications • Each mixer oscillator band optimized for wide dynamic range • RF input stages allow for either single-ended or differential drive • PLL frequency synthesizer designed for low phase noise performance • Broadband output level detect with onset adjust • PLL frequency synthesizer compatible with standard digital terrestrial offsets • Four integrated switching ports • I2C fast mode compliant • ESD protection (Normal ESD handling procedures should be observed) Ordering Information SL2610/IG/LH1Q SL2610/IG/LH1N SL2610/IG/LH2Q SL2610/IG/LH2N Terrestrial digital receiver systems • Terrestrial analogue receiver systems • Cable receiver systems • Data communications systems Pin Pin Pin Pin MLP MLP MLP MLP Tape & Reel, Bake & Drypack Trays, Bake & Drypack Tape & Reel, Bake & Drypack* Trays, Bake & Drypack* *Leadfree -40°C to +85°C Description The SL2610 is a mixer oscillator intended primarily for application in all band tuners, where it performs image reject downconversion of the RF channel to a standard 36 MHz or 44 MHz IF. Each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank. The band outputs share a common low impedance SAWF driver stage. Applications • 40 40 40 40 Frequency selection is controlled by the on-board I2C bus frequency synthesizer. This block also controls four general purpose switching ports for selecting the prefilter/AGC stages. LO HI MID BAND BAND BAND PROG DIVIDER CHARGE PUMP ~ ~ ~ DRIVE IF SELECT XTAL XTALCAP REF DIVIDER ~ CONVOP CONVOPB IFIP IFIPB IFOP IFOPB AGC BIAS AGC OUT PORT P0 PORT P1 PORT P2 PORT P3 Port Interface I2C Interface HI LO MID BAND BAND BAND SDA SCL ADD Figure 1 - SL2610 Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. SL2610 Data Sheet The SL2610 has high intermodulation intercept performance so offering high signal to spurious performance in the presence of higher amplitude interferers or in the presence of a wide bandwidth composite input signal. VccLO LOHIIPB LOHIOPB LOHIOP LOHIIP VccLO LOMIDOPB LOMIDOP LOLOWOP LOLOWOPB An output broadband level detect circuit is included for control of the tuner front end AGC. PORT P3 IFOPB Pin 1 VccRF IFOP HI INPUT AGCBIAS HI INPUTB VCCIF PORT P2 IFIPB PORT P1 IFIP MID INPUT ADD MID INPUTB CONVOP VccRF CONVOPB LO INPUT SCL SDA XTAL XTAL CAP CHARGE PUMP DRIVE PORT P0 VccRF AGCOUT LO INPUTB VEE (PACKAGE PADDLE) VccDIG LH40 Figure 2 - Pin Allocation Diagram Quick Reference Data Characteristics Frequency range: Units LOW band 50-500 MHz MID band 50-500 MHz HIGH band 200-900 MHz 32 ± 2 dB Noise figure 13 dB Typical Image Reject 35 dB P1dB input referred, Converter section only 106 dBuV IP3 input referred, Converter section only 14 dBm IP2 input referred, Converter section only 48 dBm LO phase noise (free running) @ 10 kHz offset -90 dBc/Hz @ 100 kHz offset -110 dBc/Hz -158 dBc/Hz 3 dBm Conversion gain * PLL phase noise Maximum composite output amplitude * Assuming 2 dB shaping filter loss in external IF path. 2 Zarlink Semiconductor Inc. +5V Figure 3 - SL2610 Evaluation Board Schematic 750R R15 750R R14 750R R13 750R R12 D4 1nF C7 VT 1nF C8 1nF 10 9 8 7 6 5 4 3 gnd 18K R9 gnd 10nF C34 +5V LO INPUT Vcc RF MID IP B MID INPUT PORT P1 PORT P2 HIGH IP B HIGH IP Vcc RF PORT P3 P3 1n5F gnd gnd C5 P1 P2 C6 1nF 1nF C4 1nF C3 2 4K7 P3 1 R1 1u5H L2 C21 +5V gnd gnd 10nF C29 gnd 20R R16 C1 100pF D7 P3 P2 P1 P0 gnd gnd 10nF C35 gnd gnd +5V 6p8F C2 BB640 D1 P2 D6 P1 D5 P0 SK3 RF IN (LOW) LOW IN MID IN SK2 HI IN SK1 RF IN (MID) RF IN (HIGH) L1 120nH 10K R20 gnd 20K R8 +30V gnd 4K7 R4 100pF D2 82nH L4 BB640 38 LOMIDOP C9 SL2610 L6 2p2 10R R18 2p2 C12 C13 22nH L5 BB555 D3 Vee = Pin 0 = PACKAGE PADDLE BCW31 TR1 TP TP1 10R IC1 R17 10nF 2p2 C11 C30 gnd +5V 7pF C10 gnd 4K7 R6 100pF 14 39 36nH C16 1K 33K R7 100nF C17 15 LOLOWOPB Vcc RF 12 L3 R3 DRIVE 1K 16 R2 CHARGE PUMP VT XTAL CAP gnd 47pF C20 47pF C18 17 40 11 8n2H 18 LOLOWOP LO INPUT B 35 LOHII/P 37 PORT P0 P0 AGC OUT 13 LOMIDOPB 34 LOHIO/P 36 VccLO 33 1K 4 MHz X1 47pF C19 19 LOHIO/PB XTAL 32 5pF 10R 2p2 10nF C32 Vcc DIG CONV OP B CONV OP ADD IF INPUT IF INPUT B Vcc IF AGC BIAS IF O/P IF O/P B gnd C15 R19 C14 LOHII/PB SDA 31 VccLO SCL 20 Zarlink Semiconductor Inc. Gnd 3 gnd 0 gnd +5V 21 22 23 24 25 26 27 28 29 30 5:1 T1 R11 4K7 4K7 +5V 82pF C27 82pF C26 10nF 10nF R10 10nF C31 1nF C25 1nF C24 C23 C22 +5V +30V gnd 3 4 5 6 220nH L8 220nH L7 2 +5V I2C SDA VDD GND SCL CN1 gnd AGC gnd ADDRESS 10K VR1 I2C Control IF OUT IF OUT SK4 POWER ADDRESS CN3 10nF C33 gnd TP TP2 +5V +5V CN2 GND +30V 2 gnd +5V 470uF C36 gnd 100nF gnd gnd gnd C28 1 3 1 3 R5 SL2610 Data Sheet SL2610 Figure 4 - SL2610 Evaluation Board Layout (Top) Figure 5 - SL2610 Evaluation Board Layout (Bottom) 4 Zarlink Semiconductor Inc. Data Sheet SL2610 1.0 Data Sheet Functional Description The SL2610 is a multi band RF mixer oscillator with image reject and on-board frequency synthesizer. It is intended primarily for application in all band terrestrial tuners and requires a minimum external component count. It contains all elements required for RF downconversion to a standard IF with the exception of external VCO tank circuits. The pin allocation is contained in Figure 2 and the block diagram in Figure 1. 1.1 Mixer/oscillator section In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner prefilter and AGC stages. The mixer input is arranged such that the signal can be coupled either differentially or single-ended, and achieves the specified minimum performance in both configurations. Band input impedances and NF are contained in Figure 11 and Figure 12 respectively. The converter two tone input spectra are contained in Figure 13 and Figure 14. The preamplifier output then feeds the mixer stage where the required channel is image reject downconverted to the IF frequency. The local oscillator frequency for the downconversion is obtained from the on board local oscillator, which uses an external varactor tuned tank. Typical VCO applications are contained in Figures 8, 9 and 10. The output of the mixer is then fed to the converter output driver which presents a matched 200 Ω differential load to an external IF shaping filter. The output of the shaping filter is then coupled into the IFAMP stage, which provides further gain and offers a 50 Ω output impedance to interface direct with the tuner SAW filter. The SL2610 contains a broadband level detect circuit whose output can be used to control the tuner AGC. The target level of the AGC detector is controlled by the voltage applied to the AGCBIAS pin. The characteristic of the target level is given in Figure 18. 1.2 PLL Frequency Synthesizer The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency reference and loop filter, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers. The LO signal is multiplexed from the selected oscillator section to an internal preamplifier which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider which is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits and the M counter is 11 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1. The output of the phase detector feeds a charge pump and loop amplifier section which when used with an external loop filter integrates the current pulses into the varactor line voltage. The programmable divider output Fpd, divided by two and the reference divider output Fcomp, can be switched to port P0 by programming the device into test mode. The test modes are described in Table 5. 5 Zarlink Semiconductor Inc. SL2610 2.0 Data Sheet Programming The SL2610 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesizer can either accept data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. Tables 2 and 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesizer in an I2C bus system (Tables 2 and 3). Table 4 shows how the address is selected by applying a voltage to the ‘ADD’ input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period the device generates an internal STOP condition which inhibits further reading. 2.1 Write mode With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the reference divider ratio bits R4-R0 (Table 1) and the charge pump setting bits C1-C0 (Table 6). Byte 5 controls the IF select (Table 8), the band select function bits BS1-BS0 (Table 7), the switching ports P3-P0 and the test modes (Table 5). After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2 and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. 2.2 Read mode When the device is in read mode, the status byte read from the device takes the form shown Table 3. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3V (at 25oC), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to power up condition. Bit 2 (FL) indicates whether the device is phase locked, a logic '1' is present if the device is locked and a logic '0' if the device is unlocked. 6 Zarlink Semiconductor Inc. SL2610 2.3 Data Sheet Programmable features Synthesiser programmable divider Function as described above. Reference programmable divider Function as described above. Band selection The required mixer oscillator band and RF input is selected by bits BS1-BS0, within data byte 5, as defined in Table 7. IF selection The centre of the image reject passband is selected by IF as defined in Table 8. Charge pump current The charge pump current can be programmed by bits C1-C0 within data byte 4, as defined in Table 6. Ports P3-P0 These are configured as NPN open collector buffers and programmed by bits P3P0. Logic ‘1’ = on. Logic ‘0’ = off (high impedance); default on power up. In test modes, when TE=1, ports P3-P0 respond according to T2-T0 respectively and previously transmitted data is lost. Test mode The test modes are invoked by setting bits T2–T0 as described in Table 5. 7 Zarlink Semiconductor Inc. SL2610 Data Sheet R4 R3 R2 R1 R0 Ratio 0 0 0 0 0 2 0 0 0 0 1 4 0 0 0 1 0 8 0 0 0 1 1 16 0 0 1 0 0 32 0 0 1 0 1 64 0 0 1 1 0 128 0 0 1 1 1 256 0 1 0 0 0 not allowed 0 1 0 0 1 5 0 1 0 1 0 10 0 1 0 1 1 20 0 1 1 0 0 40 0 1 1 0 1 80 0 1 1 1 0 160 0 1 1 1 1 320 1 0 0 0 0 not allowed 1 0 0 0 1 6 1 0 0 1 0 12 1 0 0 1 1 24 1 0 1 0 0 48 1 0 1 0 1 96 1 0 1 1 0 192 1 0 1 1 1 384 1 1 0 0 0 not allowed 1 1 0 0 1 7 1 1 0 1 0 14 1 1 0 1 1 28 1 1 1 0 0 56 1 1 1 0 1 112 1 1 1 1 0 224 1 1 1 1 1 448 Table 1 - Reference Division Ratio 8 Zarlink Semiconductor Inc. SL2610 Data Sheet MSB LSB Address 1 1 0 0 0 MA1 MA0 0 A Byte 1 Programmable divider 0 214 213 212 211 210 29 28 A Byte 2 Programmable divider 27 26 25 24 23 22 21 20 A Byte 3 Control data 1 C1 C0 R4 R3 R2 R1 R0 A Byte 4 Control data IF BS1 BS0 TE P3/T2 P2/T1 P1/T0 P0 A Byte 5 Table 2 - Write Data Format (MSB is transmitted first) MSB Address Status Byte LSB 1 1 0 0 0 MA1 MA0 1 A Byte 1 POR FL 0 0 0 0 0 0 A Byte 2 Table 3 - Read Data Format (MSB is transmitted first) A MA1,MA0 : Acknowledge bit : Variable address bits (see Table 4) 0 : Programmable division ratio control bits R4-R0 : Reference division ratio select (see Table 1) C1,C0 : Charge pump current select (see Table 6) BS1-BS0 : Band select bits (see Table 7) IF : IF passband select (see Table 8) TE : Test mode enable T2-T0 : Test mode control bits when TE=1 (see Table 5) P3-P0 : P3-P0 port output states POR : Power on reset indicator FL : Phase lock flag 14 2 -2 9 Zarlink Semiconductor Inc. SL2610 Data Sheet MA1 MA0 Address Input Voltage Level 0 0 0-0.1Vcc 0 1 Open circuit 1 0 0.4Vvcc – 0.6 Vcc # 1 1 0.9 Vcc - Vcc # Programmed by connecting a 30 kΩ resistor between pin and Vcc Table 4 - Address Selection TE T2 T1 T0 Test Mode Description 0 X X X Normal operation 1 0 0 0 Normal operation 1 0 0 1 Charge pump sink * Status byte FL set to logic ‘0’ 1 0 1 0 Charge pump source * Status byte FL set to logic ‘0’ 1 0 1 1 Charge pump disabled * Status byte FL set to logic ‘1’ 1 1 0 0 Normal operation and Port P0 = Fpd/2 1 1 0 1 Charge pump sink * Status byte FL set to logic ‘0’ Port P0 = Fcomp 1 1 1 0 Charge pump source * Status byte FL set to logic ‘0’ Port P0 = Fcomp 1 1 1 1 Charge pump disabled * Status byte FL set to logic ‘1’ Port P0 = Fcomp Table 5 - Test Modes * crystal and selected local oscillator need signals to enable charge pump test modes and to toggle status byte bit FL X -’don’t care’ 10 Zarlink Semiconductor Inc. SL2610 C1 Data Sheet Current in µA C0 Min. Typ. Max. 0 0 +85 +130 +175 0 1 +190 +280 +370 1 0 +420 +600 +780 1 1 +930 +1300 +1670 Table 6 - Charge pump current BS1 BS0 Band Selected 0 0 LO Band 0 1 MID Band 1 0 HI band 1 1 HI band Table 7 - Band select IF input Centre of Image Reject Passband Passband Bandwidth 0 57 MHz 6 MHz 0 44 MHz 6 MHz 1 36 MHz 8 MHz Table 8 - IF SELECT function 11 Zarlink Semiconductor Inc. SL2610 Data Sheet XTALCAP 47 pF SL2610 XTAL 47 pF Figure 6 - Crystal Oscillator Application to 50 Ω load IFOPB SL2610 5:1 IFOP Figure 7 - Ifamp Output Load Condition for Test Purposes C2 L1 120nH 7pF R16 20R D1 BB640 R1 R2 1K 4K7 C1 L2 1u5H 100pF LOLOWOP LOLOWOPB Figure 8 - LO Band VCO Application 12 Zarlink Semiconductor Inc. VT SL2610 Data Sheet VT R3 1K L3 36nH C9 100pF R4 4K7 D2 BB640 C10 7pF L4 82nH LOMIDOP LOMIDOPB Figure 9 - Mid Band VCO Application VT R5 L6 1K 8.2nH C16 100pF C15 D3 R6 BB555 L5 4K7 5pF 22nH R19 10R C11 2p2 C12 C13 2p2 2p2 C14 2p2 R18 10R R17 10R LOHIIP LOHIOP LOHIOPB LOHIIPB Figure 10 - HI Band VCO Application 13 Zarlink Semiconductor Inc. SL2610 CH1 S 11 1 U FS Data Sheet 12 Mar 2002 15:10:11 -12.117 145.94 pF 1_: 152.31 DEV1 VCC=4.7V 90.000 000 MHz PRm 2_: 150.74 -34.063 220 MHz Cor 3_: 133.48 -62.813 500 MHz 4_: 111.79 -86.926 900 MHz 1 2 3 4 START 50.000 000 MHz STOP 900.000 000 MHz Figure 11 - LO, MID and HI Band Input Impedance Figure 12 - Low, Mid and Hi Band Noise Figure versus Frequency 14 Zarlink Semiconductor Inc. SL2610 Data Sheet IIM3; -42 dBc Incident power from 50Ω source -14 dBm -56 dBm df (6 MHz) f1-df f1 f2 f2+df -14 dBm IIM2; -40 dBc Incident power from 50Ω source Figure 13 - Converter Third Order Two Tone Intermodulation Test Condition Spectrum, Input Referred, All Bands -54 dBm X df f2-f1 f1 f2 Figure 14 - Second Order Two Tone Intermodulation Test Condition Spectrum, Input Referred 15 Zarlink Semiconductor Inc. SL2610 CH1 S 11 1 U FS Data Sheet 26 Nov 2002 13:38:57 -8.0313 347.67 pF 3_: 101.43 DEV4 5.3V 57.000 000 MHz PRm 1_: 102.92 -5.043 36 MHz 2_: 102.48 -6.4883 44 MHz 3 1 2 START 32.000 000 MHz STOP 60.000 000 MHz Figure 15 - Converter Output Impedance (Single Ended) CH1 S 11 1 U FS 27 Nov 2002 09:17:33 11.094 49.045 nH 1_: 173.88 36.000 000 MHz PRm C? 2_: 178.89 10.016 44 MHz Avg 16 3_: 185.77 04.922 57 MHz 1 23 START 30.000 000 MHz STOP 60.000 000 MHz Figure 16 - IFAMP Input Impedance 16 Zarlink Semiconductor Inc. SL2610 CH1 S 11 1 U FS Data Sheet 27 Nov 2002 08:59:45 8.8438 39.098 nH 1_: 58.967 36.000 000 MHz PRm 2_: 59.295 11.096 44 MHz 3_: 60.443 14.813 57 MHz 1 3 2 START 30.000 000 MHz STOP 60.000 000 MHz Figure 17 - IFAMP Output Impedance (Single Ended) 120 Output Level (dBΗV) 115 110 105 100 0 1 2 3 4 5 AGCBIAS Voltage (V) Figure 18 - Typical AGC Output Level Set versus AGCBIAS Voltage 17 Zarlink Semiconductor Inc. 6 SL2610 Data Sheet Electrical Characteristics Test conditions (unless otherwise stated) Tamb = -40oC to 85oC, Vee= 0 V, Vcc=Vcca=Vccd = 5 V +5% These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Min. Supply current Typ. Max. Units 163 196 mA 500 MHz Conditions All switching ports off. LO or MID BAND ENABLED Input frequency range 50 Input impedance See Figure 11 and refer to Note 8. Input Noise Figure 13 dB Tamb=27oC, see Figure 12, refer to Note 2, no correction for external filtering. Converter gain 10 8.5 14 12.5 dB dB At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 Ω single ended source to differential 200 Ω load, refer to Note 3. Conversion gain to IFAMP output 28 25 36 33 dB dB At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 Ω single ended source to 50 Ω single-ended load with output transformer as in Figure 7, see Notes 2 and 3. 1 dB Channel bandwidth 8 MHz within operating frequency range, see note (2), excluding interstage shaping filter ripple. dBm See Figure 14 and refer to Notes 4 and 6. Assuming ideal power match. dBc See Figure 14 and refer to Notes 4 and 6. dBm See Figure 13 and refer to Notes 4 and 6. Assuming ideal power match. dBc See Figure 13 and refer to Notes 4 and 6. Gain variation within channel Converter input referred IP2 0.4 26 Converter input referred IM2 Converter input referred IP3 -40 7 Converter input referred IM3 -42 dBµV Input referred P1dB 101 Local oscillator operation range 50 550 MHz Refer to Note 7. Local oscillator tuning range 68 200 225 465 MHz MHz With application as in Figure 8. With application as in Figure 9. 18 Zarlink Semiconductor Inc. SL2610 Characteristic Pin Min. Typ. LO phase noise, SSB @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset Data Sheet Max. Units -55 -86 -109 dBc/Hz dBc/Hz dBc/Hz Conditions With application as in Figure 8 and Figure 9 outside of PLL loop bandwidth. kHz/oC Application as in Figure 8 and Figure 9. No temperature compensation. 100 kHz Application as in Figure 8 and Figure 9, frequency drift over 15 minute period from turn on at a fixed ambient temperature. No temperature compensation. LO to RF input leakage 60 dBµV LO Vcc stability 0.5 MHz/V LO spurs due to RF pulling -52 dBc 870 MHz LO temperature stability 80 LO turn on drift Application as in Figures 8 and 9. See Note 5. HI BAND ENABLED Input frequency range 200 Input impedance See Figure 11 and refer to Note 8. Input Noise Figure 13.5 dB Tamb=27oC, see Figure 12, refer to Note 2, no correction for external filtering. Converter gain 10 8.5 14 12.5 dB dB At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 Ω single ended source to differential 200 Ω load, refer to Note 3. Conversion gain to IFAMP output 28 25 36 33 dB dB At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 Ω single ended source to 50 Ω single-ended load with output transformer as in Figure 7, see Notes 2 and 3. 1 dB Channel bandwidth 8 MHz within operating frequency range, see Note 3, excluding interstage shaping filter ripple. dBm See Figure 14 and refer to Notes 4 and 6. Assuming ideal power match. Gain variation within channel Converter input referred IP2 0.4 26 19 Zarlink Semiconductor Inc. SL2610 Characteristic Pin Min. Typ. Converter input referred IM2 Converter input referred IP3 Max. Units -40 dBc See Figure 14 and refer to Notes 4 and 6. dBm See Figure 13 and refer to Notes 4 and 6. Assuming ideal power match. dBc See Figure 13 and refer to Notes 4 and 6. 7 Converter input referred IM3 Data Sheet -42 Conditions Input referred P1dB 101 dBµV Local oscillator operation range 200 1000 MHz Refer to Note 7. Local oscillator tuning range 440 950 MHz With application as in Figure 10. -55 -86 -109 dBc/Hz dBc/Hz dBc/Hz 110 kHz/oC LO phase noise, SSB @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset LO temperature stability LO turn on drift 100 kHz LO to RF input leakage 60 dBµV LO Vcc stability 0.5 MHz/V LO spurs due to RF pulling -52 dBc With application as in Figure 10, outside of PLL loop bandwidth. Application as in Figure 10. No temperature compensation. Application as in Figure 10, frequency drift over 15 minute period from turn on at a fixed ambient temperature. No temperature compensation. Application as in Figure 10. See Note 5. All Bands Converter output impedance Image rejection Isolation between band inputs 25 29 25 200 Ω Differential, see Figure 15. 30 35 30 dB dB dB At 36 MHz IF frequency, IF bit = 1. At 44 MHz IF frequency, IF bit = 0. At 57 MHz IF frequency, IF bit = 0. See Table 8. Tamb = 0oC to +85oC. Tank Schematics and layouts as in recommended application. See Figures 4 and 5. -60 dBc Level of desired signal converted to IF output through disabled band relative to signal converted through enabled band. 3 dBm Composite output amplitude 20 Zarlink Semiconductor Inc. SL2610 Characteristic Pin Min. Typ. Data Sheet Max. Units 60 MHz Conditions IFAMP Input frequency range 32 Input impedance 200 Gain 20 18.5 Output impedance 24 22.5 100 Ω Differential, see Figure 16. dB dB At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Voltage conversion gain from 200 Ω differential source to differential load as contained in Figure 7, see Note 3. Ω Differential, see Figure 17. Output limiting 3 2.7 Vp-p Vp-p At 36 MHz and 44 MHz IF fequency. At 57 MHz IF frequency. Differential into load as in Figure 7. IFAMP OPIP3 135 dBµV Two output tones at 2 MHz separation at 104 dBuV into load as in Figure 7, see Note 2. -62 dBc Two output tones at 2 MHz separation at 104 dBuV into load as in Figure 7, see Note 2. IFAMP OPIM3 AGCBIAS Leakage current 28 -100 -50 100 50 µA µA Vee ≤ Vagc1 ≤ Vcc 1.5V ≤ Vagc1 ≤ 3.5V AGCOUT voltage range 13 0.5 3 V Max load current 20 µA. AGC output level set See Figure 18. Supply rejection -52 dBc 5.5 1.5 10 10 V V µA µA Spurs introduced on converted output relative to desired signal by a supply ripple voltage of 10 mV p-p in the range 1 kHz to 100 kHz (including external supply decoupling). Synthesiser SDA, SCL Input high voltage Input low voltage Input current Leakage current 19, 20 Hysterysis 19, 20 3 0 -10 0.4 Input voltage =Vee to Vcc Input voltage = Vee to 5.5 V, Vcc=Vee V SDA output voltage 19 0.4 0.6 V V SCL clock rate 20 400 kHz 21 Zarlink Semiconductor Inc. Isink = 3 mA Isink = 6 mA SL2610 Characteristic Pin Min. Charge pump output current 16 Charge pump output leakage 16 Charge pump drive output current 15 0.5 Crystal frequency 17, 18 4 Recommended crystal series resonance Typ. Max. Data Sheet Units Conditions See Table 6. Vpin16 = 2 V +3 +10 nA Vpin16 = 2 V mA Vpin15 = 0.7 V 16 MHz Application as in Figure 6. 10 200 Ω 4 MHz parallel resonant crystal. External reference input frequency 17, 18 4 20 MHz Sinewave coupled through 10 nF blocking capacitor. External reference drive level 18 0.2 0.5 Vpp Sinewave coupled through 10 nF blocking capacitor. .03125 0.25 MHz Phase detector comparison frequency With 4 MHz crystal, SSB, within loop bandwidth. With Fcomp = 125 kHz Equivalent phase noise at phase detector -158 RF division ratio 240 32767 Reference division ratio Switching ports P0-P3 sink current leakage current Address select Input high current Input low current See Table 1. 1, 5, 6, 14 10 10 mA µA Vport = 0.7 V Vport = Vcc 1 -0.5 mA mA See Table 4. Vin=Vcc Vin=Vee 24 Notes 1 All power levels are referred to 50 Ω, and 0 dBm = 107 dBµV. 2 Total system with final load as in Figure 7, including an interstage IF shaping filter with IL of 2 dB and characteristic impedance of 200 Ω differential. 3 The specified gain is determined by the following formula; Gs = Gm + Vtr where Gs = gain as specified Gm = gain as measured with specified load conditions Vtr = voltage transformation ratio of transformer as in Figure 7 4 Two input tones within RF operating range at -14 dBm from 50 Ω single ended source with 200 Ω differential output load. DC output current must be shunted to Vcc through suitable inductor, i.e. 10 µH. 5 Modulation spurs introduced on local oscillator through injection locking of the local oscillator by an undesired RF carrier. Desired carrier at 80 dBµV, undesired carrier at 90 dBµV at an offset frequency of fd plus 42+fc MHz, where fd is desired carrier frequency, fc is US chrominance sub carrier and 42 equals 7 channel spacings. 6 All intermodulation specifications are measured with a single-ended input. 7 Operation range is defined as the region over which the oscillator presents a negative impedance. 8 Target to achieve 6 dB minimum S11. 22 Zarlink Semiconductor Inc. SL2610 Data Sheet Absolute Maximum Ratings All voltages are referred to Vee at 0 V. Characteristic Min. Max. Units Supply voltage -0.3 6 V 117 dBµV Vcc+0.3 V 20 mA RF input voltage All I/O port DC offsets -0.3 Total port current 150 o C Junction temperature 125 o C Package thermal resistance, chip to ambient 27 Power consumption at 5.25V 1 Storage temperature ESD protection -55 o C/W Conditions Transient condition only. Power applied. Package paddle soldered to ground. W 1 kV 23 Zarlink Semiconductor Inc. Mil-std 883B method 3015 cat1 SL2610 Data Sheet VCC VCC 50 Ω 29 4, 8, 11 IPB 3, 7, 10 IP IFOPB Typical 133-j62 Ω @ 500 MHz (see Figure 10) IFOP 30 50 Ω 1 nF External to Chip LOW, MID, HI, RF Input IF Output VCC 400 Ω 400 Ω 34 LOHIOP 13 33 AGCOUT LOHIIP Vbias 20K LOHIOPB 35 500 Ω 32 LOHIPB AGC Out LOHI Input & Output LOLOWOP 38 LOMIDOP 40 100 Ω 100 Ω 23 22 CONVOPB CONVOP 37 LOLOWOPB 39 LOMIDOPB Vbias LOLOW and LOMID Outputs Converter Output VCC VCC IFIP 25 IFIPB 26 95 Ω 1.38 K 28 40 K AGCBIAS 9K 2.4 V AGCBIAS Input IF Input Figure 19 - Input and Output Interface Circuits (RF Section) 24 Zarlink Semiconductor Inc. SL2610 Data Sheet Vccd Vccd 16 XTAL 18 PUMP 13 XTALCAP 17 220 200 µA 15 DRIVE Loop amplifier Reference oscillator Vccd Vccd 120 K 500 K SCL/SDA * 24 ADD 40 K ACK * On SDA only SDA/SCL (pins 19 and 20) ADD input P0, P1, P2, P3 Output Ports (pins 1, 5, 6, 14) Figure 20 - Input and Output Interface Circuits (PLL Section) 25 Zarlink Semiconductor Inc. See Note 8. 1 Package Code c Zarlink Semiconductor 2004 All rights reserved. ISSUE ACN DATE APPRD. 0.80 Previous package codes Package Outline for 40 Lead QFN Pull back lead (6 x 6 x 0.9 mm) For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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