ZARLINK SL2101CNP2Q

SL2101
Synthesized Broadband Converter with
Programmable Power
Data Sheet
Features
August 2004
•
Single chip synthesized broadband solution
•
Configurable as both up converter and
downconverter requirements in double
conversion tuner applications
•
Incorporates 8 programmable mixer power
settings
•
Compatible with digital and analogue system
requirements
•
CSO -65 dBc, CTB -68 dBc (typical)
•
Extremely low phase noise balanced local
oscillator, with very low fundamental and
harmonic radiation
•
PLL frequency synthesizer designed for high
comparison frequencies and low phase noise
•
Buffered crystal output for pipelining system
reference frequency
•
I2C Controlled
Ordering Information
SL2101C/KG/NP1P
SL2101C/KG/NP1Q
SL2101C/KG/NP2P
SL2101C/KG/NP2Q
SL2101C/KG/LH2N
SL2101C/KG/LH2Q
Double conversion tuners
•
Digital Terrestrial tuners
•
Cable telephony
•
Cable Modems
•
MATV
Tubes
Tape & Reel
Tubes
Tape & Reel
Trays
Tape& Reel
* Pb free
All codes baked and drypacked
-40°C to +85°C
Description
The SL2101 is a fully integrated single chip broadband
mixer oscillator with low phase noise PLL frequency
synthesizer. It is intended for use in double conversion
tuners as both the up and down converter and is
compatible with HIIF frequencies up to 1.4 GHz and all
standard tuner IF output frequencies. It also contains a
programmable power facility for use in systems where
power consumption is important.
Applications
•
SSOP
SSOP
SSOP*
SSOP*
MLP*
MLP*
The device contains all elements necessary, with the
exception of local oscillator tuning network, loop filter
and crystal reference to produce a complete
synthesized block converter, compatible with digital
and analogue requirements.
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
SL2101
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XTAL CAP
XTAL
SDA
SCL
BUFREF
Vccd
Vee
Vee
RF
RFB
Vee
VccRF
Vee
IFOUTPUTB
Data Sheet
PUMP
DRIVE
PORT P0
Vee
ADD
Vee
VccLO
LOB
LO
VccLO
Vee
VccLO
Vee
IFOUTPUT
NP 28
PORT P0
DRIVE
PUMP
XTAL
XTAL CAP
SDA
SCL
Figure 2 - Pin Diagram SSOP Package
Vccd
1
28 27 26 25 24 23 22
21
nc
2
20
nc
nc
3
19
VccLO
RF
4
18
LOB
RFB
5
17
LO
nc
6
16
VccLO
VccRF
7
15
10 11 12 13 14
nc
VccLO
nc
IFOUT
nc
nc
9
IFOUTPUTB
8
nc
Vee to pad
under package
Pin 1 Ident
ADD
Figure 3 - Pin Diagram MLP Package
2
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Quick Reference Data
All data applies at maximum power setting with the following conditions unless otherwise stated;
a) nominal loads as follows;
1220 MHz output load as in Figure 4
44 MHz output load as in Figure 5
b) input signal per carrier of 63 dBµV
Characteristic
Units
RF input operating range
50-1400
MHz
Input noise figure, SSB,
50-860 MHz
860-1400
6.5 - 8.5
8.5 - 12
dB
dB
Conversion gain
12
dB
CTB (fully loaded matrix)
-68
dBc
CSO (fully loaded matrix)
-65
dBc
P1 dB input referred
110
dBµV
Local oscillator phase noise as upconverter
SSB @ 10 kHz offset
SSB @ 100 kHz offset
-90
-112
dBc/Hz
dBc/Hz
Local oscillator phase noise as downconverter
SSB @ 10 kHz offset
SSB @ 100 kHz offset
-93
-115
dBc/Hz
dBc/Hz
Local oscillator phase noise floor
-136
dBc/Hz
PLL spurs on converted output with input @ 60 dBµV
<-70
dBc
4
MHz
-152
dBc/Hz
PLL maximum comparison frequency
PLL phase noise at phase detector
*dBm assumes a 75 Ω characteristic impedance, and 0 dBm = 109 dBµV
Functional Description
The SL2101 is a broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL frequency
synthesizer, optimized for application in double conversion tuner systems as both the up and down converter. It
also has application in any system where a wide dynamic range broadband synthesized frequency converter is
required.
The SL2101 is a single chip solution containing all necessary active circuitry and simply requires an external
tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in Figures 2
and 3 for the SSOP and MLP packages and the block diagram in Figure 1.
The device also contains a programmable facility to adjust the power in the lna/mixer so allowing power to be
traded against intermodulation performance for power critical applications, such as telephony modems.
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
Converter Section
In normal application the RF input is interfaced through appropriate impedance matching and an AGC front end to
the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region
of 50 to 1400 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite
distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the
mixer section and back isolation from the local oscillator section.
The lna/mixer current and hence signal handling and device power consumption are programmable through the I2C
bus as tabulated in Figure 7.
The typical RF input impedance and matching network for broadband upconversion are contained in Figures 8 and
9 respectively and for narrow band downconversion in Figures 10 and 11 respectively. The input referred two tone
intermodulation test condition spectrum at maximum power setting is shown in Figure 12. The typical input NF and
gain versus frequency and NF specification limits, over selectable power settings are contained in Figures 13, 14
and 15 respectively.
The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this
stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The
oscillator block uses an external tuneable network and is optimized for low phase noise. The typical oscillator
application as an upconverter is shown in Figure 16 and the typical phase noise performance in Figure 17. The
typical oscillator application as a downconverter is shown in Figure 18, and the phase noise performance in Figure
19. This oscillator block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator.
Finally the output of the mixer provides an open collector differential output drive. The device allows for selection of
an IF in the range 30-1400 MHz so covering standard HIIFs between 1 and 1.4 GHz and all conventional tuner
output IFs. When used as a broadband upconverter to a HIIF the output should be differentially loaded, for example
with a differential SAW filter, to maximize intermodulation performance. A nominal load in maximum power setting is
shown in Figure 4, which will typically be terminated with a differential 200 load. When used as a narrowband
downconverter the output should be differentially loaded with a discrete differential to single ended converter as in
Figure 5, shown tuned to 44 MHz IF. Alternatively loading can be direct into a differential input amplifier or SAWF, in
which case external loads to Vcc will be required. An example load for 44 MHz application with a gain of 16 dB is
contained in Figure 6. The NF and gain with recommended load versus power setting are contained in Figure 20.
The typical IF output impedance as upconverter and downconverter are contained in Figures 21 and 22
respectively.
In all applications care should be taken to achieve symmetric balance to the IF outputs to maximize intermodulation
performance.
The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the section 'Quick Reference
Data'.
PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference
frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance.
The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The
programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits,
and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
4
Zarlink Semiconductor Inc.
SL2101
Data Sheet
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in figure
23. Typical applications for the crystal oscillator are contained in Figure 24 and Figure 25. Figure 25 is used when
driving a second SL2101 as a downconverter.
The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop
filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the
oscillator.
The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to
port P0 by programming the device into test mode. The test modes are described in Figure 26.
The crystal reference frequency can be switched to BUFREF output by bit RE as described in Figure 27. The
BUFREF output is not available on the MLP package.
Programming
The SL2101 is controlled by an I2C data bus and is compatible with both standard and fast mode formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is low, and read mode if it is high. Tables 1 and 2 in Figure 28 illustrate the format of the data. The
device can be programmed to respond to several addresses, which enables the use of more than one device in an
I2C bus system. Figure 28, Table 3 shows how the address is selected by applying a voltage to the 'ADD' input.
When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are received. When the device is programmed into read
mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to
read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
Write Mode
With reference to Figure 28, Table 1, bytes 2 and 3 contain frequency information bits 214 -20 inclusive.
Byte 4 controls the synthesizer reference divider ratio, see Figure 23 and the charge pump setting, see Figure 29.
Byte 5 controls the test modes, see Figure 26, the buffered crystal reference output select RE, see Figure 27, the
power setting, see Figure 7 and the output port P0.
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows
the same procedure, without re-addressing the device. This procedure continues until a STOP condition is
received. The STOP condition can be generated after any data byte, if however it occurs during a byte
transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP
condition.
Read Mode
When the device is in read mode, the status byte read from the device takes the form shown in Figure 28, Table 2.
Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped
below 3V (at 25° C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is
terminated by a STOP command. When POR is set high this indicates that the programmed information may have
been corrupted and the device reset to the power up condition.
Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic
'0' if the device is unlocked.
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
Programmable Features
Synthesizer programmable divider
Function as described above
Reference programmable divider
Function as described above.
Charge pump current
The charge pump current can be programmed by bits C1 & C0 within
data byte 4, as defined in Figure 29.
Power setting
The device power and hence signal handling can be programmed by
bits I2 - I0 within data byte 5, as defined in Figure 7.
In all power settings the synthesizer remains enabled to facilitate rapid
PLL lock reacquisition
Test mode
The test modes are defined by bits T2 - T0 as described in Figure 26.
General purpose ports, P0
The general purpose port can be programmed by bits P0;
Logic '1' = on
Logic '0' = off (high impedance) - this is the default state at device power
on
Buffered crystal reference output, BUFREFThe buffered crystal reference frequency can be switched to the
BUFREF output by bit RE as described in Figure 27. The BUFREF
output defaults to the 'ON' condition at device power up. This output is
only available on the SSOP package.
33 Ω
15
Vcc
OUTPUT
200 Ω
10nH
SL2101
SAWF
10nH
200 Ω
14
33 Ω
OUTPUTB
Figure 4 - Nominal Output Load as Upconverter into Differential SAWF
6
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Vcc
15 pF
820 nH
15
OUTPUT
10 uH
SL2101
10 nF
14
15 pF
820 nH
Figure 5 - Nominal Output Load as Downconverter, 44 MHz IF
10 nF
OUTPUT
15
Vcc
680 nH
SL2101
100 nF
680 nH
14
10 nF
OUTPUTB
Figure 6 - Output Load as Downconverter to a Differential Amplifier
I2
I1
I0
0
0
0
Supply Current in mA
Typ.
Max.
0
90*
120
0
1
67
89
0
1
0
56
75
0
1
1
51
68
1
0
0
82
109
1
0
1
59
78
1
1
0
48
64
1
1
1
43
57
Figure 7 - Supply Current
* default setting on SL2101
7
Zarlink Semiconductor Inc.
SL2101
CH1
S 11
DB1
27 Jul 2001 11:24:54
-99.426
1.6007 pF
1_: 4.3164
1 U FS
Data Sheet
4.7V
1 000.000 000 MHz
PRm
Cor
Avg
16
Smo
2_: 3.7266
-80.117
1.15 GHz
Z0
50
3_: 4.1328
-70.223
1.25 GHz
4_: 4.7617
-58.166
1.4 GHz
1
4
START 1 000.000 000 MHz
2
3
STOP 1 400.000 000 MHz
Figure 8 - Typical RF Input Impedance as Broadband Upconverter (Maximum Power Setting)
100nF
75 Ω
9
RFINPUT
RFIN
10
200 Ω
100nF
RFINPUTB
47nH
SL2101
Figure 9 - RF Input Impedance Matching Network as 50 - 860 MHz Upconverter
8
Zarlink Semiconductor Inc.
SL2101
CH1
S 11
UA6
27 Jul 2001 09:05:31
-46.965
3.3888 pF
1_: 20.07
1 U FS
Data Sheet
4.7V
1 000.000 000 MHz
PRm
Cor
Avg
16
Smo
2_: 19.795
-34.527
1.15 GHz
Z0
75
3_: 20.666
-26.233
1.25 GHz
4_: 25.772
-15.155
1.4 GHz
4
3
1
2
START 1 000.000 000 MHz
STOP 1 400.000 000 MHz
Figure 10 - Typical RF Input Impedance as Narrow Band Downconverter (maximum power
setting)
2.7pF
9
RFIN
RFINPUT
10
200 Ω
10nF
3.9nH
RFINPUTB
SL2101
Figure 11 - RF Input Impedance Matching Network as 1.22 GHz Downconverter
9
Zarlink Semiconductor Inc.
SL2101
Data Sheet
94 dBuV
IIM3 -46dBc
IIM2-47dBc
48 dBuV
47 dBuV
df
f2-f1
f1-df
f1
f2
f2+df
Figure 12 - Two Tone Intermodulation Test Condition Spectrum, Input Referred
8
7
Noise Figure (dB)
6
5
4
3
2
1
0
0
100
200
300
400
500
600
700
800
Input frequency (MHz)
Figure 13 - Input NF, Typical (Maximum Power Setting)
10
Zarlink Semiconductor Inc.
900
SL2101
Data Sheet
11
10
Conversion gain(in dB)
9
8
7
6
Gain
5
4
3
2
1
0
0
100
200
300
400
500
600
700
800
900
Input frequency(in MHz)
Figure 14 - Conversion Gain as Upconverter (Maximum Power Setting)
Gain
(dB)
typ
CSO*
(dBc)
typ
CTB*
(dBc)
typ
IPIP2
(dBµV)
typ
IPIP3
(dBµV)
I2
I1
I0
Typ NF
(dB)
0
0
0
6.8
10.1
-65
-65
144
121
0
0
1
6.0
9.1
-60
-54
141
114
0
1
0
5.8
7.6
-56
-42
132
108
0
1
1
6.5
5.4
-49
-35
129
106
1
0
0
8.7
10.4
-63
-60
146
117
1
0
1
6.2
10.0
-64
-56
142
113
1
1
0
5.9
8.3
-58
-42
133
106
1
1
1
6.4
5.8
-50
-34
126
103
Figure 15 - Upconverter Gain, NF and Intermodulation with Recommended Load Versus Power
Setting
* Measured with 128 channels at +7 dBmV.
BB555
1 kΩ
2 pF
3x0.5 mm
3x1.5 mm
Varactor
line
BB555 3x2.75 mm
(centre)
Figure 16 - Upconverter Oscillator Application
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
-87
-89
-91
PN
-93
-95
0
100
200
300
400
500
600
700
800
900
Figure 17 - Oscillator Typical Phase Noise Performance at 10 kHz Offset
2.5 pF
20
1 kΩ
4.3 nH
21
Varactor
line
BB555
Figure 18 - Downconverter Oscillator Application
100
98
96
Phase noise (at 10 kHz offset)
Phase noi se(in dBc/Hz)
-85
94
92
90
88
86
84
82
80
1040
1060
1080
1100
1120
1140
1160
1180
1200
2201
LO frequency
Figure 19 - Typical Phase Noise Performance as Downconverter at 10 kHz Offset
12
Zarlink Semiconductor Inc.
SL2101
Data Sheet
I2
I1
I0
Typ NF
(dB)
Gain (dB)
typ IPIP3
(dBµV)
0
0
0
10.3
15.6
124
0
0
1
9.3
15.1
119
0
1
0
8.8
14.0
112
0
1
1
8.7
12.1
106
1
0
0
11.6
15.4
121.3
1
0
1
9.0
15.1
119.7
1
1
0
8.3
13.9
112.6
1
1
1
8.0
11.9
106.3
Figure 20 - Downconverter Gain, NF and IP3 with Recommended (Fig. 4) Load Versus Power
Setting
CH1
S 11
1 U FS
DB1
27 Jul 2001 11:24:54
-99.426
1.6007 pF
1_: 4.3164
1 000.000 000 MHz
4.7V
PRm
Cor
Avg
16
Smo
2_: 3.7266
-80.117
1.15 GHz
Z0
50
3_: 4.1328
-70.223
1.25 GHz
4_: 4.7617
-58.166
1.4 GHz
1
4
START 1 000.000 000 MHz
2
3
STOP 1 400.000 000 MHz
Figure 21 - Typical IF Output Impedance as Upconverter, Single-Ended
13
Zarlink Semiconductor Inc.
SL2101
CH1
S 11
UA6
27 Jul 2001 09:48:39
-1.1071 k
7.1882 pF
1_: 1.3588 k
1 U FS
Data Sheet
20.000 000 MHz
4.7V
PRm
Cor
Avg
16
Smo
2_: 606.87
-695.97
40 MHz
Z0
50
3_: 305.72
-549.5
70 MHz
4_: 213.55
-449.58
100 MHz
1
2
3
4
START 10.000 000 MHz
STOP 100.000 000 MHz
Figure 22 - Typical IF Output Impedance as Downconverter, Single-Ended
R4
R3
R2
R1
R0
Ratio
0
0
0
0
0
2
0
0
0
0
1
4
0
0
0
1
0
8
0
0
0
1
1
16
0
0
1
0
0
32
0
0
1
0
1
64
0
0
1
1
0
128
0
0
1
1
1
256
0
1
0
0
0
Illegal state
0
1
0
0
1
5
0
1
0
1
0
10
0
1
0
1
1
20
0
1
1
0
0
40
0
1
1
0
1
80
0
1
1
1
0
160
0
1
1
1
1
320
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
R4
R3
R2
R1
R0
Ratio
1
0
0
0
0
Illegal state
1
0
0
0
1
6
1
0
0
1
0
12
1
0
0
1
1
24
1
0
1
0
0
48
1
0
1
0
1
96
1
0
1
1
0
192
1
0
1
1
1
384
1
1
0
0
0
Illegal state
1
1
0
0
1
7
1
1
0
1
0
14
1
1
0
1
1
28
1
1
1
0
0
56
1
1
1
0
1
112
1
1
1
1
0
224
1
1
1
1
1
448
Figure 23 - Reference Division Ratios
1
XTALCAP
47pf
2
47pf
XTAL
4MHz
Figure 24 - Standard Application
15
Zarlink Semiconductor Inc.
SL2101
Data Sheet
1
XTALCAP
SL2101
DOWNCONVE RTER
47pF
2
47pF
XTAL
1
4MHz
XTALCAP
820nH
10k
10pF
SL2101
2 UPCONVE RTER
XTAL
Figure 25 - Application When Driving Two SL2101 from One Crystal
T2
T1
T0
Test Mode Description
0
0
0
Normal operation
0
0
1
Charge pump sink *
Status byte FL set to logic ‘0’
0
1
0
Charge pump source *
Status byte FL set to logic ‘0’
0
1
1
Charge pump disabled *
Status byte FL set to logic ‘1’
1
0
0
Normal operation and Port P0 = Fpd/2
1
0
1
Charge pump sink *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
1
1
0
Charge pump source *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
1
1
1
Charge pump disabled *
Status byte FL set to logic ‘1’
Port P0 = Fcomp
Figure 26 - Test Modes
* clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle
status byte bit FL.
RE
BUFREF output
0
disabled, high impedance
1
enabled
Note:The BUFREF output is only available on the SSOP package
Figure 27 - Buffered Crystal Reference Output Select
16
Zarlink Semiconductor Inc.
SL2101
Data Sheet
MSB
LSB
Address
1
1
0
0
0
MA1
MA0
0
A
Byte 1
Programmable
divider
0
214
213
212
211
210
29
28
A
Byte 2
Programmable
divider
27
26
25
24
23
22
21
20
A
Byte 3
Control data
1
C1
C0
R4
R3
R2
R1
R0
A
Byte 4
Control data
T2
T1
T0
I2
I1
I0
RE
P0
A
Byte 5
Table 1 - Write Data Format (MSB is transmitted first)
MSB
Address
Programmable
divider
LSB
1
1
0
0
0
MA1
MA0
1
A
Byte 1
POR
FL
0
0
0
0
0
0
A
Byte 2
Table 2 - Read Data Format (MSB is transmitted first)
A
MA1,MA0
:
:
Acknowledge bit
Variable address bits (see Table 3)
214-20
I2-I0
C1-C0
R4-R0
T2-T0
RE
P0
POR
FL
:
:
:
:
:
:
:
:
:
Programmable division ratio control bits
lna/mixer power select (see Figure 7)
Charge pump current select (see Figure 29)
Reference division ratio select (see Figure 23)
Test mode control bits (see Figure 26)
Buffered crystal reference output enable (see Figure 27
P0 port output state
Power on reset indicator
Phase lock flag
MA1
MA0
Address input voltage level
0
0
0-0.1Vcc
0
1
Open circuit
1
0
0.4Vcc – 0.6 Vcc #
1
1
0.9 Vcc - Vcc
Table 3 - Address Selection
Figure 28 - Read/Write Data Formats
17
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Current in mA
C1
C0
Min.
Typ.
Max.
0
0
+-98
+-130
+-162
0
1
+-210
+-280
+-350
1
0
+-450
+-600
+-750
1
1
+-975
+-1300
+-1625
Figure 29 - Charge Pump Current
Electrical Characteristics - Test conditions (unless otherwise stated). Tamb = -40o to 85oC, Vee= 0V, Vcc=5 V+-5%. These
characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage at
maximum power setting unless otherwise stated.
Characteristic
Pin
Min.
Typ.
Max.
Units
Conditions
90
120
mA
IF outputs will be connected to
Vcc through the differential load
as in Figures 4, 5 & 6.
See Figure 7 for programmable
settings.
Supply current
6,
12,17,
19, 22
Input frequency range
9, 10
50
1400
MHz
Operating condition only.
Output frequency range
14, 15
30
1400
MHz
Operating condition only.
Composite peak input
signal
9, 10
dBµV
Operating condition only.
All synthesizer related
spurs on IF Output
14, 15
97
-60
dBc
860
MHz
Within channel bandwidth of
8 MHz and with input power of
60 dBµV.
Upconverter
application
Input frequency range
9, 10
50
Input impedance
Input return loss
75
6
Input Noise Figure
Conversion gain
9.5
9
18
Zarlink Semiconductor Inc.
Ω
See Figure 8.
dB
With input matching network as in
Figure 9.
dB
Tamb=27°C, see Figure 13, with
input matching network as in
Figure 9.
See Figure 15 for programmable
settings.
dB
Differential voltage gain to 200 Ω
load on output of SAWF as in
Figure 4, see Figure 14.
See Figure 15 for programmable
settings.
SL2101
Characteristic
Pin
Max.
Units
+1
dB
50-860 MHz
Gain variation within
channel
0.5
dB
Channel bandwidth 8 MHz within
operating frequency range.
Through gain
-20
dB
45-1400 MHz
Gain variation across
operation range
Min.
Typ.
Data Sheet
-1
Conditions
CSO
-65
dBc
Measured with 128 channels at 62
dBµV. See Figure 15 for
programmable settings.
CTB
-68
dBc
Measured with 128 channels at 62
dBµV. See Figure 15 for
programmable settings.
IPIP22T
141
dBuV
See Note 2.
See Figure 15 for programmable
settings.
IPIP32T
117
dBuV
See Note 2.
See Figure 15 for programmable
settings.
IPIM22T
-47
dBc
See Note 2. See Figure 12.
IPIM32T
-46
dBc
See Note 2. See Figure 12.
2.3
GHz
Maximum tuning range 0.9 GHz
determined by application.
LO operating range
1
LO phase noise, SSB
@ 10 kHz offset
@ 100 kHz offset
-86
-106
dBc/Hz
dBc/Hz
LO phase noise floor
IF output frequency
range
14, 15
1
-136
dBc/Hz
1.4
GHz
IF output impedance
Application as in Figure 16. See
Figure 17.
Application as in Figure 16.
See Figure 21.
Downconverter
application
Input frequency range
9, 10
1000
Input impedance
Input return loss
1400
75
12
Input Noise Figure
14
19
Zarlink Semiconductor Inc.
MHz
Ω
See Figure 10.
dB
With input matching network as in
Figure 11.
dB
Tamb=27°C, with input matching
network as in Figure 11. See
Figure 20 for programmable
settings.
SL2101
Characteristic
Pin
Min.
Conversion gain
Typ.
Max.
12
Data Sheet
Units
Conditions
dB
Differential voltage gain to 50 Ω
load on output of impedance
transformer as in Figure 6. See
Figure 20 for programmable
settings.
Gain variation within
channel
0.5
dB
Channel bandwidth 8 MHz within
operating frequency range.
Through gain
-20
dB
45-1400 MHz
IPIP32T
dBµV
117
IPIM32T
LO operating range
1
LO phase noise, SSB
@ 10 kHz offset
@ 100 kHz offset
IF output frequency
range
-46
dBc
See Note 2. See Figure 12.
2.3
GHz
Maximum tuning range
determined by application, see
Note 4.
-92
-112
dBc/Hz
dBc/Hz
LO phase noise floor
14, 15
See Note 2.
-136
dBc/Hz
100
MHz
IF output impedance
Application as in Figure 18. See
Figure 19.
Application as in Figure 18.
See Figure 22.
Synthesizer
SDA, SCL
3, 4
I2C ‘Fast mode’ compliant
Input high voltage
3
5.5
V
Input low voltage
0
1.5
V
10
µA
Input voltage = Vcc
µA
Input voltage = Vee
10
µA
Vcc=Vee
Isink = 3 mA
Isink = 6 mA
Input high current
Input low current
-10
Leakage current
Hysterysis
0.4
SDA output voltage
3
0.4
0.6
V
V
SCL clock rate
4
400
kHz
Charge pump output
current
28
Charge pump output
leakage
28
See Figure 29.
Vpin = 2 V
+-3
+-10
20
Zarlink Semiconductor Inc.
nA
Vpin = 2 V
SL2101
Characteristic
Pin
Min.
Charge pump drive
output current
27
0.5
Crystal frequency
1,2
2
Recommended crystal
series resistance
Typ.
Max.
Data Sheet
Units
Conditions
mA
Vpin = 0.7 V
20
MHz
See Figure24 and Figure 25 for
application.
10
200
Ω
4 MHz parallel resonant crystal
External reference input
frequency
2
2
20
MHz
Sinewave coupled through 10 nF
blocking capacitor
External reference drive
level
2
0.2
0.5
Vpp
Compatible with BUFREF output.
(SSOP package only)
4
MHz
Phase detector
comparison frequency
Equivalent phase noise
at phase detector
SSB, within loop bandwidth
Local oscillator
programmable divider
division ratio
-148
dBc/Hz
Fcomp = 1 MHz
-152
dBc/Hz
Fcomp = 250 kHz
-158
dBc/Hz
Fcomp = 62.5 kHz
240
32767
Reference division ratio
See Figure 23.
Output port
sink current
leakage current
26
BUFREF output
output amplitude
5
2
10
output impedance
0.35
Vpp
250
Ω
Address select
Input high current
Input low current
Note 1:
mA
µA
1
-0.5
mA
mA
See Note 3.
Vport = 0.7 V
Vport =Vcc
AC coupled. Note 5.
Enabled by bit RE=1 and default
state on power-up. BUFREF
output only available on SSOP
package
See Figure 28, Table 3
Vin=Vcc
Vin=Vee
All power levels are referred to 75 Ω and 0 dBm = 109 dB µV
Note 2:
Any two tones within RF operating range at 94 dBµV beating within band, with output load as in Figure 4
Note 3:
Port powers up in high impedance state
Note 4:
To maximise phase noise the tuning range should be minimised and Q of resonator maximised. The application as in Figure
18 has a tuning range of 200 MHz.
Note 5:
If the BUFREF output is not used it should be left open circuit or connected to Vccd and disabled by setting RE = '0'.
21
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Absolute Maximum Ratings - All voltages are referred to Vee at 0 V (pins 7, 8, 11, 13, 16, 18, 23, 25).
Characteristic
Pin
Min.
Max.
Units
6, 12,
17, 19,
22
-0.3
6
V
117
dBuV
-0.3
Vcc+0.3
V
-0.3
6
V
-55
150
°C
Junction temperature
125
°C
Package thermal resistance, chip
to case (SSOP)
20
°
Package thermal resistance, chip
to ambient (SSOP)
85
°C/W
Power consumption at 5.25 V
630
mW
Maximum power setting.
Mil-std 883B method 3015
cat1
Supply voltage, Vcc
RF input voltage
9, 10
All I/O port DC offsets
SDA, SCL DC offsets
Storage temperature
3, 4
1
kV
ESD protections (pins 1, 2)
0.75
kV
Zarlink Semiconductor Inc.
Differential, AC coupled
inputs
Vcc = Vee to 5.25 V
Power applied.
C/W
ESD protection (pins 3-28)
22
Conditions
SL2101
RF inputs
Data Sheet
Oscillator inputs
IF outputs
Figure 30 - Input and Output Interface Circuits (RF section)
23
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Vccd
1
200µA
Reference oscillator
Loop amplifier
Vccd
120K
*
* On SDA only
SDA/SCL (pins 3 and 4)
ADD input
Vccd
P0
1mA
Output port
BUFREF output
Figure 31 - Input and Output Interface Circuits (PLL section)
24
Zarlink Semiconductor Inc.
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