TECHNICAL DATA IN472-3 Liquid Crystal Display Controller The IN472-3-3 Liquid Crystal Display (LDC) Controller is a perpheral member of the COPSTM family, fabricated using CMOS technology. The IN472-3 drives a multiplexed liquid crystal directly. Data is loaded serially and is held in internal latches. The In472-3 contains an on-chip oscillator and generates all the multi-level waveforms for back-planes and segment outputs on a triplex display. One IN472-3 can drive 36 segments multiplexed as 3 x 12 (41/2 digit display). Two IN472-3 devices can be used together to drive 72 segments (3 x 24) which could be an 81/2 digit display. • • • • • • • • • • • Direct interface to TRIPLEX LCD Low power dissipation (100 µW typ.) Low cost Compatible with all COP400 processors Needs no refresh from processor On-chip oscillator and latches Expandable to longer displays Software compatible with COP470 V.F.Display Driver Chip Operates from display voltage MICROWIRETM compatible serial I/O 20-pin Dual-In-Line package ORDERING INFORMATION IN472-3N Plastic IN472-3DW SOIC TA = 0° to 70° C for all packages PIN ASSIGNMENT Pin Description Pin Description CS Chip select VDD Power supply (display voltage) GND Ground DI Serial data input SK Serial clock input BPA Display backplane A (or oscillator in) BPB Display backplane B BPC Display backplane C (or oscillator out) SA1∼SA4 12 multiplexed outputs 1 IN472-3 DC ELECTRICAL CHARACTERISTICS (GND=0 V, VDD=3.0 V to 5.5 V, TA= 0°C to 70°C (depends on display characteristics) Guaranteed Limit Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current (Note 1) VIL Input Levels DI, SK, CS Test Conditions µA 0.8 V VDD 0.6 VDD-0.4 VDD VDD -∆V VDD 1/3VDD -∆V 1/3VDD +∆V V V BP + Time V Backplane Outputs (BPA,BPB,BPC) 0 ∆V 2/3VDD -∆V 2/3VDD +∆V 0 ∆V 2/3VDD -∆V 2/3VDD +∆V VDD -∆V VDD 1/3VDD -∆V 1/3VDD +∆V Internal Oscillator Frequency 15 80 kHz Frame Time (Int. Osc. ÷ 192) 2.4 12.8 ms Scan Frequency 39 208 Hz SK Clock Frequency 4 250 kHz During BP - Time Segment Outputs (SA1 ∼ SA4) During BP + Time Segment Outputs (SA1 ∼ SA4) During BP - Time V V SK Width 1.7 µs tSETUP DI Data Stup 1.0 µs tHOLD DI Data Hold 100 ns tSETUP CS 1.0 µs tHOLD 1.0 Output Loading Capacitance 100 Note 1: Power supply current as measured in stand-alone mode with all outputs open and all inputs at VDD. Note 2: ∆V - 0.05VDD. 2 V VDD 0.4 During VSEG OFF 1/TSCAN 250 Backplane Outputs (BPA,BPB,BPC) VSEG OFF VSEG ON V Output Levels, BPC (as Osc. Out) VBPA,BPB,BPC OFF VSEG ON 5.5 VDD-0.6 VBPA,BPB,BPC OFF VBPA,BPB,BPC ON 3.0 BPA (as Osc. in) VOH VBPA,BPB,BPC ON Unit 0.7 VDD VIH VOL Max VDD =5.5 V VIH VIL Min pF IN472-3 Figure 1. Serial Load Timing Diagram Figure 2. Backplane and Segment Waveforms 3