TECHNICAL DATA Liquid Crystal Display Controller KK472 The KK472 Liquid Crystal Display (LDC) Controller is a perpheral member of the COPSTM family, fabricated using CMOS technology. The KK472 drives a multiplexed liquid crystal directly. Data is loaded serially and is held in internal latches. The KK472 contains an on-chip oscillator and generates all the multi-level waveforms for back-planes and segment outputs on a triplex display. One KK472 can drive 36 segments multiplexed as 3 x 12 (41/2 digit display). Two KK472 devices can be used together to drive 72 segments (3 x 24) which could be an 81/2 digit display. • • • • • • • • • • • Direct interface to TRIPLEX LCD Low power dissipation (100 µW typ.) Low cost Compatible with all COP400 processors Needs no refresh from processor On-chip oscillator and latches Expandable to longer displays Software compatible with COP470 V.F.Display Driver Chip Operates from display voltage MICROWIRETM compatible serial I/O 20-pin Dual-In-Line package ORDERING INFORMATION KK472N Plastic KK472DW SOIC TA = 0° to 70° C for all packages PIN ASSIGNMENT Pin Description Pin Description CS Chip select VDD Power supply (display voltage) GND Ground DI Serial data input SK Serial clock input BPA Display backplane A (or oscillator in) BPB Display backplane B BPC Display backplane C (or oscillator out) SA1∼SA4 12 multiplexed outputs 1 KK472 DC ELECTRICAL CHARACTERISTICS (GND=0 V, VDD=3.0 V to 5.5 V, TA= 0°C to 70°C (depends on display characteristics) Guaranteed Limit Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current (Note 1) VIL Input Levels DI, SK, CS Test Conditions µA 0.8 V VDD 0.6 V VDD 0.4 V VDD VDD -∆V VDD 1/3VDD -∆V 1/3VDD +∆V 0 ∆V 2/3VDD -∆V 2/3VDD +∆V 0 ∆V 2/3VDD -∆V 2/3VDD +∆V VDD -∆V VDD 1/3VDD -∆V 1/3VDD +∆V Internal Oscillator Frequency 15 80 kHz Frame Time (Int. Osc. ÷ 192) 2.4 12.8 ms Scan Frequency 39 208 Hz SK Clock Frequency 4 250 kHz Backplane Outputs (BPA,BPB,BPC) V During BP + Time Backplane Outputs (BPA,BPB,BPC) V During BP - Time Segment Outputs (SA1 ∼ SA4) During BP + Time Segment Outputs (SA1 ∼ SA4) VSEG OFF 1/TSCAN 250 VDD-0.4 VSEG OFF VSEG ON V Output Levels, BPC (as Osc. Out) VBPA,BPB,BPC OFF VSEG ON 5.5 VDD-0.6 VBPA,BPB,BPC OFF VBPA,BPB,BPC ON 3.0 BPA (as Osc. in) VOH VBPA,BPB,BPC ON Uni t 0.7 VDD VIH VOL Max VDD =5.5 V VIH VIL Min During BP - Time V V SK Width 1.7 µs tSETUP DI Data Stup 1.0 µs tHOLD DI Data Hold 100 ns tSETUP CS 1.0 µs tHOLD 1.0 Output Loading Capacitance 100 pF Note 1: Power supply current as measured in stand-alone mode with all outputs open and all inputs at VDD. Note 2: ∆V - 0.05VDD. 2 KK472 Figure 1. Serial Load Timing Diagram Figure 2. Backplane and Segment Waveforms 3 KK472 N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 11 20 B 1 10 Symbol MIN MAX A 24.89 26.92 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 N G K M J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 013AC) A 20 11 H Dimension, mm B 1 P 10 G R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. F M Symbol MIN MAX A 12.6 13 B 7.4 7.6 C 2.35 2.65 D 0.33 0.51 F 0.4 1.27 G 1.27 H 9.53 J 0° 8° K 0.1 0.3 M 0.23 0.32 P 10 10.65 R 0.25 0.75 4