TI SN74AUC74

SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
D
1D
1CLK
1PRE
1Q
1Q
VCC
1
14
2
13 2CLR
3
12 2D
4
11 2CLK
5
10 2PRE
9 2Q
6
7
8
2Q
D
D
D
D
D
1CLR
D
RGY PACKAGE
(TOP VIEW)
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 1.8 ns at 1.8-V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
GND
D
description/ordering information
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically
for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop
for higher frequencies, the CLR input overrides the PRE input when they are both low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
–40°C to 85°C QFN – RGY
Tape and reel
SN74AUC74RGYR
MS74
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
X
L
X
X
L
H
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-5.
2
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SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
MIN
MAX
0.8
2.7
UNIT
V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
V
1.7
0
0.35 × VCC
VIL
Low-level input voltage
VI
VO
Input voltage
0
3.6
V
Output voltage
0
VCC
–0.7
V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
VCC = 0.8 V
VCC = 1.1 V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
V
–3
VCC = 1.4 V
VCC = 1.65 V
–5
VCC = 2.3 V
VCC = 0.8 V
–9
mA
–8
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
mA
5
9
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
MIN
0.8 V
MAX
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
ICC
D inputs
VI = VCC or GND,
VI = VCC or GND
Control inputs
VI = VCC or GND
IO = 0
UNIT
0.55
1.1 V
0.8 V
TYP†
VCC–0.1
IOH = –3 mA
IOH = –5 mA
II
Ioff
Ci
VCC
0.8 V to 2.7 V
V
0 to 2.7 V
±5
µA
0
±10
µA
0.8 V to 2.7 V
10
µA
2.5 V
2
2.5 V
2.5
pF
† All typical values are at TA = 25°C.
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3
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V
TYP
fclock
Clock frequency
tw
Pulse
duration
Setup time
before CLK↑
tsu
th
MIN
100
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
225
MIN
250
VCC = 2.5 V
± 0.2 V
MAX
MIN
300
350
CLK high or low
4.6
1.3
0.6
0.5
0.5
CLR low
6.6
2
1.5
1.5
1.5
PRE low
4.8
1.8
1.5
1.5
1.5
Data
2.3
1
0.6
0.6
0.7
CLR inactive
0
0
0
0
0.3
PRE inactive
0
0
0
0.2
0.3
2.1
0.3
0.3
0.3
0.3
Hold time, data after CLK↑
UNIT
MAX
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 0.8 V
TO
(OUTPUT)
VCC = 1.5 V
± 0.1 V
100
225
CLK
9.5
1.3
4
0.7
2.5
0.5
1.2
2.1
0.5
1.4
CLR
10.5
1.5
4.1
1.1
2.9
0.9
1.4
2.4
0.7
1.6
12
1.6
4.7
1.1
2.8
0.9
1.4
2.4
0.7
1.6
PRE
MIN
MAX
MIN
250
TYP
VCC = 2.5 V
± 0.2 V
MIN
Q or Q
MAX
VCC = 1.8 V
± 0.15 V
TYP
fmax
tpd
VCC = 1.2 V
± 0.1 V
MAX
300
MIN
UNIT
MAX
350
MHz
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
TYP
MAX
1.2
1.9
2.8
1
2.2
1.3
2.1
3
1.1
2.4
1.3
2.1
3.1
1.1
2.5
300
CLK
tpd
VCC = 2.5 V
± 0.2 V
CLR
Q or Q
PRE
MIN
UNIT
MAX
350
MHz
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
36
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VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
36
• DALLAS, TEXAS 75265
36
VCC = 1.8 V
TYP
37
VCC = 2.5 V
TYP
41
UNIT
pF
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
VCC/2
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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