bq24314C www.ti.com SLUSAV3 – AUGUST 2012 OVERVOLTAGE AND OVERCURRENT PROTECTION IC AND Li+ CHARGER FRONT-END PROTECTION IC Check for Samples: bq24314C FEATURES • 1 • 23 • • • • • • Provides Protection for Three Variables: – Input Overvoltage, with Rapid Response in < 1 μs – User-Programmable Overcurrent with Current Limiting – Battery Overvoltage 30V Maximum Input Voltage Supports up to 1.5A Input Current Robust Against False Triggering Due to Current Transients Thermal Shutdown Enable Input Status Indication – Fault Condition Available in Space-Saving Small 8 Lead 2×2 SON APPLICATIONS • • • • • Mobile Phones and Smart Phones PDAs MP3 Players Low-Power Handheld Devices Bluetooth™ Headsets DESCRIPTION The bq24314C is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the charging circuit. The IC continuously monitors the input voltage, the input current, and the battery voltage. In case of an input overvoltage condition, the IC immediately removes power from the charging circuit by turning off an internal switch. In the case of an overcurrent condition, it limits the system current at the threshold value, and if the overcurrent persists, switches the pass element OFF after a blanking period. Additionally, the IC also monitors its own die temperature and switches off if it exceeds 140°C. The input overcurrent threshold is userprogrammable. The IC can be controlled by a processor and also provides status information about fault conditions to the host. APPLICATION SCHEMATIC AC Adapter VDC 1 IN OUT 8 1 mF 1 mF GND bq24080 Charger IC bq24314C SYSTEM VBAT 6 VSS ILIM FAULT 4 2 7 CE 5 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Bluetooth is a trademark of Bluetooth SIG, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated bq24314C SLUSAV3 – AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) DEVICE (2) OVP THRESHOLD PACKAGE MARKING 5.85 V 2mm x 2mm SON SDL bq24314CDSG (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. To order a 3000 pcs reel add R to the part number, or to order a 250 pcs reel add T to the part number. PACKAGE DISSIPATION RATINGS PART NO. PACKAGE RθJC RθJA bq24314CDSG 2×2 SON 5°C/W 75°C/W ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER VI PIN Input voltage VALUE IN (with respect to VSS) –0.3 to 30 OUT (with respect to VSS) –0.3 to 12 ILIM, FAULT, CE, VBAT (with respect to VSS) –0.3 to 7 UNIT V II Input current IN 2 A IO Output current OUT 2 A Output sink current FAULT ESD Withstand Voltage 15 mA All (Human Body Model per JESD22-A114-E) 2000 V All (Machine Model per JESD22-A115-E) 200 V All (Charge Device Model per JESD22-C101-C) 500 V IN(IEC 61000-4-2) (with IN bypassed to the VSS with a 1-μF low-ESR ceramic capacitor) 15 (Air Discharge) 8 (Contact) kV TJ Junction temperature –40 to 150 °C Tstg Storage temperature –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. THERMAL INFORMATION THERMAL METRIC (1) bq24314C DSG (8 PINS) θJA Junction-to-ambient thermal resistance 58.6 θJCtop Junction-to-case (top) thermal resistance 67.9 θJB Junction-to-board thermal resistance 29.7 ψJT Junction-to-top characterization parameter 1.2 ψJB Junction-to-board characterization parameter 30.3 θJCbot Junction-to-case (bottom) thermal resistance 7.6 (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C bq24314C www.ti.com SLUSAV3 – AUGUST 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN 3 MAX UNIT VIN Input voltage range 30 V IIN Input current, IN pin 1.5 A IOUT Output current, OUT pin 1.5 A RILIM OCP Programming resistor 15 90 kΩ TJ Junction temperature –40 125 °C Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C 3 bq24314C SLUSAV3 – AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS over junction temperature range –40°C to 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IN UVLO Undervoltage lock-out, input power detected threshold CE = Low, VIN increasing from 0V to 3V 2.6 2.7 2.8 V Vhys(UVLO) Hysteresis on UVLO CE = Low, VIN decreasing from 3V to 0V 200 260 300 mV TDGL(PGOOD) Deglitch time, input power detected status CE = Low. Time measured from VIN 0V → 5V 1μs rise-time, to output turning ON IDD Operating current CE = Low, No load on OUT pin, VIN = 5V, RILIM = 25kΩ ISTDBY Standby current CE = High, VIN = 5.0V 8 ms 400 600 μA 65 95 μA 170 280 mV 5.85 6.00 INPUT TO OUTPUT CHARACTERISTICS VDO Drop-out voltage IN to OUT CE = Low, VIN = 5V, IOUT = 1A INPUT OVERVOLTAGE PROTECTION VOVP Input overvoltage protection threshold CE = Low, VIN increasing from 5V to 7.5V tPD(OVP) Input OV propagation delay (1) CE = Low Vhys(OVP) Hysteresis on OVP CE = Low, VIN decreasing from 7.5V to 5V tON(OVP) Recovery time from input overvoltage condition CE = Low, Time measured from VIN 7.5V → 5V, 1μs fall-time 5.71 200 20 60 V ns 110 8 mV ms INPUT OVERCURRENT PROTECTION IOCP Input overcurrent protection threshold range IOCP Input overcurrent protection threshold KILIM Programmable current limit factor tBLANK(OCP) Blanking time, input overcurrent detected tREC(OCP) Recovery time from input overcurrent condition 300 CE = Low, RILIM = 24.9kΩ, 3 V ≤ VIN < VOVP -Vhys(OVP) 900 1000 1500 mA 1100 mA 25 AΩ 176 μs 64 ms BATTERY OVERVOLTAGE PROTECTION BVOVP Battery overvoltage protection threshold CE = Low, VIN > 4.4V 4.40 4.45 4.5 V Vhys(Bovp) Hysteresis on BVOVP CE = Low, VIN > 4.4V 200 280 350 mV IVBAT Input bias current on VBAT pin VBAT = 4.4V, TJ = 25°C 10 nA TDGL(Bovp) Deglitch time, battery overvoltage detected CE = Low, VIN > 4.4V. Time measured from VVBAT rising from 4.1V to 4.4V to FAULT going low. μs 176 THERMAL PROTECTION TJ(OFF) Thermal shutdown temperature TJ(OFF-HYS) Thermal shutdown hysteresis 140 150 20 °C °C LOGIC LEVELS ON CE VIL Low-level input voltage 0 0.4 V VIH High-level input voltage IIL Low-level input current VCE = 0V 1 μA IIH High-level input current VCE = 1.8V 15 μA 1.4 V LOGIC LEVELS ON FAULT VOL Output low voltage ISINK = 5mA 0.2 V IHI-Z Leakage current, FAULT pin HI-Z VFAULT = 5V 10 μA (1) 4 Not tested in production. Specified by design. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C bq24314C www.ti.com SLUSAV3 – AUGUST 2012 Q1 IN Charge Pump, Bandgap, Bias Gen OUT VBG ISNS ILIM ILIMREF Current limiting loop OFF OCP comparator ILIMREF - Δ t BLANK(OCP) ISNS FAULT VIN VBG COUNTERS, CONTROL, AND STATUS OVP VIN CE VBG t DGL(PGOOD) UVLO VBAT THERMAL SHUTDOW VBG t DGL(BOVP) VSS Figure 1. Simplified Block Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C 5 bq24314C SLUSAV3 – AUGUST 2012 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME DSG I/O DESCRIPTION IN 1 I Input power, connect to external DC supply. Connect external 1μF ceramic capacitor (minimum) to VSS. OUT 8 O Output terminal to the charging system. Connect external 1μF ceramic capacitor (minimum) to VSS. VBAT 6 I Battery voltage sense input. Connect to pack positive terminal through a resistor. ILIM 7 I/O CE 5 I Chip enable input. Active low. When CE = High, the input FET is off. Internally pulled down. FAULT 4 O Open-drain output, device status. FAULT = Low indicates that the input FET Q1 has been turned off due to input overvoltage, input overcurrent, battery overvoltage, or thermal shutdown. VSS 2 – Ground terminal NC 3 Thermal PAD Input overcurrent threshold programming. Connect a resistor to VSS to set the overcurrent threshold. These pins may have internal circuits used for test purposes. Do not make any external connections at these pins for normal operation. – There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. The VSS pin must be connected to ground at all times. DSG Package (Top View) IN 1 8 OUT 7 ILIM NC 3 6 VBAT FAULT 4 5 CE VSS 2 bq24314C 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C bq24314C www.ti.com SLUSAV3 – AUGUST 2012 TYPICAL OPERATING PERFORMANCE Test conditions (unless otherwise noted) for typical operating performance: VIN = 5 V, CIN = 1 μF, COUT = 1 μF, RILIM = 25 kΩ, RBAT = 100 kΩ, TA = 25°C, VPU = 3.3V (see Figure 20 for the Typical Application Circuit) VIN VIN VOUT VOUT IOUT FAULT Figure 2. Normal Power-On Showing Soft-Start, ROUT = 6.6Ω Figure 3. OVP at Power-On, VIN = 0V to 9V, tr = 50μs VIN VIN Max VOUT = 5.92 V Max VOUT = 5.84 V VOUT VOUT FAULT FAULT Figure 4. OVP Response for Input Step, VIN = 5V to 12V, tr = 1μs Figure 5. OVP Response for Input Step, VIN = 5V to 12V, tr = 20μs Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C 7 bq24314C SLUSAV3 – AUGUST 2012 www.ti.com TYPICAL OPERATING PERFORMANCE (continued) VIN VIN VOUT IOUT IOUT VOUT FAULT FAULT Figure 6. Recovery from OVP, VIN = 7.5V to 5V, tf = 400μs Figure 7. OCP, Powering Up into a Short Circuit on OUT Pin, OCP Counter Counts to 15 Before Switching OFF the Device VIN VIN VOUT IOUT IOUT VOUT FAULT FAULT Figure 8. OCP, Zoom-in on the First Cycle of Figure 7 Figure 9. OCP, ROUT Switches from 6.6Ω to 3.3Ω, Shows Current Limiting and Soft-Stop VOUT VVBAT Begin soft-stop VOUT VVBAT tDGL(BAT-OVP) = 220 ms FAULT FAULT Figure 10. BAT-OVP, VVBAT Steps from 4.2V to 4.4V, Shows tDGL(BAT-OVP) and Soft-Stop 8 Figure 11. BAT-OVP, VVBAT Cycles Between 4.1V and 4.4V, Shows BAT-OVP Counter Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C bq24314C www.ti.com SLUSAV3 – AUGUST 2012 TYPICAL OPERATING PERFORMANCE (continued) UNDERVOLTAGE LOCKOUT vs FREE-AIR TEMPERATURE DROPOUT VOLTAGE (IN to OUT) vs FREE-AIR TEMPERATURE 280 2.75 260 2.7 VIN Increasing 240 VIN = 4 V 220 VDO @ 1A - mV VUVLO, VHYS-UVLO - V 2.65 2.6 2.55 200 VIN = 5 V 180 160 2.5 140 VIN Decreasing 2.45 2.4 -50 120 100 -30 -10 10 30 50 70 Temperature - °C 90 110 0 130 50 100 150 Temperature - °C Figure 12. Figure 13. OVERVOLTAGE THRESHOLD PROTECTION vs FREE-AIR TEMPERATURE INPUT OVERCURRENT PROTECTION vs ILIM RESISTANCE 5.88 1600 1400 5.86 5.84 1000 VIN Increasing IOCP - mA VOVP, VHYS-OVP - V 1200 5.82 800 600 400 5.8 VIN Decreasing 5.78 -50 -30 -10 10 30 50 70 90 200 110 130 0 0 Temperature - °C Figure 14. 10 20 30 40 50 60 RILIM - kW 70 80 90 100 Figure 15. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C 9 bq24314C SLUSAV3 – AUGUST 2012 www.ti.com TYPICAL OPERATING PERFORMANCE (continued) INPUT OVERCURRENT PROTECTION vs FREE-AIR TEMPERATURE BATTERY OVERVOLTAGE PROTECTION vs FREE-AIR TEMPERATURE 4.5 985 984 4.45 BVOVP (VBAT Increasing) 983 4.4 981 BVOVP - V IOCP - mA 982 980 4.35 4.3 979 4.25 978 977 BVOVP Recovery (VBAT Decreasing) 4.2 976 975 -50 -30 -10 10 30 50 70 Temperature - °C 90 110 4.15 -50 130 -30 -10 10 30 50 70 90 110 130 Temperature - °C Figure 16. Figure 17. LEAKAGE CURRENT (VBAT Pin) vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs INPUT VOLTAGE 2.5 900 800 2 IDD, ISTDBY - mA 1.5 IVBAT - nA IDD (CE = Low) 700 1 600 500 400 300 200 0.5 ISTDBY (CE = High) 100 0 -50 -30 -10 10 30 50 70 Temperature - °C 90 110 130 0 0 10 15 20 25 30 35 VIN - V Figure 18. 10 5 Figure 19. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C bq24314C www.ti.com SLUSAV3 – AUGUST 2012 TYPICAL APPLICATION CIRCUIT VOVP = 6.8V, IOCP = 1000mA, BVOVP = 4.45V (Terminal numbers shown are for the 2×2 DSG package) AC Adapter VDC 1 IN OUT 8 CIN GND COUT 1 mF 1 mF bq24080 Charger IC bq24314C RBAT SYSTEM VBAT 6 100 kW VPU RPU 47 kW 47 kW FAULT 4 RFAULT ILIM VSS 47 kW 7 2 CE 5 Host Controller RCE RILM Figure 20. DETAILED FUNCTIONAL DESCRIPTION The bq24314C is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the charging circuit. The IC continuously monitors the input voltage, the input current and the battery voltage. In case of an input overvoltage condition, the IC immediately removes power from the charging circuit by turning off an internal switch. In the case of an overcurrent condition, it limits the system current at the threshold value, and if the overcurrent persists, switches the pass element OFF after a blanking period. If the battery voltage rises to an unsafe level, the IC disconnects power from the charging circuit until the battery voltage returns to an acceptable value. Additionally, the IC also monitors its own die temperature and switches off if it exceeds 140°C. The input overcurrent threshold is user-programmable. The IC can be controlled by a processor, and also provides status information about fault conditions to the host. POWER DOWN The device remains in power down mode when the input voltage at the IN pin is below the undervoltage threshold UVLO. The FET Q1 connected between IN and OUT pins is off, and the status output, FAULT, is set to Hi-Z. POWER-ON RESET The device resets when the input voltage at the IN pin exceeds the UVLO threshold. All internal counters and other circuit blocks are reset. The IC then waits for duration tDGL(PGOOD) for the input voltage to stabilize. If, after tDGL(PGOOD), the input voltage and battery voltage are safe, FET Q1 is turned ON. The IC has a soft-start feature to control the inrush current. The soft-start minimizes the ringing at the input (the ringing occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant circuit). Figure 2 shows the power-up behavior of the device. Because of the deglitch time at power-on, if the input voltage rises rapidly to beyond the OVP threshold, the device will not switch on at all, instead it will go into protection mode and indicate a fault on the FAULT pin, as shown in Figure 3. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C 11 bq24314C SLUSAV3 – AUGUST 2012 www.ti.com OPERATION The device continuously monitors the input voltage, the input current, and the battery voltage as described in detail in the following sections. Input Overvoltage Protection If the input voltage rises above VOVP, the internal FET Q1 is turned off, removing power from the circuit. As shown in Figure 4 to Figure 5, the response is very rapid, with the FET turning off in less than a microsecond. The FAULT pin is driven low. When the input voltage returns below VOVP – Vhys(OVP) (but is still above UVLO), the FET Q1 is turned on again after a deglitch time of tON(OVP) to ensure that the input supply has stabilized. Figure 6 shows the recovery from input OVP. Input Overcurrent Protection The overcurrent threshold is programmed by a resistor RILIM connected from the ILIM pin to VSS. Figure 15 shows the OCP threshold as a function of RILIM, and may be approximated by the following equation: IOCP = 25 ÷ RILIM (current in A, resistance in kΩ), where RILIM must be between 15 kΩ and 90 kΩ. If the load current tries to exceed the IOCP threshold, the device limits the current for a blanking duration of tBLANK(OCP). If the load current returns to less than IOCP before tBLANK(OCP) times out, the device continues to operate. However, if the overcurrent situation persists for tBLANK(OCP), the FET Q1 is turned off for a duration of tREC(OCP), and the FAULT pin is driven low. The FET is then turned on again after tREC(OCP) and the current is monitored all over again. Each time an OCP fault occurs, an internal counter is incremented. If 15 OCP faults occur in one charge cycle, the FET is turned off permanently. The counter is cleared either by removing and reapplying input power, or by disabling and re-enabling the device with the CE pin. Figure 7 to Figure 9 show what happens in an overcurrent fault. To prevent the input voltage from spiking up due to the inductance of the input cable, Q1 is turned off slowly, resulting in a “soft-stop”, as shown in Figure 9. Battery Overvoltage Protection The battery overvoltage threshold BVOVP is internally set to 4.45V. If the battery voltage exceeds the BVOVP threshold, the FET Q1 is turned off, and the FAULT pin is driven low. The FET is turned back on once the battery voltage drops to BVOVP – Vhys(Bovp) (see Figure 10 and Figure 11). Each time a battery overvoltage fault occurs, an internal counter is incremented. If 15 such faults occur in one charge cycle, the FET is turned off permanently. The counter is cleared either by removing and re-applying input power, or by disabling and re-enabling the device with the CE pin. In the case of a battery overvoltage fault, Q1 is switched OFF gradually (see Figure 10). Thermal Protection If the junction temperature of the device exceeds TJ(OFF), the FET Q1 is turned off, and the FAULT pin is driven low. The FET is turned back on when the junction temperature falls below TJ(OFF) – TJ(OFF-HYS). Enable Function The IC has an enable pin which can be used to enable or disable the device. When the CE pin is driven high, the internal FET is turned off. When the CE pin is low, the FET is turned on if other conditions are safe. The OCP counter and the Bat-OVP counter are both reset when the device is disabled and re-enabled. The CE pin has an internal pulldown resistor and can be left floating. Note that the FAULT pin functionality is also disabled when the CE pin is high. Fault Indication The FAULT pin is an active-low open-drain output. It is in a high-impedance state when operating conditions are safe, or when the device is disabled by setting CE high. With CE low, the FAULT pin goes low whenever any of these events occurs: • Input overvoltage • Input overcurrent • Battery overvoltage • IC Overtemperature 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C bq24314C www.ti.com SLUSAV3 – AUGUST 2012 Power Down All IC functions OFF FAULT = HiZ Any State if V(IN) < V (UVLO), go to Power Down No V(IN) > V(UVLO) ? Any State if CE = Hi, go to Reset Yes Reset Timers reset Counters reset FAULT = HiZ FET off No CE = Low ? V(IN) < V(OVP) ? No Turn off FET FAULT = Low No CE = Hi ? Yes Go to Reset Yes No I < IOCP ? No Turn off FET FAULT = Low Incr OCP counter Wait tREC(OCP) count <15 ? Yes No CE = Hi ? Yes Go to Reset No Turn off FET FAULT = Low VBAT < BATOVP ? No Incr BAT counter count <15 ? Yes TJ < TJ(OFF) ? No Turn off FET FAULT = Low Yes Turn on FET FAULT = HiZ Figure 21. Flow Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C 13 bq24314C SLUSAV3 – AUGUST 2012 www.ti.com APPLICATION INFORMATION (WITH REFERENCE TO FIGURE 20) Selection of RBAT It is strongly recommended that the battery not be tied directly to the VBAT pin of the device, as under some failure modes of the IC, the voltage at the IN pin may appear on the VBAT pin. This voltage can be as high as 30V, and applying 30V to the battery in case of the failure of the bq24314C can be hazardous. Connecting the VBAT pin through RBAT prevents a large current from flowing into the battery in case of a failure of the IC. In the interests of safety, RBAT should have a very high value. The problem with a large RBAT is that the voltage drop across this resistor because of the VBAT bias current IVBAT causes an error in the BVOVP threshold. This error is over and above the tolerance on the nominal 4.45V BVOVP threshold. Choosing RBAT in the range 100kΩ to 470kΩ is a good compromise. In the case of an IC failure, with RBAT equal to 100kΩ, the maximum current flowing into the battery would be (30V – 3V) ÷ 100kΩ = 246μA, which is low enough to be absorbed by the bias currents of the system components. RBAT equal to 100kΩ would result in a worst-case voltage drop of RBAT × IVBAT = 1mV. This is negligible to compared to the internal tolerance of 50mV on BVOVP threshold. If the Bat-OVP function is not required, the VBAT pin should be connected to VSS. Selection of RCE, RFAULT, and RPU The CE pin can be used to enable and disable the IC. If host control is not required, the CE pin can be tied to ground or left un-connected, permanently enabling the device. In applications where external control is required, the CE pin can be controlled by a host processor. As in the case of the VBAT pin (see above), the CE pin should be connected to the host GPIO pin through as large a resistor as possible. The limitation on the resistor value is that the minimum VOH of the host GPIO pin less the drop across the resistor should be greater than VIH of the bq24314C CE pin. The drop across the resistor is given by RCE × IIH. The FAULT pin is an open-drain output that goes low during OV, OC, battery-OV, and OT events. If the application does not require monitoring of the FAULT pin, it can be left unconnected. But if the FAULT pin has to be monitored, it should be pulled high externally through RPU, and connected to the host through RFAULT. RFAULT prevents damage to the host controller if the bq24314C fails (see above). The resistors should be of high value, in practice values between 22kΩ and 100kΩ should be sufficient. Selection of Input and Output Bypass Capacitors The input capacitor CIN in Figure 20 is for decoupling, and serves an important purpose. Whenever there is a step change downwards in the system load current, the inductance of the input cable causes the input voltage to spike up. CIN prevents the input voltage from overshooting to dangerous levels. It is strongly recommended that a ceramic capacitor of at least 1μF be used at the input of the device. It should be located in close proximity to the IN pin. COUT in Figure 20 is also important: If a very fast (< 1μs rise time) overvoltage transient occurs at the input, the current that charges COUT causes the device’s current-limiting loop to kick in, reducing the gate-drive to FET Q1. This results in improved performance for input overvoltage protection. COUT should also be a ceramic capacitor of at least 1μF, located close to the OUT pin. COUT also serves as the input decoupling capacitor for the charging circuit downstream of the protection IC. Powering Accessories In some applications, the equipment that the protection IC resides in may be required to provide power to an accessory (e.g. a cellphone may power a headset or an external memory card) through the same connector pins that are used by the adapter for charging. Figure 22 and Figure 23 illustrate typical charging and accessorypowering scenarios: 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C bq24314C www.ti.com SLUSAV3 – AUGUST 2012 Accessory power supply IN AC Adapter OUT Charger bq24314A e.g. cellphone DIS EN Battery pack to rest of system Figure 22. Charging - The Red Arrows Show the Direction of Current Flow Accessory power supply IN OUT bq24314A e.g. cellphone EN Charger DIS Battery pack to rest of system Figure 23. Powering an Accessory - The Red Arrows Show the Direction of Current Flow In the second case, when power is being delivered to an accessory, the bq24314C device is required to support current flow from the OUT pin to the IN pin. If VOUT > UVLO + 0.7V, FET Q1 is turned on, and the reverse current does not flow through the diode but through Q1. Q1 will then remain ON as long as VOUT > UVLO – Vhys(UVLO) + RDS(on) × IACCESSORY. Within this voltage range, the reverse current capability is the same as the forward capability, 1.5A. It should be noted that there is no overcurrent protection in this direction. PCB Layout Guidelines: • • • This device is a protection device, and is meant to protect down-stream circuitry from hazardous voltages. Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of PCB traces satisfy the design rules for high voltages. The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD should be thermally coupled with the PCB ground plane. In most applications, this will require a copper pad directly under the IC. This copper pad should be connected to the ground plane with an array of thermal vias. CIN and COUT should be located close to the IC. Other components like RILIM and RBAT should also be located close to the IC. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24314C 15 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) BQ24314CDSGR ACTIVE WSON DSG 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SDL BQ24314CDSGT ACTIVE WSON DSG 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SDL (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 7-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ24314CDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 BQ24314CDSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24314CDSGR WSON DSG 8 3000 210.0 185.0 35.0 BQ24314CDSGT WSON DSG 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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