TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com 50-V Input Voltage, 50-mA, Very High Voltage LINEAR REGULATOR Check for Samples: TPS7A41 FEATURES DESCRIPTION • • The TPS7A41 is a very high voltage-tolerant linear regulator that offers the benefits of a thermally-enhanced package (MSOP-8), and is able to withstand continuous dc or transient input voltages of up to 50 V. 1 23 • • • • • • • • • • Wide Input Voltage Range: 7 V to 50 V Accuracy: – Nominal: 1% – Over Line, Load, and Temperature: 2.5% Low Quiescent Current: 25 µA Quiescent Current at Shutdown: 4.1 µA Maximum Output Current: 50 mA CMOS Logic-Level-Compatible Enable Pin Adjustable Output Voltage: ~1.175 V to 48 V Stable with Ceramic Capacitors: – Input Capacitance: ≥ 1 µF – Output Capacitance: ≥ 4.7 µF Dropout Voltage: 290 mV Built-In Current-Limit and Thermal Shutdown Protection Package: High Thermal Performance MSOP-8 PowerPAD™ Operating Temperature Range: –40°C to +125°C APPLICATIONS • • • • • • Microprocessors, Microcontrollers Powered by Industrial Busses with High Voltage Transients Industrial Automation Telecom Infrastrucure Automotive LED Lighting Bias Power Supplies DGN PACKAGE 3-mm ´ 5-mm MSOP-8 PowerPAD (TOP VIEW) OUT FB NC GND 1 2 3 4 8 7 6 5 IN NC NC EN The TPS7A41 is stable with any output capacitance greater than 4.7 µF and any input capacitance greater than 1 µF (over temperature and tolerance). Therefore, implementations of this device require minimal board space because of its miniaturized packaging (MSOP-8) and a potentially small output capacitor. In addition, the TPS7A41 offers an enable pin (EN) compatible with standard CMOS logic to enable a low-current shutdown mode. The TPS7A41 has an internal thermal shutdown and current limiting to protect the system during fault conditions. The MSOP-8 packages has an operating temperature range of TJ = –40°C to +125°C. In addition, the TPS7A41 is ideal for generating a low-voltage supply from intermediate voltage rails in telecom and industrial applications; not only it can supply a well-regulated voltage rail, but it can also withstand and maintain regulation during very high and fast voltage transients. These features translate to simpler and more cost-effective electrical surge-protection circuitry for a wide range of applications. Typical Application 50 V VIN VIN VOUT OUT IN CIN CBYP Device VEN R1 COUT EN GND FB R2 Post DC/DC Converter Regulation for High-Performace Analog Circuitry 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT TPS7A4101 yyy z (1) YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE Voltage Current MAX UNIT IN pin to GND pin –0.3 +55 V OUT pin to GND pin –0.3 +55 V OUT pin to IN pin –55 +0.3 V FB pin to GND pin –0.3 +2 V FB pin to IN pin –55 +0.3 V EN pin to IN pin –55 0.3 EN pin to GND pin –0.3 Peak output Temperature Electrostatic discharge rating (1) MIN +55 V Internally limited Operating virtual junction, TJ –40 +125 Storage, Tstg –65 +150 °C °C Human body model (HBM) 2.5 kV Charged device model (CDM) 500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TPS7A4001 THERMAL METRIC (1) DGN UNITS 8 PINS θJA Junction-to-ambient thermal resistance 55.09 θJC(top) Junction-to-case(top) thermal resistance 8.47 θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter 0.36 ψJB Junction-to-board characterization parameter 14.6 θJC(bottom) Junction-to-case(bottom) thermal resistance — (1) — °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. DISSIPATION RATINGS (1) 2 BOARD PACKAGE RθJA RθJC DERATING FACTOR ABOVE TA = +25°C TA ≤ +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING High-K (1) DGN 55.9°C/W 8.47°C/W 16.6mW/°C 1.83W 1.08W 0.833W The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 2.0 V or VIN = 7.0 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT = 4.7 μF, and FB tied to OUT, unless otherwise noted. TPS7A41 PARAMETER TEST CONDITIONS VIN Input voltage range VREF Internal reference MIN TYP 7.0 TJ = +25°C, VFB = VREF, VIN = 9 V, IOUT = 25 mA (1) 1.161 1.173 MAX UNIT 50.0 V 1.185 V VIN ≥ VOUT(NOM) + 2.0 V VREF 48 Nominal accuracy TJ = +25°C, VIN = 9 V, IOUT = 25 mA –1.0 +1.0 %VOUT Overall accuracy VOUT(NOM) + 2.0 V ≤ VIN ≤ 24 V (2) 100 µA ≤ IOUT ≤ 50 mA –2.5 +2.5 %VOUT ΔVO(ΔVI) Line regulation 7 V ≤ VIN ≤ 50 V 0.03 %VOUT ΔVO(ΔVL) Load regulation 100 µA ≤ IOUT ≤ 50 mA 0.31 %VOUT VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 20 mA 290 mV Output voltage range VOUT VDO Dropout voltage VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 50 mA ILIM Current limit IGND Ground current ISHDN Shutdown supply current V 0.78 1.3 V VOUT = 90% VOUT(NOM), VIN = 7.0 V, TJ ≤ +85°C 51 117 200 mA VOUT = 90% VOUT(NOM), VIN = 9.0 V 51 128 200 mA 7 V ≤ VIN ≤ 50 V, IOUT = 0 mA 25 65 μA IOUT = 50 mA 25 VEN = +0.4 V 4.1 20 μA 0.01 0.1 µA 0.02 1.0 μA (3) –0.1 μA I FB Feedback current IEN Enable current VEN_HI Enable high-level voltage 1.5 VIN V VEN_LO Enable low- level voltage 0 0.4 V VNOISE Output noise voltage PSRR Power-supply rejection ratio TSD Thermal shutdown temperature TJ Operating junction temperature range (1) (2) (3) (4) 7 V ≤ VIN ≤ 50 V, VIN = VEN VIN = 12 V, VOUT(NOM) = VREF, COUT = 10 μF, BW = 10 Hz to 100 kHz 58 μVRMS VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF, CBYP (4) = 10 nF, BW = 10 Hz to 100 kHz 73 μVRMS VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF, CBYP (4) = 10 nF, f = 100 Hz 65 dB Shutdown, temperature increasing +170 °C Reset, temperature decreasing +150 °C –40 +125 °C To ensure stability at no-load conditions, a current from the feedback resistive network greater than or equal to 10 μA is required. Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT = (24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking. IFB > 0 flows out of the device. CBYP refers to a bypass capacitor connected to the FB and OUT pins. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 3 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM IN OUT UVLO Pass Device Thermal Shutdown Current Limit Error Amp Enable EN FB TYPICAL APPLICATION CIRCUIT VIN CIN 10 mF VEN CBYP 10 nF Device EN VOUT OUT IN GND R1 FB Where: COUT 10 mF VOUT ³ 10 mA, and R1 + R2 R1 = R2 R2 VOUT -1 VREF Example Circuit to Maximize Transient Performance 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com PIN CONFIGURATION DGN PACKAGE MSOP-8 (TOP VIEW) OUT FB NC GND 1 2 3 4 8 7 6 5 IN NC NC EN PIN DESCRIPTIONS TPS7A41 NAME NO. DESCRIPTION EN 5 This pin turns the regulator on or off. If VEN ≥ VEN_HI the regulator is enabled. If VEN ≤ VEN_LO, the regulator is disabled. If not used, the EN pin can be connected to IN. Make sure that VEN ≤ VIN at all times. FB 2 This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device. GND 4 Ground IN 8 Input supply NC 3, 6, 7 OUT 1 PowerPAD Not internally connected. This pin must either be left open or tied to GND. Regulator output. A capacitor greater than 4.7 µF must be tied from this pin to ground to assure stability. Solder to printed circuit board (PCB) to enhance thermal performance. NOTE: The PowerPAD is internally connected to GND. Although it can be left floating, it is highly recommended to connect the PowerPAD to the GND plane. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 5 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 2.0 V or VIN = 9.0 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT = 4.7 μF, and FB tied to OUT, unless otherwise noted. LOAD TRANSIENT RESPONSE LINE REGULATION 10 VIN = 12V, VOUT = 5V DIOUT = 1mA®29mA®1mA COUT = 10mF, CBYP = 10nF 5 VOUT(NOM) (%) VOUT 50mV/div −40°C +25°C +85°C 7.5 2.5 0 −2.5 −5 IOUT 10mA/div −7.5 −10 Time (100ms/div) 5 10 15 20 Figure 1. 25 30 35 Input Voltage (V) 40 45 50 G001 Figure 2. FEEDBACK VOLTAGE QUIESCENT CURRENT vs INPUT VOLTAGE 1.275 100 −40°C +25°C +85°C +105°C +125°C −40°C +25°C +85°C +105°C +125°C 80 IQ (µA) 1.225 VFB (V) +105°C +125°C 1.175 1.125 60 40 20 IOUT = 0 mA 1.075 5 10 15 20 25 30 35 Input Voltage (V) 40 45 0 50 5 10 15 G002 Figure 3. 90 90 80 80 70 70 60 60 50 40 50 G003 40 30 20 20 10 10 80 95 110 125 − 40°C + 25°C + 85°C + 105°C + 125°C 0 0 Figure 5. 6 45 50 30 20 35 50 65 Temperature (°C) 40 GROUND CURRENT 100 IGND (µA) IFB (nA) FEEDBACK CURRENT 5 25 30 35 Input Voltage (V) Figure 4. 100 0 −40 −25 −10 20 10 20 30 Output Current (mA) 40 50 Figure 6. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 2.0 V or VIN = 9.0 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT = 4.7 μF, and FB tied to OUT, unless otherwise noted. DROPOUT VOLTAGE ENABLE THRESHOLD VOLTAGE 2 2.5 − 40°C + 25°C + 85°C 1.75 + 105°C + 125°C 2 1.5 VEN (V) VDROP (V) 1.25 1 0.75 1.5 OFF−TO−ON 1 0.5 0.5 ON−TO−OFF 0.25 0 0 10 20 30 Output Current (mA) 40 0 −40 −25 −10 50 5 20 35 50 65 Temperature (°C) Figure 7. 80 95 110 125 Figure 8. OUTPUT SPECTRAL NOISE DENSITY CURRENT LIMIT 10 200 160 ICL (mA) Noise (µV/ Hz) 1 0.1 VIN = 12V VOUT = VREF COUT = 10µF CBYP = 10nF 0.01 0.001 10 100 120 80 − 40°C + 25°C + 85°C + 105°C + 125°C 40 IOUT = 100µA,VNOISE = 60µVRMS IOUT = 50mA,VNOISE = 100µVRMS 1k 10k 100k Frequency (Hz) 1M 0 10M 6 9 12 Figure 9. 15 18 Input Voltage (V) 21 24 Figure 10. POWER-SUPPLY REJECTION RATIO 100 90 80 PSRR (dB) 70 60 50 40 30 VIN = 12V VOUT = 5V COUT = 10µF CBYP = 10nF 20 10 0 10 100 IOUT = 50mA IOUT = 100µA 1k 10k 100k Frequency (Hz) 1M 10M Figure 11. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 7 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The TPS7A4101 belongs to a new generation of linear regulators that use an innovative BiCMOS process technology to achieve very high maximum input and output voltages. This process not only allows the TPS7A4101 to maintain regulation during very fast high-voltage transients up to 50 V, but it also allows the TPS7A4101 to regulate from a continuous high-voltage input rail. Unlike other regulators created using bipolar technology, the TPS7A4101 ground current is also constant over its output current range, resulting in increased efficiency and lower power consumption. These features, combined with a high thermal performance MSOP-8 PowerPAD package, make this device ideal for industrial and telecom applications. ADJUSTABLE OPERATION The TPS7A4101 has an output voltage range of ~1.175 V to 48 V. The nominal output voltage of the device is set by two external resistors, as shown in Figure 12. VOUT VIN CIN 10 mF OUT IN CBYP 10 nF Device EN GND R1 FB COUT 10 mF R2 Figure 12. Adjustable Operation for Maximum AC Performance R1 and R2 can be calculated for any output voltage range using the formula shown in Equation 1. To ensure stability under no-load conditions, this resistive network must provide a current greater than or equal to 10 μA. VOUT VOUT ³ 10 mA R1 = R2 - 1 , where R1 + R2 VREF (1) If greater voltage accuracy is required, take into account the output voltage offset contributions because of the feedback pin current and use 0.1% tolerance resistors. ENABLE PIN OPERATION The TPS7A4101 provides an enable pin (EN) feature that turns on the regulator when VEN > 1.5 V. CAPACITOR RECOMMENDATIONS Low equivalent series resistance (ESR) capacitors should be used for the input, output, and bypass capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics. Ceramic X7R capacitors offer improved over-temperature performance, while ceramic X5R capacitors are the most cost-effective and are available in higher values. Note that high ESR capacitors may degrade PSRR. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com INPUT AND OUTPUT CAPACITOR REQUIREMENTS The TPS7A4101 high voltage linear regulator achieves stability with a minimum output capacitance of 4.7 µF and input capacitance of 1 µF; however, it is highly recommended to use 10-μF output and input capacitors to maximize ac performance. BYPASS CAPACITOR REQUIREMENTS Although a bypass capacitor (CBYP) is not needed to achieve stability, it is highly recommended to use a 10-nF bypass capacitor to maximize ac performance (including line transient, noise and PSRR). MAXIMUM AC PERFORMANCE In order to maximize line transient, noise, and PSRR performance, it is recommended to include 10-μF (or higher) input and output capacitors, and a 10-nF bypass capacitor; see Figure 12. The solution shown delivers minimum noise levels of 58 μVRMS and power-supply rejection levels above 36 dB from 10 Hz to 10 MHz. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. Note that the presence of the CBYP capacitor may greatly improve the TPS7A4101 line transient response, as noted in . Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 9 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com APPLICATION INFORMATION TRANSIENT VOLTAGE PROTECTION One of the primary applications of the TPS7A4101 is to provide transient voltage protection to sensitive circuitry that may be damaged in the presence of high-voltage spikes. This transient voltage protection can be more cost-effective and compact compared to topologies that use a transient voltage suppression (TVS) block. LED ARRAY DRIVER The TPS7A4101 can be used to drive several LED drivers connected in series, as shown in Figure 13. ILED = ILED VREF RSET 50 V OUT IN COUT Device EN EN RSET FB GND Figure 13. LED Array Driver Application The TPS7A4101 high voltage rating makes it suitable not only for driving the intensity of an array of multiple LEDs by using a PWM signal at its EN pin, but also for controlling such an array. This PWM signal enables and disables the regulator, causing the LED light to vary its intensity. 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com Whenever the regulator is disabled, no current flows through the LED array. This condition means that the regulator has the same high voltage applied to the first LED in the array as is applied to the regulator input. Figure 14 illustrates the solution to this problem with the addition of the TPS7A4101 high-voltage regulator. 100 V I = 0 mA 50 V 50 V OUT IN COUT Device Low EN RSET FB GND Figure 14. LED Array Driver with Regulator Disabled Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 11 TPS7A41 SBVS183 – DECEMBER 2011 www.ti.com LAYOUT PACKAGE MOUNTING Solder pad footprint recommendations for the TPS7A4101 are available at the end of this product data sheet and at www.ti.com. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor (CIN, COUT, CBYP) must be placed as close as possible to the device and on the same side of the PCB as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for TPS7A41 evaluation board, available at www.ti.com. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +170°C, allowing the device to cool. When the junction temperature cools to approximately +150°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to a maximum of +125°C. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS7A4101 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A4101 into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Dissipation Ratings Table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element, as shown in Equation 2: PD = (VIN - VOUT) IOUT (2) 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS7A41 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPS7A4101DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7A4101DGNT ACTIVE MSOPPowerPAD DGN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A4101DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS7A4101DGNT MSOPPower PAD DGN 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A4101DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0 TPS7A4101DGNT MSOP-PowerPAD DGN 8 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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