DS90CP02 DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch Literature Number: SNLS267 DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch General Description Features The DS90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs. Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. The 3.3V supply, CMOS process, and LVDS I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1.5 Gbps per channel Low power: 70 mA in dual repeater mode @1.5 Gbps Low output jitter Non-blocking architecture allows 1:2 splitter, 2:1 mux, crossover, and dual buffer configurations Flow-through pinout LVDS/BLVDS/CML/LVPECL inputs, LVDS Outputs Single 3.3V supply Separate control of inputs and outputs allows for power savings Industrial -40 to +85°C temperature range 28-lead LLP-28 space saving package Block Diagram 30011901 FIGURE 1. DS90CP02 Block Diagram © 2008 National Semiconductor Corporation 300119 www.national.com DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch November 20, 2008 DS90CP02 Pin Descriptions Pin Name Pin Number I/O, Type Description DIFFERENTIAL INPUTS COMMON TO ALL MUXES IN0+ IN0− 9 10 I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. IN1+ IN1− 12 13 I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SWITCHED DIFFERENTIAL OUTPUTS OUT0+ OUT0− 27 26 O, LVDS Inverting and non-inverting differential outputs. OUT0± can be connected to any one pair IN0±, or IN1±. LVDS compatible . OUT1+ OUT1− 24 23 O, LVDS Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair IN0±, or IN1±. LVDS compatible . DIGITAL CONTROL INTERFACE SEL0, SEL1 6 5 I, LVTTL Select Control Inputs EN0, EN1 7 15 I, LVTTL Output Enable Inputs N/C 8, 20, 28 Not Connected POWER VDD 11, 14, 16, 18, 19, 22, 25 I, Power VDD = 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be connected from VDD to GND plane. GND DAP, 1, 2, 3, 4, 17, 21 I, Power Ground reference to LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-28 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. www.national.com 2 DS90CP02 Connection Diagram 30011903 LLP Top View DAP = GND Configuration Select Truth Table SEL0 SEL1 EN0 EN1 OUT0 OUT1 0 0 0 0 IN0 IN0 1:2 Splitter (IN1 powered down) Mode 0 1 0 0 IN0 IN1 Dual Channel Repeater 1 0 0 0 IN1 IN0 Dual Channel Switch 1 1 0 0 IN1 IN1 1:2 Splitter (IN0 powered down) 0 1 0 1 IN0 PD Single Channel Repeater (Channel 1 powered down) 1 1 0 1 IN1 PD Single Channel Switch (IN0 and OUT1 powered down) 0 0 1 0 PD IN0 Single Channel Switch (IN1 and OUT0 powered down) 0 1 1 0 PD IN1 Single Channel Repeater (Channel 0 powered down) X X 1 1 PD PD Both Channels in Power Down Mode 0 0 0 1 Invalid State* 1 0 0 1 Invalid State* 1 0 1 0 Invalid State* 1 1 1 0 Invalid State* PD = Power Down mode to minimize power consumption X = Don't Care * Entering these states is not forbidden, however device operation is not defined in these states. 3 www.national.com DS90CP02 Application Information 30011902 FIGURE 2. DS90CP02 Configuration Select Decode www.national.com 4 34.5 mW/°C Thermal Resistance, θJA LLP-28 ESD Rating If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) −0.3V to +4.0V CMOS Input Voltage −0.3V to (VDD +0.3V) LVDS Receiver Input Voltage −0.3V to +3.6V LVDS Driver Output Voltage −0.3V to +3.6V LVDS Output Short Circuit Current 40mA Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4sec.) +260°C Maximum Package Power Dissipation at 25°C LLP-28 4.31 W Derating above 25°C 29°C/W HBM, 1.5 kΩ, 100 pF 6.5 kV EIAJ, 0Ω, 200 pF >250V Recommended Operating Conditions Supply Voltage (VDD– GND) Receiver Input Voltage Operating Free Air Temperature Junction Temperature Min 3.0 0 Typ 3.3 −40 25 Max Unit 3.6 V 3.6 V 85 150 °C °C Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 2) Max Units LVTTL DC SPECIFICATIONS (SEL0, SEL1, EN1, EN2) VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to VSS VCL Input Clamp Voltage ICL = −18 mA −1.5 3.5 pF −0.8 V LVDS INPUT DC SPECIFICATIONS (IN0±, IN1±) VTH Differential Input High Threshold (Note 3) VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VTL Differential Input Low Threshold VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VID Differential Input Voltage VCM = 0.8V to 3.55V, VDD = 3.6V 100 VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.6V 0.05 CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 3.6V, VDD = VDDMAX or 0V VIN = 0V, VDD = VDDMAX or 0V 0 −100 100 0 mV mV mV 3.55 V −10 +10 µA −10 +10 µA 575 mV 35 mV 1.475 V 35 mV -90 mA 3.5 pF LVDS OUTPUT DC SPECIFICATIONS (OUT0±, OUT1±) RL = 100Ω between OUT+ and OUT− VOD Differential Output Voltage, 0% Pre-emphasis (Note 3) ΔVOD Change in VOD between Complementary States −35 VOS Offset Voltage (Note 4) 1.09 ΔVOS Change in VOS between Complementary States −35 IOS Output Short Circuit Current, One Complementary Output OUT+ or OUT− Short to GND COUT Output Capacitance OUT+ or OUT− to GND when TRISTATE 5 250 400 1.25 −60 5.5 pF www.national.com DS90CP02 LLP-28 Absolute Maximum Ratings (Note 1) DS90CP02 Symbol Parameter Conditions Min Typ (Note 2) Max Units 42 60 mA SUPPLY CURRENT (Static) ICC0 Supply Current All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. ICC1 Supply Current - one channel powered down Single channel crossover switch or single channel repeater modes (1 channel active, one channel in power down mode) 22 30 mA ICC2 Supply Current - one input powered Splitter mode (One input powered down, down both outputs active) 30 40 mA ICCZ TRI-STATE Supply Current 1.4 2.5 mA 70 150 215 ps 50 135 180 ps 0.5 2.4 3.5 ns 0.5 2.4 3.5 ns 55 120 ps 130 315 ps 1.4 2.5 psrms DJ - K28.5 Pattern 1.5 Gbps (Note 7) 42 75 psp-p TJ - PRBS 223-1 Pattern 1.5 Gbps (Note 8) 93 126 psp-p 110 150 ns 5 12 ns 110 150 ns Both input/output Channels in Power Down Mode SWITCHING CHARACTERISTICS—LVDS OUTPUTS (Figures 3, 4) tLHT Differential Low to High Transition Time tHLT Differential High to Low Transition Time tPLHD Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200 Delay Mb/s, measure at 50% VOD between Differential High to Low Propagation input to output. Delay tPHLD Use an alternating 1 and 0 pattern at 200 Mb/s, measure between 20% and 80% of VOD. tSKD1 Pulse Skew |tPLHD–tPHLD| tSKCC Output Channel to Channel Skew Difference in propagation delay (tPLHD or tPHLD) among all output channels in Splitter mode (any one input to all outputs). tJIT Jitter (Note 5) 0 RJ - Clock Pattern 750 MHz (Note 6) tON LVDS Output Enable Time Time from ENx to OUT± change from TRI-STATE to active. tOFF LVDS Output Disable Time Time from ENx to OUT± change from active to TRI-STATE. tSW LVDS Switching Time SELx to OUT± Time from configuration select (SELx) to new switch configuration effective for OUT±. 50 Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Note 3: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Note 4: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 5: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 6: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 750MHz, tr = tf = 50ps (20% to 80%). Note 7: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Note 8: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). www.national.com 6 DS90CP02 Timing Diagrams 30011915 FIGURE 3. LVDS Signals 30011916 FIGURE 4. LVDS Output Transition Time 30011917 FIGURE 5. LVDS Output Propagation Delay 7 www.national.com DS90CP02 30011920 FIGURE 6. Configuration and Output Enable/Disable Timing www.national.com 8 DS90CP02 Typical Performance Total Jitter (TJ) vs. Bit Data Rate Total Jitter (TJ) vs. Temperature 30011943 30011942 Total Jitter measured at 0V differential while running a PRBS 223-1 pattern in dual channel repeater mode. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate Total Jitter measured at 0V differential while running a PRBS 223-1 pattern in single channel repeater mode. VCC = 3.3V, TA = +25°C, VID = 0.5V 9 www.national.com DS90CP02 Physical Dimensions inches (millimeters) unless otherwise noted LLP, Plastic, QUAD, Order Number DS90CP02SP (1000 piece Tape and Reel), DS90CP02SPX (4500 piece Tape and Reel) NS Package Number SPA28A www.national.com 10 DS90CP02 Notes 11 www.national.com DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy PowerWise® Solutions www.national.com/powerwise Solutions www.national.com/solutions Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero Temperature Sensors www.national.com/tempsensors Solar Magic® www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless Analog University® www.national.com/AU THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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