TI DS90CF384AQ

DS90CF384AQ
DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65
MHz
Literature Number: SNLS345
DS90CF384AQ
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link
- 65 MHz
General Description
Features
The DS90CF384AQ receiver converts the four LVDS data
streams at up to 1.8 Gbps throughput (227 Megabytes/sec
bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data.
In a Display application, the 28 bits include: 24 bits of RGB
data and up to 4 bits of video control (Hsync, Vsync, DE and
CNTL).
The DS90CF384AQ device is enhanced over prior generation
FPD-Link receivers, provides a wider data valid time on the
receiver output and is offered as an AEC-Q100 grade 3 device.
FPD-Link is an ideal means to solve EMI and cable size problems associated with wide, high speed LVCMOS/LVTTL interfaces.
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Automotive grade device, AEC-Q100 grade 3 qualified
Operating Temperature Range: –40°C to +85°C
20 to 65 MHz shift clock support
50% duty cycle on receiver output clock
Best–in–Class Set & Hold Times on RxOUTPUTs
Rx power consumption <142 mW (typ) @65MHz
Grayscale
Rx Power-down mode <200μW (max)
ESD rating >7 kV (HBM), >700V (EIAJ)
Supports VGA, SVGA, XGA and Dual Pixel SXGA.
PLL requires no external components
Compatible with TIA/EIA-644 LVDS standard
Low profile 56-lead TSSOP package
Block Diagram
DS90CF384AQ
30161127
Order Number DS90CF384AQMT
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
301611
www.national.com
DS90CF384AQ +3.3V LVDS Receiver 24-Bit-Color Flat Panel Display (FPD) Link - 65 MHz
August 1, 2011
DS90CF384AQ
Maximum Package Power
Dissipation Capacity @ 25°C
MTD56 Package:
MTD56 Package Derating:
ESD Rating
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
−0.3V to +4V
LVCMOS/LVTTL Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS/LVTTL Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage
−0.3V to (VCC + 0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
1.61 W
12.4 mW/°C above +25°C
(HBM, 1.5 kΩ, 100 pF)
> 7 kV
(EIAJ, 0Ω, 200 pF)
> 700V
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA )
Receiver Input Range
Supply Noise Voltage (VCC)
Min
3.0
Nom
3.3
Max
3.6
Units
V
−40
0
+25
+85
2.4
100
°C
V
mVPP
Min
Typ
Max
Units
VCC
V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
LVCMOS/LVTTL DC SPECIFICATIONS (For Power Down Pin)
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
V IN = 0.4V, 2.5V or VCC
GND
V IN = GND
−10
2.7
0.8
V
−0.79
−1.5
V
+1.8
+10
μA
μA
0
LVCMOS/LVTTL DC SPECIFICATIONS
VOH
High Level Output Voltage
IOH = −0.4 mA
VOL
Low Level Output Voltage
IOL = 2 mA
0.06
3.3
0.3
V
V
IOS
Output Short Circuit Current
VOUT = 0V
−60
−120
mA
+100
mV
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
IIN
Input Current
V CM = +1.2V
−100
mV
V IN = +2.4V, VCC = 3.6V
±10
μA
V IN = 0V, VCC = 3.6V
±10
μA
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current
Worst Case
CL = 8 pF, Worst Case
Pattern, (Figures 1, 3 )
Receiver Supply Current,
CL = 8 pF,
16 Grayscale
Receiver Supply Current
Power Down
f = 32.5 MHz
49
65
mA
f = 37.5 MHz
53
70
mA
f = 65 MHz
81
105
mA
f = 32.5 MHz
28
mA
16 Grayscale Pattern,
f = 37.5 MHz
30
mA
(Figures 2, 3 )
f = 65 MHz
43
Power Down = Low, Receiver Outputs Stay
Low during Power Down Mode
10
mA
55
μA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ΔV OD).
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2
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3 )
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3 )
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 9 )
RSPos1
Min
Typ
Max
Units
2
5
ns
1.8
5
ns
1.20
1.96
2.82
ns
Receiver Input Strobe Position for Bit 1
6.91
7.67
8.53
ns
RSPos2
Receiver Input Strobe Position for Bit 2
12.62
13.38
14.24
ns
RSPos3
Receiver Input Strobe Position for Bit 3
18.33
19.09
19.95
ns
RSPos4
Receiver Input Strobe Position for Bit 4
24.04
24.80
25.66
ns
RSPos5
Receiver Input Strobe Position for Bit 5
29.75
30.51
31.37
ns
RSPos6
Receiver Input Strobe Position for Bit 6
35.46
36.22
37.08
ns
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 9 )
0.7
1.1
1.4
ns
RSPos1
Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2
Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3
Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4
Receiver Input Strobe Position for Bit 4
9.5
9.9
10.2
ns
RSPos5
Receiver Input Strobe Position for Bit 5
11.7
12.1
12.4
ns
RSPos6
Receiver Input Strobe Position for Bit 6
13.9
14.3
14.6
ns
RSKM
RxIN Skew Margin(Note 4) (Figure 10 )
f = 25 MHz
f = 65 MHz
f = 25 MHz
750
ps
f = 65 MHz
500
ps
15
T
50
ns
f = 65 MHz
5.0
7.6
9.0
ns
9.0
ns
RCOP
RxCLK OUT Period (Figure 4)
RCOH
RxCLK OUT High Time (Figure 4)
RCOL
RxCLK OUT Low Time (Figure 4)
5.0
6.3
RSRC
RxOUT Setup to RxCLK OUT (Figure 4)
4.5
7.3
RHRC
RxOUT Hold to RxCLK OUT (Figure 4)
4.0
6.3
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 5 )
3.5
5.0
RPLLS
RPDD
ns
ns
7.5
ns
Receiver Phase Lock Loop Set (Figure 6 )
10
ms
Receiver Power Down Delay (Figure 8 )
1
μs
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383B transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). The RSKM will change when different
transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less
than 250 ps).
3
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DS90CF384AQ
Receiver Switching Characteristics
DS90CF384AQ
AC Timing Diagrams
30161102
FIGURE 1. “Worst Case” Test Pattern (Note 5)
30161112
FIGURE 2. “16 Grayscale” Test Pattern (Note 6, Note 7, Note 8)
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figure 1 and Figure 2 shows a falling edge data strobe (TxCLK IN / RxCLK OUT).
Note 8: Recommended pin to signal mapping. Application may choose to define differently, check compatibility with source.
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4
DS90CF384AQ
30161104
FIGURE 3. Receiver CMOS/TTL Output Load and Transition Times
30161105
FIGURE 4. Receiver Output Setup/Hold and High/Low Times
30161106
FIGURE 5. Receiver Clock In to Clock Out Delay
30161107
FIGURE 6. Receiver Phase Lock Loop Set Time
5
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DS90CF384AQ
30161109
FIGURE 7. 28 Parallel TTL Data Inputs/Outputs Mapped to LVDS Bits (TxINn / RxOUTn)
30161108
FIGURE 8. Receiver Power Down Delay
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6
DS90CF384AQ
30161125
FIGURE 9. Receiver LVDS Input Strobe Position
30161111
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Note 9: Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
Note 10: ISI is dependent on interconnect length; may be zero.
FIGURE 10. Receiver LVDS Input Skew Margin
7
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DS90CF384AQ
DS90CF384AQ Pin Descriptions — 56L TSSOP Package
Pin Name
I/O
No.
Description
RxIN+
I
4
Positive LVDS differentiaI data inputs.
RxIN−
I
4
Negative LVDS differential data inputs.
RxOUT
O
28
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
I
1
Positive LVDS differential clock input.
RxCLK IN−
I
1
Negative LVDS differential clock input.
RxCLK OUT
O
1
TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN
I
1
TTL level input. When asserted (low input) the receiver outputs are low.
VCC
I
4
Power supply pins for TTL outputs.
GND
I
5
Ground pins for TTL outputs.
PLL VCC
I
1
Power supply for PLL.
PLL GND
I
2
Ground pin for PLL.
LVDS VCC
I
1
Power supply pin for LVDS inputs.
LVDS GND
I
3
Ground pins for LVDS inputs.
Pin Diagram for TSSOP Package
DS90CF384AQ
30161123
www.national.com
8
DS90CF384AQ
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Dimensions shown in millimeters only
Order Number DS90CF384AQMT
NS Package Number MTD56
9
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DS90CF384AQ +3.3V LVDS Receiver 24-Bit-Color Flat Panel Display (FPD) Link - 65 MHz
Notes
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