DS90C032QML DS90C032QML LVDS Quad CMOS Differential Line Receiver Literature Number: SNLS203C DS90C032QML LVDS Quad CMOS Differential Line Receiver General Description Features The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE® function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions. The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. ■ ■ ■ ■ ■ ■ ■ ■ Single Event Latchup (SEL) Immune 120 MeV-cm2/mg High impedance LVDS inputs with power-off. Accepts small swing (330 mV) differential signal levels Low power dissipation. Low differential skew. Low chip to chip skew. Pin compatible with DS26C32A Compatible with IEEE 1596.3 SCI LVDS standard Ordering Information NS Part Number SMD Part Number NS Package Number DS90C032E-QML 5962–9583401Q2A E20A 20LD Leadless Chip Carrier Package Description DS90C032W-QMLV 5962–9583401VFA W16A 16LD Ceramic Flatpack DS90C032WLQMLV 5962L9583401VFA 50 krad(Si) W16A 16LD Ceramic Flatpack DS90C032WGLQMLV 5962L9583401VZA 50 krad(Si) WG16A 16LD Ceramic SOIC Connection Diagrams Dual-In-Line Pictured 20163701 See NS Package Number W16A & WG16A TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 201637 www.national.com DS90C032QML LVDS Quad CMOS Differential Line Receiver September 28, 2010 DS90C032QML Leadless Chip Carrier Package 20163720 See NS Package Number E20A Functional Diagram and Truth Tables 20163702 www.national.com 2 DS90C032QML Receiver INPUTS OUTPUT EN ENABLES EN* RI+ − RI− RO L H X Z All other combinations VID ≥ 0.1V H of ENABLE inputs VID ≤ −0.1V L 3 www.national.com DS90C032QML Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) Input Voltage (RI+, RI−) Enable Input Voltage (EN, EN*) Output Voltage (RO) Storage Temperature Range (TStg) −0.3V to +6V −0.3V to +5.8V −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −65°C ≤ TA ≤ +150°C +260°C Lead Temperature Range Soldering (4 sec.) Maximum Package Power Dissipation @ +25°C (Note 2) LCC Package Ceramic Flatpack Ceramic SOIC Thermal Resistance 1,830 mW 1,400 mW 1,400 mW θJA LCC Package Ceramic Flatpack Ceramic SOIC 82°C/W 145°C/W 145°C/W θJC LCC Package Ceramic Flatpack Ceramic SOIC ESD Rating (Note 3) 20°C/W 20°C/W 20°C/W 2KV Recommended Operating Conditions Min +4.5V Gnd −55°C Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature (TA) Typ +5.0V Max +5.5V 2.4V +125°C +25°C Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A www.national.com Subgroup Description 1 Static tests at Temp °C +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 4 DC Parameters Symbol (Note 7) Parameter Conditions Notes Min Max Units Subgroups VThL Differential Input Low Threshold VCM = +1.2V (Note 4) -100 mV 1, 2, 3 VThH Differential Input High Threshold VCM = +1.2V (Note 4) 100 mV 1, 2, 3 IIn Input Current ( Input Pins) VCC=5.5V, VI = 2.4V ±10 µA 1, 2, 3 VCC = 5.5V, VI = 0 ±10 µA 1, 2, 3 VCC = 0.0V, VI = 2.4V ±10 µA 1, 2, 3 VCC = 0.0V, VI = 0.0V ±10 µA 1, 2, 3 V 1, 2, 3 0.3 V 1, 2, 3 -100 mA 1, 2, 3 ±10 µA 1, 2, 3 VOH Output High Voltage VCC= 4.5V, IOH = -0.4 mA, VID = 200mV VOL Output Low Voltage VCC = 4.5, IOL = 2 mA, VID = -200mV IOS Output Short Circuit Current Enabled, VO = 0V IOZ Output TRI-STATE Current Disabled, VO = 0V or VCC VIH Input High Voltage (Note 4) VIL Input Low Voltage (Note 4) II Input Current (Enable Pins) VCL ICC ICCZ 3.8 -15 V 1, 2, 3 0.8 V 1, 2, 3 VCC = 5.5V ±10 µA 1, 2, 3 Input Clamp Voltage ICl = -18mA -1.5 V 1, 2, 3 No Load Supply Current EN, EN* = VCC or Gnd, Inputs Open 11 mA 1, 2, 3 EN, EN* = 2.4 or 0.5, Inputs Open 11 mA 1, 2, 3 EN = Gnd, EN* = VCC , Inputs Open 11 mA 1, 2, 3 Min Max Units Subgroups No Load Supply Current Receivers Disabled 2.0 AC Parameters (Note 7) The following conditions apply, unless otherwise specified. AC: VCC = 4.5V / 5.0V / 5.5V, CL = 20pF Symbol Parameter Conditions Notes tPHLD Differential Propagation Delay High to Low VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC 1.0 8.0 ns 9, 10, 11 tPLHD Differential Propagation Delay Low to High VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC 1.0 8.0 ns 9, 10, 11 tSkD Differential Skew |tPHLD - tPLHD| CL = 20pF, VID = 200mV 3.0 ns 9, 10, 11 tSk1 Channel to Channel Skew CL = 20pF, VID = 200mV (Note 5) 3.0 ns 9, 10, 11 tSk2 Chip to Chip Skew CL = 20pF, VID = 200mV (Note 6) 7.0 ns 9, 10, 11 tPLZ Disable Time Low to Z Input pulse = 0V to 3.0V, VO = VOL+ 0.5V, 20 ns 9, 10, 11 20 ns 9, 10, 11 RL = 1KΩ to VCC, VI = 1.5V tPHZ Disable Time High to Z Input pulse = 0V to 3.0V, VI = 1.5V, VO = VOH- 0.5V, RL = 1KΩ to Gnd 5 www.national.com DS90C032QML DS90C032 Electrical Characteristics DS90C032QML Symbol Max Units Subgroups 20 ns 9, 10, 11 20 ns 9, 10, 11 Max Units Subgroups EN, EN* = VCC or Gnd, Inputs Open 20 mA 1 EN, EN* = 2.4 or 0.5, Inputs Open 20 mA 1 EN = Gnd, EN* = VCC, Inputs Open 20 mA 1 Parameter tPZH Enable Time Z to High tPZL Enable Time Z to Low Conditions Notes Min Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, RL = 1KΩ to Gnd Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, RL = 1KΩ to VCC AC/DC Post Radiation Limits Symbol ICC ICCZ Parameter No Load Supply Current No Load Supply Current Receivers Disabled (Note 7) Conditions Notes Min Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Derate LCC @ 12.2mW/°C above +25°C. Derate ceramic flatpack @ 6.8mW/°C above +25°C Note 3: Human body model, 1.5 kΩ in series with 100 pF. Note 4: Tested during VOH / VOL tests. Note 5: Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event on the inputs. Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 7: Pre and post irradiation limits are identical to those listed under AC & DC electrical characteristics except as listed in the “Post Radiation Limits” table. Radiation end point limits for the noted parameters are guaranteed only for the conditions, as specified. www.national.com 6 DS90C032QML Parameter Measurement Information 20163703 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit 20163704 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms 20163705 CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = Gnd for tPZH and tPHZ measurements. FIGURE 3. Receiver TRI-STATE Delay Test Circuit 7 www.national.com DS90C032QML 20163706 FIGURE 4. Receiver TRI-STATE Delay Waveforms Typical Performance Characteristics Output High Voltage vs Power Supply Voltage Output High Voltage vs Ambient Temperature 20163708 www.national.com 20163709 8 DS90C032QML Output Low Voltage vs Power Supply Voltage Output Low Voltage vs Ambient Temperature 20163710 20163711 Output Short Circuit Current vs Power Supply Voltage Output Short Circuit Current vs Ambient Temperature 20163712 20163713 9 www.national.com DS90C032QML Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature 20163714 20163715 Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature 20163717 20163716 www.national.com 10 DS90C032QML Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature 20163718 20163719 Typical Application 20163707 FIGURE 5. Point-to-Point Application ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. Applications Information LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90C032 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to Receiver Failsafe The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal failsafe circuitry is designed to source/ sink a small amount of current, providing failsafe protection (a stable known state of HIGH output voltage) for floating and terminated (100Ω) receiver inputs in low noise environment (differential noise < 10mV). 1. Open Input Pins TheDS90C032 is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2. Terminated Input The DS90C032 requires external failsafe biasing for terminated input failsafe. Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the driver is in the following situations. Unplugged from the bus, or the driver output 11 www.national.com DS90C032QML is in TRI-STATE or in power-off condition. The use of external biasing resistors provide a small bias to set the differential input voltage while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the receiver may respond. To insure that any noise is seen as commonmode and not differential, a balanced interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common to both lines and rejected by the receivers. 3. Operation in environment with greater than 10mV differential noise National recommends external failsafe biasing on its LVDS receivers for a number of system level and signal quality rea- sons. First, only an application that requires failsafe biasing needs to employ it. Second, the amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific application. In applications in low noise environments, they may choose to use a very small bias if any. For applications with less balanced interconnects and/or in high noise environments they may choose to boost failsafe further. Nationals "LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and un-driven states, the common-mode modulation on the bus is held to a minimum. For additional Failsafe Biasing information, please refer to Application Note AN-1194 for more detail. Pin Descriptions Pin No. (SOIC) Name 2, 6, 10, 14 RI+ Description Non-inverting receiver input pin 1, 7, 9, 15 RI− Inverting receiver input pin 3, 5, 11, 13 RO Receiver output pin 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +5V ± 10% 8 Gnd Ground pin Radiation Environments Single Event Latch-Up and Functional Interrupt Careful consideration should be given to environmental conditions when using a product in a radiation environment. One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the Features on the front page is the maximum LET tested. A test report is available upon request. Total Ionizing Dose Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level specified in the Ordering Information table on the front page. Testing and qualification of these products is done on a wafer level according to MIL-STD-883G, Test Method 1019.7, Condition A and the “Extended room temperature anneal test” described in section 3.11 for application environment dose rates less than 0.19 rad(Si)/s. Wafer level TID data is available with lot shipments. www.national.com Single Event Upset A report on single event upset (SEU) is available upon request. 12 Released Revision Section Changes 03/01/06 A New Release, Corporate format 1 MDS data sheet converted into Corp. data sheet format. MNDS90C032-X-RH Rev 1B1 will be archived. 10/10/06 B Applications Information - Pg. 10, Physical Dimensions - Pg. 12 Deleted Shorted Inputs paragraph - page 10. Updated Physical Dimensions package drawings E20A, W16A to current revision - page 12. Revision A will be Archived. 05/07/07 C Receiver Table - Pg. 2, Application Information - Pg. 9 & 10 Deleted Full Fail-safe OPEN/SHORT or terminated Page 2. & Paragraph RECEIVER FAIL-SAFE and 1, 2, 3 - Page 9 & 10. Revision B will be Archived. 9/28/2010 D Order Information Table, General Copied general description and Receiver Failsafe Description, Applications Information section from commercial d/s DS90C032B, dated Sept. 2003. Removed Code K devices. Added Radiation Environments paragraph to data sheet. Revision C will be Archived. 13 www.national.com DS90C032QML Revision History DS90C032QML Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier NS Package Number E20A 16-Lead Ceramic Flatpack NS Package Number W16A www.national.com 14 DS90C032QML 16-Lead Ceramic SOIC NS Package Number WG16A 15 www.national.com DS90C032QML LVDS Quad CMOS Differential Line Receiver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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